1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/ptrace.h 4 * 5 * Copyright (C) 1996-2003 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASM_PTRACE_H 9 #define __ASM_PTRACE_H 10 11 #include <asm/cpufeature.h> 12 13 #include <uapi/asm/ptrace.h> 14 15 /* Current Exception Level values, as contained in CurrentEL */ 16 #define CurrentEL_EL1 (1 << 2) 17 #define CurrentEL_EL2 (2 << 2) 18 19 /* 20 * PMR values used to mask/unmask interrupts. 21 * 22 * GIC priority masking works as follows: if an IRQ's priority is a higher value 23 * than the value held in PMR, that IRQ is masked. Lowering the value of PMR 24 * means masking more IRQs (or at least that the same IRQs remain masked). 25 * 26 * To mask interrupts, we clear the most significant bit of PMR. 27 * 28 * Some code sections either automatically switch back to PSR.I or explicitly 29 * require to not use priority masking. If bit GIC_PRIO_PSR_I_SET is included 30 * in the the priority mask, it indicates that PSR.I should be set and 31 * interrupt disabling temporarily does not rely on IRQ priorities. 32 */ 33 #define GIC_PRIO_IRQON 0xe0 34 #define GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80) 35 #define GIC_PRIO_PSR_I_SET (1 << 4) 36 37 /* Additional SPSR bits not exposed in the UABI */ 38 #define PSR_MODE_THREAD_BIT (1 << 0) 39 #define PSR_IL_BIT (1 << 20) 40 41 /* AArch32-specific ptrace requests */ 42 #define COMPAT_PTRACE_GETREGS 12 43 #define COMPAT_PTRACE_SETREGS 13 44 #define COMPAT_PTRACE_GET_THREAD_AREA 22 45 #define COMPAT_PTRACE_SET_SYSCALL 23 46 #define COMPAT_PTRACE_GETVFPREGS 27 47 #define COMPAT_PTRACE_SETVFPREGS 28 48 #define COMPAT_PTRACE_GETHBPREGS 29 49 #define COMPAT_PTRACE_SETHBPREGS 30 50 51 /* SPSR_ELx bits for exceptions taken from AArch32 */ 52 #define PSR_AA32_MODE_MASK 0x0000001f 53 #define PSR_AA32_MODE_USR 0x00000010 54 #define PSR_AA32_MODE_FIQ 0x00000011 55 #define PSR_AA32_MODE_IRQ 0x00000012 56 #define PSR_AA32_MODE_SVC 0x00000013 57 #define PSR_AA32_MODE_ABT 0x00000017 58 #define PSR_AA32_MODE_HYP 0x0000001a 59 #define PSR_AA32_MODE_UND 0x0000001b 60 #define PSR_AA32_MODE_SYS 0x0000001f 61 #define PSR_AA32_T_BIT 0x00000020 62 #define PSR_AA32_F_BIT 0x00000040 63 #define PSR_AA32_I_BIT 0x00000080 64 #define PSR_AA32_A_BIT 0x00000100 65 #define PSR_AA32_E_BIT 0x00000200 66 #define PSR_AA32_PAN_BIT 0x00400000 67 #define PSR_AA32_SSBS_BIT 0x00800000 68 #define PSR_AA32_DIT_BIT 0x01000000 69 #define PSR_AA32_Q_BIT 0x08000000 70 #define PSR_AA32_V_BIT 0x10000000 71 #define PSR_AA32_C_BIT 0x20000000 72 #define PSR_AA32_Z_BIT 0x40000000 73 #define PSR_AA32_N_BIT 0x80000000 74 #define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */ 75 #define PSR_AA32_GE_MASK 0x000f0000 76 77 #ifdef CONFIG_CPU_BIG_ENDIAN 78 #define PSR_AA32_ENDSTATE PSR_AA32_E_BIT 79 #else 80 #define PSR_AA32_ENDSTATE 0 81 #endif 82 83 /* AArch32 CPSR bits, as seen in AArch32 */ 84 #define COMPAT_PSR_DIT_BIT 0x00200000 85 86 /* 87 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a 88 * process is located in memory. 89 */ 90 #define COMPAT_PT_TEXT_ADDR 0x10000 91 #define COMPAT_PT_DATA_ADDR 0x10004 92 #define COMPAT_PT_TEXT_END_ADDR 0x10008 93 94 /* 95 * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing 96 * a syscall -- i.e., its most recent entry into the kernel from 97 * userspace was not via SVC, or otherwise a tracer cancelled the syscall. 98 * 99 * This must have the value -1, for ABI compatibility with ptrace etc. 100 */ 101 #define NO_SYSCALL (-1) 102 103 #ifndef __ASSEMBLY__ 104 #include <linux/bug.h> 105 #include <linux/types.h> 106 107 /* sizeof(struct user) for AArch32 */ 108 #define COMPAT_USER_SZ 296 109 110 /* Architecturally defined mapping between AArch32 and AArch64 registers */ 111 #define compat_usr(x) regs[(x)] 112 #define compat_fp regs[11] 113 #define compat_sp regs[13] 114 #define compat_lr regs[14] 115 #define compat_sp_hyp regs[15] 116 #define compat_lr_irq regs[16] 117 #define compat_sp_irq regs[17] 118 #define compat_lr_svc regs[18] 119 #define compat_sp_svc regs[19] 120 #define compat_lr_abt regs[20] 121 #define compat_sp_abt regs[21] 122 #define compat_lr_und regs[22] 123 #define compat_sp_und regs[23] 124 #define compat_r8_fiq regs[24] 125 #define compat_r9_fiq regs[25] 126 #define compat_r10_fiq regs[26] 127 #define compat_r11_fiq regs[27] 128 #define compat_r12_fiq regs[28] 129 #define compat_sp_fiq regs[29] 130 #define compat_lr_fiq regs[30] 131 132 static inline unsigned long compat_psr_to_pstate(const unsigned long psr) 133 { 134 unsigned long pstate; 135 136 pstate = psr & ~COMPAT_PSR_DIT_BIT; 137 138 if (psr & COMPAT_PSR_DIT_BIT) 139 pstate |= PSR_AA32_DIT_BIT; 140 141 return pstate; 142 } 143 144 static inline unsigned long pstate_to_compat_psr(const unsigned long pstate) 145 { 146 unsigned long psr; 147 148 psr = pstate & ~PSR_AA32_DIT_BIT; 149 150 if (pstate & PSR_AA32_DIT_BIT) 151 psr |= COMPAT_PSR_DIT_BIT; 152 153 return psr; 154 } 155 156 /* 157 * This struct defines the way the registers are stored on the stack during an 158 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for 159 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs. 160 */ 161 struct pt_regs { 162 union { 163 struct user_pt_regs user_regs; 164 struct { 165 u64 regs[31]; 166 u64 sp; 167 u64 pc; 168 u64 pstate; 169 }; 170 }; 171 u64 orig_x0; 172 #ifdef __AARCH64EB__ 173 u32 unused2; 174 s32 syscallno; 175 #else 176 s32 syscallno; 177 u32 unused2; 178 #endif 179 180 u64 orig_addr_limit; 181 /* Only valid when ARM64_HAS_IRQ_PRIO_MASKING is enabled. */ 182 u64 pmr_save; 183 u64 stackframe[2]; 184 }; 185 186 static inline bool in_syscall(struct pt_regs const *regs) 187 { 188 return regs->syscallno != NO_SYSCALL; 189 } 190 191 static inline void forget_syscall(struct pt_regs *regs) 192 { 193 regs->syscallno = NO_SYSCALL; 194 } 195 196 #define MAX_REG_OFFSET offsetof(struct pt_regs, pstate) 197 198 #define arch_has_single_step() (1) 199 200 #ifdef CONFIG_COMPAT 201 #define compat_thumb_mode(regs) \ 202 (((regs)->pstate & PSR_AA32_T_BIT)) 203 #else 204 #define compat_thumb_mode(regs) (0) 205 #endif 206 207 #define user_mode(regs) \ 208 (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t) 209 210 #define compat_user_mode(regs) \ 211 (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \ 212 (PSR_MODE32_BIT | PSR_MODE_EL0t)) 213 214 #define processor_mode(regs) \ 215 ((regs)->pstate & PSR_MODE_MASK) 216 217 #define irqs_priority_unmasked(regs) \ 218 (system_uses_irq_prio_masking() ? \ 219 (regs)->pmr_save == GIC_PRIO_IRQON : \ 220 true) 221 222 #define interrupts_enabled(regs) \ 223 (!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs)) 224 225 #define fast_interrupts_enabled(regs) \ 226 (!((regs)->pstate & PSR_F_BIT)) 227 228 static inline unsigned long user_stack_pointer(struct pt_regs *regs) 229 { 230 if (compat_user_mode(regs)) 231 return regs->compat_sp; 232 return regs->sp; 233 } 234 235 extern int regs_query_register_offset(const char *name); 236 extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, 237 unsigned int n); 238 239 /** 240 * regs_get_register() - get register value from its offset 241 * @regs: pt_regs from which register value is gotten 242 * @offset: offset of the register. 243 * 244 * regs_get_register returns the value of a register whose offset from @regs. 245 * The @offset is the offset of the register in struct pt_regs. 246 * If @offset is bigger than MAX_REG_OFFSET, this returns 0. 247 */ 248 static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset) 249 { 250 u64 val = 0; 251 252 WARN_ON(offset & 7); 253 254 offset >>= 3; 255 switch (offset) { 256 case 0 ... 30: 257 val = regs->regs[offset]; 258 break; 259 case offsetof(struct pt_regs, sp) >> 3: 260 val = regs->sp; 261 break; 262 case offsetof(struct pt_regs, pc) >> 3: 263 val = regs->pc; 264 break; 265 case offsetof(struct pt_regs, pstate) >> 3: 266 val = regs->pstate; 267 break; 268 default: 269 val = 0; 270 } 271 272 return val; 273 } 274 275 /* 276 * Read a register given an architectural register index r. 277 * This handles the common case where 31 means XZR, not SP. 278 */ 279 static inline unsigned long pt_regs_read_reg(const struct pt_regs *regs, int r) 280 { 281 return (r == 31) ? 0 : regs->regs[r]; 282 } 283 284 /* 285 * Write a register given an architectural register index r. 286 * This handles the common case where 31 means XZR, not SP. 287 */ 288 static inline void pt_regs_write_reg(struct pt_regs *regs, int r, 289 unsigned long val) 290 { 291 if (r != 31) 292 regs->regs[r] = val; 293 } 294 295 /* Valid only for Kernel mode traps. */ 296 static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) 297 { 298 return regs->sp; 299 } 300 301 static inline unsigned long regs_return_value(struct pt_regs *regs) 302 { 303 return regs->regs[0]; 304 } 305 306 static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc) 307 { 308 regs->regs[0] = rc; 309 } 310 311 /** 312 * regs_get_kernel_argument() - get Nth function argument in kernel 313 * @regs: pt_regs of that context 314 * @n: function argument number (start from 0) 315 * 316 * regs_get_argument() returns @n th argument of the function call. 317 * 318 * Note that this chooses the most likely register mapping. In very rare 319 * cases this may not return correct data, for example, if one of the 320 * function parameters is 16 bytes or bigger. In such cases, we cannot 321 * get access the parameter correctly and the register assignment of 322 * subsequent parameters will be shifted. 323 */ 324 static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs, 325 unsigned int n) 326 { 327 #define NR_REG_ARGUMENTS 8 328 if (n < NR_REG_ARGUMENTS) 329 return pt_regs_read_reg(regs, n); 330 return 0; 331 } 332 333 /* We must avoid circular header include via sched.h */ 334 struct task_struct; 335 int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task); 336 337 static inline unsigned long instruction_pointer(struct pt_regs *regs) 338 { 339 return regs->pc; 340 } 341 static inline void instruction_pointer_set(struct pt_regs *regs, 342 unsigned long val) 343 { 344 regs->pc = val; 345 } 346 347 static inline unsigned long frame_pointer(struct pt_regs *regs) 348 { 349 return regs->regs[29]; 350 } 351 352 #define procedure_link_pointer(regs) ((regs)->regs[30]) 353 354 static inline void procedure_link_pointer_set(struct pt_regs *regs, 355 unsigned long val) 356 { 357 procedure_link_pointer(regs) = val; 358 } 359 360 extern unsigned long profile_pc(struct pt_regs *regs); 361 362 #endif /* __ASSEMBLY__ */ 363 #endif 364