1 /* 2 * Based on arch/arm/include/asm/processor.h 3 * 4 * Copyright (C) 1995-1999 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASM_PROCESSOR_H 20 #define __ASM_PROCESSOR_H 21 22 #define TASK_SIZE_64 (UL(1) << VA_BITS) 23 24 #define KERNEL_DS UL(-1) 25 #define USER_DS (TASK_SIZE_64 - 1) 26 27 #ifndef __ASSEMBLY__ 28 29 /* 30 * Default implementation of macro that returns current 31 * instruction pointer ("program counter"). 32 */ 33 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 34 35 #ifdef __KERNEL__ 36 37 #include <linux/build_bug.h> 38 #include <linux/cache.h> 39 #include <linux/init.h> 40 #include <linux/stddef.h> 41 #include <linux/string.h> 42 43 #include <asm/alternative.h> 44 #include <asm/cpufeature.h> 45 #include <asm/hw_breakpoint.h> 46 #include <asm/lse.h> 47 #include <asm/pgtable-hwdef.h> 48 #include <asm/ptrace.h> 49 #include <asm/types.h> 50 51 /* 52 * TASK_SIZE - the maximum size of a user space task. 53 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. 54 */ 55 #ifdef CONFIG_COMPAT 56 #define TASK_SIZE_32 UL(0x100000000) 57 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ 58 TASK_SIZE_32 : TASK_SIZE_64) 59 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ 60 TASK_SIZE_32 : TASK_SIZE_64) 61 #else 62 #define TASK_SIZE TASK_SIZE_64 63 #endif /* CONFIG_COMPAT */ 64 65 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4)) 66 67 #define STACK_TOP_MAX TASK_SIZE_64 68 #ifdef CONFIG_COMPAT 69 #define AARCH32_VECTORS_BASE 0xffff0000 70 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ 71 AARCH32_VECTORS_BASE : STACK_TOP_MAX) 72 #else 73 #define STACK_TOP STACK_TOP_MAX 74 #endif /* CONFIG_COMPAT */ 75 76 extern phys_addr_t arm64_dma_phys_limit; 77 #define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1) 78 79 struct debug_info { 80 #ifdef CONFIG_HAVE_HW_BREAKPOINT 81 /* Have we suspended stepping by a debugger? */ 82 int suspended_step; 83 /* Allow breakpoints and watchpoints to be disabled for this thread. */ 84 int bps_disabled; 85 int wps_disabled; 86 /* Hardware breakpoints pinned to this task. */ 87 struct perf_event *hbp_break[ARM_MAX_BRP]; 88 struct perf_event *hbp_watch[ARM_MAX_WRP]; 89 #endif 90 }; 91 92 struct cpu_context { 93 unsigned long x19; 94 unsigned long x20; 95 unsigned long x21; 96 unsigned long x22; 97 unsigned long x23; 98 unsigned long x24; 99 unsigned long x25; 100 unsigned long x26; 101 unsigned long x27; 102 unsigned long x28; 103 unsigned long fp; 104 unsigned long sp; 105 unsigned long pc; 106 }; 107 108 struct thread_struct { 109 struct cpu_context cpu_context; /* cpu context */ 110 111 /* 112 * Whitelisted fields for hardened usercopy: 113 * Maintainers must ensure manually that this contains no 114 * implicit padding. 115 */ 116 struct { 117 unsigned long tp_value; /* TLS register */ 118 unsigned long tp2_value; 119 struct user_fpsimd_state fpsimd_state; 120 } uw; 121 122 unsigned int fpsimd_cpu; 123 void *sve_state; /* SVE registers, if any */ 124 unsigned int sve_vl; /* SVE vector length */ 125 unsigned int sve_vl_onexec; /* SVE vl after next exec */ 126 unsigned long fault_address; /* fault info */ 127 unsigned long fault_code; /* ESR_EL1 value */ 128 struct debug_info debug; /* debugging */ 129 }; 130 131 static inline void arch_thread_struct_whitelist(unsigned long *offset, 132 unsigned long *size) 133 { 134 /* Verify that there is no padding among the whitelisted fields: */ 135 BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) != 136 sizeof_field(struct thread_struct, uw.tp_value) + 137 sizeof_field(struct thread_struct, uw.tp2_value) + 138 sizeof_field(struct thread_struct, uw.fpsimd_state)); 139 140 *offset = offsetof(struct thread_struct, uw); 141 *size = sizeof_field(struct thread_struct, uw); 142 } 143 144 #ifdef CONFIG_COMPAT 145 #define task_user_tls(t) \ 146 ({ \ 147 unsigned long *__tls; \ 148 if (is_compat_thread(task_thread_info(t))) \ 149 __tls = &(t)->thread.uw.tp2_value; \ 150 else \ 151 __tls = &(t)->thread.uw.tp_value; \ 152 __tls; \ 153 }) 154 #else 155 #define task_user_tls(t) (&(t)->thread.uw.tp_value) 156 #endif 157 158 /* Sync TPIDR_EL0 back to thread_struct for current */ 159 void tls_preserve_current_state(void); 160 161 #define INIT_THREAD { \ 162 .fpsimd_cpu = NR_CPUS, \ 163 } 164 165 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc) 166 { 167 memset(regs, 0, sizeof(*regs)); 168 forget_syscall(regs); 169 regs->pc = pc; 170 } 171 172 static inline void start_thread(struct pt_regs *regs, unsigned long pc, 173 unsigned long sp) 174 { 175 start_thread_common(regs, pc); 176 regs->pstate = PSR_MODE_EL0t; 177 regs->sp = sp; 178 } 179 180 #ifdef CONFIG_COMPAT 181 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc, 182 unsigned long sp) 183 { 184 start_thread_common(regs, pc); 185 regs->pstate = COMPAT_PSR_MODE_USR; 186 if (pc & 1) 187 regs->pstate |= COMPAT_PSR_T_BIT; 188 189 #ifdef __AARCH64EB__ 190 regs->pstate |= COMPAT_PSR_E_BIT; 191 #endif 192 193 regs->compat_sp = sp; 194 } 195 #endif 196 197 /* Forward declaration, a strange C thing */ 198 struct task_struct; 199 200 /* Free all resources held by a thread. */ 201 extern void release_thread(struct task_struct *); 202 203 unsigned long get_wchan(struct task_struct *p); 204 205 static inline void cpu_relax(void) 206 { 207 asm volatile("yield" ::: "memory"); 208 } 209 210 /* Thread switching */ 211 extern struct task_struct *cpu_switch_to(struct task_struct *prev, 212 struct task_struct *next); 213 214 #define task_pt_regs(p) \ 215 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1) 216 217 #define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc) 218 #define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk)) 219 220 /* 221 * Prefetching support 222 */ 223 #define ARCH_HAS_PREFETCH 224 static inline void prefetch(const void *ptr) 225 { 226 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr)); 227 } 228 229 #define ARCH_HAS_PREFETCHW 230 static inline void prefetchw(const void *ptr) 231 { 232 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr)); 233 } 234 235 #define ARCH_HAS_SPINLOCK_PREFETCH 236 static inline void spin_lock_prefetch(const void *ptr) 237 { 238 asm volatile(ARM64_LSE_ATOMIC_INSN( 239 "prfm pstl1strm, %a0", 240 "nop") : : "p" (ptr)); 241 } 242 243 #define HAVE_ARCH_PICK_MMAP_LAYOUT 244 245 #endif 246 247 void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused); 248 void cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused); 249 void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused); 250 251 extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */ 252 extern void __init minsigstksz_setup(void); 253 254 /* 255 * Not at the top of the file due to a direct #include cycle between 256 * <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include 257 * ensures that contents of processor.h are visible to fpsimd.h even if 258 * processor.h is included first. 259 * 260 * These prctl helpers are the only things in this file that require 261 * fpsimd.h. The core code expects them to be in this header. 262 */ 263 #include <asm/fpsimd.h> 264 265 /* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */ 266 #define SVE_SET_VL(arg) sve_set_current_vl(arg) 267 #define SVE_GET_VL() sve_get_current_vl() 268 269 #endif /* __ASSEMBLY__ */ 270 #endif /* __ASM_PROCESSOR_H */ 271