1 /* 2 * Based on arch/arm/include/asm/processor.h 3 * 4 * Copyright (C) 1995-1999 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASM_PROCESSOR_H 20 #define __ASM_PROCESSOR_H 21 22 #define TASK_SIZE_64 (UL(1) << VA_BITS) 23 24 #define KERNEL_DS UL(-1) 25 #define USER_DS (TASK_SIZE_64 - 1) 26 27 #ifndef __ASSEMBLY__ 28 29 /* 30 * Default implementation of macro that returns current 31 * instruction pointer ("program counter"). 32 */ 33 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 34 35 #ifdef __KERNEL__ 36 37 #include <linux/build_bug.h> 38 #include <linux/stddef.h> 39 #include <linux/string.h> 40 41 #include <asm/alternative.h> 42 #include <asm/cpufeature.h> 43 #include <asm/hw_breakpoint.h> 44 #include <asm/lse.h> 45 #include <asm/pgtable-hwdef.h> 46 #include <asm/ptrace.h> 47 #include <asm/types.h> 48 49 /* 50 * TASK_SIZE - the maximum size of a user space task. 51 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. 52 */ 53 #ifdef CONFIG_COMPAT 54 #define TASK_SIZE_32 UL(0x100000000) 55 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ 56 TASK_SIZE_32 : TASK_SIZE_64) 57 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ 58 TASK_SIZE_32 : TASK_SIZE_64) 59 #else 60 #define TASK_SIZE TASK_SIZE_64 61 #endif /* CONFIG_COMPAT */ 62 63 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4)) 64 65 #define STACK_TOP_MAX TASK_SIZE_64 66 #ifdef CONFIG_COMPAT 67 #define AARCH32_VECTORS_BASE 0xffff0000 68 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ 69 AARCH32_VECTORS_BASE : STACK_TOP_MAX) 70 #else 71 #define STACK_TOP STACK_TOP_MAX 72 #endif /* CONFIG_COMPAT */ 73 74 extern phys_addr_t arm64_dma_phys_limit; 75 #define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1) 76 77 struct debug_info { 78 #ifdef CONFIG_HAVE_HW_BREAKPOINT 79 /* Have we suspended stepping by a debugger? */ 80 int suspended_step; 81 /* Allow breakpoints and watchpoints to be disabled for this thread. */ 82 int bps_disabled; 83 int wps_disabled; 84 /* Hardware breakpoints pinned to this task. */ 85 struct perf_event *hbp_break[ARM_MAX_BRP]; 86 struct perf_event *hbp_watch[ARM_MAX_WRP]; 87 #endif 88 }; 89 90 struct cpu_context { 91 unsigned long x19; 92 unsigned long x20; 93 unsigned long x21; 94 unsigned long x22; 95 unsigned long x23; 96 unsigned long x24; 97 unsigned long x25; 98 unsigned long x26; 99 unsigned long x27; 100 unsigned long x28; 101 unsigned long fp; 102 unsigned long sp; 103 unsigned long pc; 104 }; 105 106 struct thread_struct { 107 struct cpu_context cpu_context; /* cpu context */ 108 109 /* 110 * Whitelisted fields for hardened usercopy: 111 * Maintainers must ensure manually that this contains no 112 * implicit padding. 113 */ 114 struct { 115 unsigned long tp_value; /* TLS register */ 116 unsigned long tp2_value; 117 struct user_fpsimd_state fpsimd_state; 118 } uw; 119 120 unsigned int fpsimd_cpu; 121 void *sve_state; /* SVE registers, if any */ 122 unsigned int sve_vl; /* SVE vector length */ 123 unsigned int sve_vl_onexec; /* SVE vl after next exec */ 124 unsigned long fault_address; /* fault info */ 125 unsigned long fault_code; /* ESR_EL1 value */ 126 struct debug_info debug; /* debugging */ 127 }; 128 129 static inline void arch_thread_struct_whitelist(unsigned long *offset, 130 unsigned long *size) 131 { 132 /* Verify that there is no padding among the whitelisted fields: */ 133 BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) != 134 sizeof_field(struct thread_struct, uw.tp_value) + 135 sizeof_field(struct thread_struct, uw.tp2_value) + 136 sizeof_field(struct thread_struct, uw.fpsimd_state)); 137 138 *offset = offsetof(struct thread_struct, uw); 139 *size = sizeof_field(struct thread_struct, uw); 140 } 141 142 #ifdef CONFIG_COMPAT 143 #define task_user_tls(t) \ 144 ({ \ 145 unsigned long *__tls; \ 146 if (is_compat_thread(task_thread_info(t))) \ 147 __tls = &(t)->thread.uw.tp2_value; \ 148 else \ 149 __tls = &(t)->thread.uw.tp_value; \ 150 __tls; \ 151 }) 152 #else 153 #define task_user_tls(t) (&(t)->thread.uw.tp_value) 154 #endif 155 156 /* Sync TPIDR_EL0 back to thread_struct for current */ 157 void tls_preserve_current_state(void); 158 159 #define INIT_THREAD { } 160 161 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc) 162 { 163 memset(regs, 0, sizeof(*regs)); 164 forget_syscall(regs); 165 regs->pc = pc; 166 } 167 168 static inline void start_thread(struct pt_regs *regs, unsigned long pc, 169 unsigned long sp) 170 { 171 start_thread_common(regs, pc); 172 regs->pstate = PSR_MODE_EL0t; 173 regs->sp = sp; 174 } 175 176 #ifdef CONFIG_COMPAT 177 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc, 178 unsigned long sp) 179 { 180 start_thread_common(regs, pc); 181 regs->pstate = COMPAT_PSR_MODE_USR; 182 if (pc & 1) 183 regs->pstate |= COMPAT_PSR_T_BIT; 184 185 #ifdef __AARCH64EB__ 186 regs->pstate |= COMPAT_PSR_E_BIT; 187 #endif 188 189 regs->compat_sp = sp; 190 } 191 #endif 192 193 /* Forward declaration, a strange C thing */ 194 struct task_struct; 195 196 /* Free all resources held by a thread. */ 197 extern void release_thread(struct task_struct *); 198 199 unsigned long get_wchan(struct task_struct *p); 200 201 static inline void cpu_relax(void) 202 { 203 asm volatile("yield" ::: "memory"); 204 } 205 206 /* Thread switching */ 207 extern struct task_struct *cpu_switch_to(struct task_struct *prev, 208 struct task_struct *next); 209 210 #define task_pt_regs(p) \ 211 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1) 212 213 #define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc) 214 #define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk)) 215 216 /* 217 * Prefetching support 218 */ 219 #define ARCH_HAS_PREFETCH 220 static inline void prefetch(const void *ptr) 221 { 222 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr)); 223 } 224 225 #define ARCH_HAS_PREFETCHW 226 static inline void prefetchw(const void *ptr) 227 { 228 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr)); 229 } 230 231 #define ARCH_HAS_SPINLOCK_PREFETCH 232 static inline void spin_lock_prefetch(const void *ptr) 233 { 234 asm volatile(ARM64_LSE_ATOMIC_INSN( 235 "prfm pstl1strm, %a0", 236 "nop") : : "p" (ptr)); 237 } 238 239 #define HAVE_ARCH_PICK_MMAP_LAYOUT 240 241 #endif 242 243 void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused); 244 void cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused); 245 void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused); 246 247 /* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */ 248 #define SVE_SET_VL(arg) sve_set_current_vl(arg) 249 #define SVE_GET_VL() sve_get_current_vl() 250 251 #endif /* __ASSEMBLY__ */ 252 #endif /* __ASM_PROCESSOR_H */ 253