1 /* 2 * Based on arch/arm/include/asm/processor.h 3 * 4 * Copyright (C) 1995-1999 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASM_PROCESSOR_H 20 #define __ASM_PROCESSOR_H 21 22 #define TASK_SIZE_64 (UL(1) << VA_BITS) 23 24 #define KERNEL_DS UL(-1) 25 #define USER_DS (TASK_SIZE_64 - 1) 26 27 #ifndef __ASSEMBLY__ 28 29 /* 30 * Default implementation of macro that returns current 31 * instruction pointer ("program counter"). 32 */ 33 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 34 35 #ifdef __KERNEL__ 36 37 #include <linux/string.h> 38 39 #include <asm/alternative.h> 40 #include <asm/fpsimd.h> 41 #include <asm/hw_breakpoint.h> 42 #include <asm/lse.h> 43 #include <asm/pgtable-hwdef.h> 44 #include <asm/ptrace.h> 45 #include <asm/types.h> 46 47 /* 48 * TASK_SIZE - the maximum size of a user space task. 49 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. 50 */ 51 #ifdef CONFIG_COMPAT 52 #define TASK_SIZE_32 UL(0x100000000) 53 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ 54 TASK_SIZE_32 : TASK_SIZE_64) 55 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ 56 TASK_SIZE_32 : TASK_SIZE_64) 57 #else 58 #define TASK_SIZE TASK_SIZE_64 59 #endif /* CONFIG_COMPAT */ 60 61 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4)) 62 63 #define STACK_TOP_MAX TASK_SIZE_64 64 #ifdef CONFIG_COMPAT 65 #define AARCH32_VECTORS_BASE 0xffff0000 66 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ 67 AARCH32_VECTORS_BASE : STACK_TOP_MAX) 68 #else 69 #define STACK_TOP STACK_TOP_MAX 70 #endif /* CONFIG_COMPAT */ 71 72 extern phys_addr_t arm64_dma_phys_limit; 73 #define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1) 74 75 struct debug_info { 76 #ifdef CONFIG_HAVE_HW_BREAKPOINT 77 /* Have we suspended stepping by a debugger? */ 78 int suspended_step; 79 /* Allow breakpoints and watchpoints to be disabled for this thread. */ 80 int bps_disabled; 81 int wps_disabled; 82 /* Hardware breakpoints pinned to this task. */ 83 struct perf_event *hbp_break[ARM_MAX_BRP]; 84 struct perf_event *hbp_watch[ARM_MAX_WRP]; 85 #endif 86 }; 87 88 struct cpu_context { 89 unsigned long x19; 90 unsigned long x20; 91 unsigned long x21; 92 unsigned long x22; 93 unsigned long x23; 94 unsigned long x24; 95 unsigned long x25; 96 unsigned long x26; 97 unsigned long x27; 98 unsigned long x28; 99 unsigned long fp; 100 unsigned long sp; 101 unsigned long pc; 102 }; 103 104 struct thread_struct { 105 struct cpu_context cpu_context; /* cpu context */ 106 unsigned long tp_value; /* TLS register */ 107 #ifdef CONFIG_COMPAT 108 unsigned long tp2_value; 109 #endif 110 struct fpsimd_state fpsimd_state; 111 void *sve_state; /* SVE registers, if any */ 112 unsigned int sve_vl; /* SVE vector length */ 113 unsigned int sve_vl_onexec; /* SVE vl after next exec */ 114 unsigned long fault_address; /* fault info */ 115 unsigned long fault_code; /* ESR_EL1 value */ 116 struct debug_info debug; /* debugging */ 117 }; 118 119 /* 120 * Everything usercopied to/from thread_struct is statically-sized, so 121 * no hardened usercopy whitelist is needed. 122 */ 123 static inline void arch_thread_struct_whitelist(unsigned long *offset, 124 unsigned long *size) 125 { 126 *offset = *size = 0; 127 } 128 129 #ifdef CONFIG_COMPAT 130 #define task_user_tls(t) \ 131 ({ \ 132 unsigned long *__tls; \ 133 if (is_compat_thread(task_thread_info(t))) \ 134 __tls = &(t)->thread.tp2_value; \ 135 else \ 136 __tls = &(t)->thread.tp_value; \ 137 __tls; \ 138 }) 139 #else 140 #define task_user_tls(t) (&(t)->thread.tp_value) 141 #endif 142 143 /* Sync TPIDR_EL0 back to thread_struct for current */ 144 void tls_preserve_current_state(void); 145 146 #define INIT_THREAD { } 147 148 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc) 149 { 150 memset(regs, 0, sizeof(*regs)); 151 forget_syscall(regs); 152 regs->pc = pc; 153 } 154 155 static inline void start_thread(struct pt_regs *regs, unsigned long pc, 156 unsigned long sp) 157 { 158 start_thread_common(regs, pc); 159 regs->pstate = PSR_MODE_EL0t; 160 regs->sp = sp; 161 } 162 163 #ifdef CONFIG_COMPAT 164 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc, 165 unsigned long sp) 166 { 167 start_thread_common(regs, pc); 168 regs->pstate = COMPAT_PSR_MODE_USR; 169 if (pc & 1) 170 regs->pstate |= COMPAT_PSR_T_BIT; 171 172 #ifdef __AARCH64EB__ 173 regs->pstate |= COMPAT_PSR_E_BIT; 174 #endif 175 176 regs->compat_sp = sp; 177 } 178 #endif 179 180 /* Forward declaration, a strange C thing */ 181 struct task_struct; 182 183 /* Free all resources held by a thread. */ 184 extern void release_thread(struct task_struct *); 185 186 unsigned long get_wchan(struct task_struct *p); 187 188 static inline void cpu_relax(void) 189 { 190 asm volatile("yield" ::: "memory"); 191 } 192 193 /* Thread switching */ 194 extern struct task_struct *cpu_switch_to(struct task_struct *prev, 195 struct task_struct *next); 196 197 #define task_pt_regs(p) \ 198 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1) 199 200 #define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc) 201 #define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk)) 202 203 /* 204 * Prefetching support 205 */ 206 #define ARCH_HAS_PREFETCH 207 static inline void prefetch(const void *ptr) 208 { 209 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr)); 210 } 211 212 #define ARCH_HAS_PREFETCHW 213 static inline void prefetchw(const void *ptr) 214 { 215 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr)); 216 } 217 218 #define ARCH_HAS_SPINLOCK_PREFETCH 219 static inline void spin_lock_prefetch(const void *ptr) 220 { 221 asm volatile(ARM64_LSE_ATOMIC_INSN( 222 "prfm pstl1strm, %a0", 223 "nop") : : "p" (ptr)); 224 } 225 226 #define HAVE_ARCH_PICK_MMAP_LAYOUT 227 228 #endif 229 230 int cpu_enable_pan(void *__unused); 231 int cpu_enable_cache_maint_trap(void *__unused); 232 int cpu_clear_disr(void *__unused); 233 234 /* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */ 235 #define SVE_SET_VL(arg) sve_set_current_vl(arg) 236 #define SVE_GET_VL() sve_get_current_vl() 237 238 #endif /* __ASSEMBLY__ */ 239 #endif /* __ASM_PROCESSOR_H */ 240