1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/processor.h 4 * 5 * Copyright (C) 1995-1999 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASM_PROCESSOR_H 9 #define __ASM_PROCESSOR_H 10 11 /* 12 * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is 13 * no point in shifting all network buffers by 2 bytes just to make some IP 14 * header fields appear aligned in memory, potentially sacrificing some DMA 15 * performance on some platforms. 16 */ 17 #define NET_IP_ALIGN 0 18 19 #define MTE_CTRL_GCR_USER_EXCL_SHIFT 0 20 #define MTE_CTRL_GCR_USER_EXCL_MASK 0xffff 21 22 #define MTE_CTRL_TCF_SYNC (1UL << 16) 23 #define MTE_CTRL_TCF_ASYNC (1UL << 17) 24 #define MTE_CTRL_TCF_ASYMM (1UL << 18) 25 26 #ifndef __ASSEMBLY__ 27 28 #include <linux/build_bug.h> 29 #include <linux/cache.h> 30 #include <linux/init.h> 31 #include <linux/stddef.h> 32 #include <linux/string.h> 33 #include <linux/thread_info.h> 34 35 #include <vdso/processor.h> 36 37 #include <asm/alternative.h> 38 #include <asm/cpufeature.h> 39 #include <asm/hw_breakpoint.h> 40 #include <asm/kasan.h> 41 #include <asm/lse.h> 42 #include <asm/pgtable-hwdef.h> 43 #include <asm/pointer_auth.h> 44 #include <asm/ptrace.h> 45 #include <asm/spectre.h> 46 #include <asm/types.h> 47 48 /* 49 * TASK_SIZE - the maximum size of a user space task. 50 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. 51 */ 52 53 #define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN) 54 #define TASK_SIZE_64 (UL(1) << vabits_actual) 55 #define TASK_SIZE_MAX (UL(1) << VA_BITS) 56 57 #ifdef CONFIG_COMPAT 58 #if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS) 59 /* 60 * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied 61 * by the compat vectors page. 62 */ 63 #define TASK_SIZE_32 UL(0x100000000) 64 #else 65 #define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE) 66 #endif /* CONFIG_ARM64_64K_PAGES */ 67 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ 68 TASK_SIZE_32 : TASK_SIZE_64) 69 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ 70 TASK_SIZE_32 : TASK_SIZE_64) 71 #define DEFAULT_MAP_WINDOW (test_thread_flag(TIF_32BIT) ? \ 72 TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64) 73 #else 74 #define TASK_SIZE TASK_SIZE_64 75 #define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64 76 #endif /* CONFIG_COMPAT */ 77 78 #ifdef CONFIG_ARM64_FORCE_52BIT 79 #define STACK_TOP_MAX TASK_SIZE_64 80 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4)) 81 #else 82 #define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64 83 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4)) 84 #endif /* CONFIG_ARM64_FORCE_52BIT */ 85 86 #ifdef CONFIG_COMPAT 87 #define AARCH32_VECTORS_BASE 0xffff0000 88 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ 89 AARCH32_VECTORS_BASE : STACK_TOP_MAX) 90 #else 91 #define STACK_TOP STACK_TOP_MAX 92 #endif /* CONFIG_COMPAT */ 93 94 #ifndef CONFIG_ARM64_FORCE_52BIT 95 #define arch_get_mmap_end(addr) ((addr > DEFAULT_MAP_WINDOW) ? TASK_SIZE :\ 96 DEFAULT_MAP_WINDOW) 97 98 #define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \ 99 base + TASK_SIZE - DEFAULT_MAP_WINDOW :\ 100 base) 101 #endif /* CONFIG_ARM64_FORCE_52BIT */ 102 103 extern phys_addr_t arm64_dma_phys_limit; 104 #define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1) 105 106 struct debug_info { 107 #ifdef CONFIG_HAVE_HW_BREAKPOINT 108 /* Have we suspended stepping by a debugger? */ 109 int suspended_step; 110 /* Allow breakpoints and watchpoints to be disabled for this thread. */ 111 int bps_disabled; 112 int wps_disabled; 113 /* Hardware breakpoints pinned to this task. */ 114 struct perf_event *hbp_break[ARM_MAX_BRP]; 115 struct perf_event *hbp_watch[ARM_MAX_WRP]; 116 #endif 117 }; 118 119 enum vec_type { 120 ARM64_VEC_SVE = 0, 121 ARM64_VEC_MAX, 122 }; 123 124 struct cpu_context { 125 unsigned long x19; 126 unsigned long x20; 127 unsigned long x21; 128 unsigned long x22; 129 unsigned long x23; 130 unsigned long x24; 131 unsigned long x25; 132 unsigned long x26; 133 unsigned long x27; 134 unsigned long x28; 135 unsigned long fp; 136 unsigned long sp; 137 unsigned long pc; 138 }; 139 140 struct thread_struct { 141 struct cpu_context cpu_context; /* cpu context */ 142 143 /* 144 * Whitelisted fields for hardened usercopy: 145 * Maintainers must ensure manually that this contains no 146 * implicit padding. 147 */ 148 struct { 149 unsigned long tp_value; /* TLS register */ 150 unsigned long tp2_value; 151 struct user_fpsimd_state fpsimd_state; 152 } uw; 153 154 unsigned int fpsimd_cpu; 155 void *sve_state; /* SVE registers, if any */ 156 unsigned int vl[ARM64_VEC_MAX]; /* vector length */ 157 unsigned int vl_onexec[ARM64_VEC_MAX]; /* vl after next exec */ 158 unsigned long fault_address; /* fault info */ 159 unsigned long fault_code; /* ESR_EL1 value */ 160 struct debug_info debug; /* debugging */ 161 #ifdef CONFIG_ARM64_PTR_AUTH 162 struct ptrauth_keys_user keys_user; 163 #ifdef CONFIG_ARM64_PTR_AUTH_KERNEL 164 struct ptrauth_keys_kernel keys_kernel; 165 #endif 166 #endif 167 #ifdef CONFIG_ARM64_MTE 168 u64 mte_ctrl; 169 #endif 170 u64 sctlr_user; 171 }; 172 173 static inline unsigned int thread_get_vl(struct thread_struct *thread, 174 enum vec_type type) 175 { 176 return thread->vl[type]; 177 } 178 179 static inline unsigned int thread_get_sve_vl(struct thread_struct *thread) 180 { 181 return thread_get_vl(thread, ARM64_VEC_SVE); 182 } 183 184 unsigned int task_get_vl(const struct task_struct *task, enum vec_type type); 185 void task_set_vl(struct task_struct *task, enum vec_type type, 186 unsigned long vl); 187 void task_set_vl_onexec(struct task_struct *task, enum vec_type type, 188 unsigned long vl); 189 unsigned int task_get_vl_onexec(const struct task_struct *task, 190 enum vec_type type); 191 192 static inline unsigned int task_get_sve_vl(const struct task_struct *task) 193 { 194 return task_get_vl(task, ARM64_VEC_SVE); 195 } 196 197 static inline void task_set_sve_vl(struct task_struct *task, unsigned long vl) 198 { 199 task_set_vl(task, ARM64_VEC_SVE, vl); 200 } 201 202 static inline unsigned int task_get_sve_vl_onexec(const struct task_struct *task) 203 { 204 return task_get_vl_onexec(task, ARM64_VEC_SVE); 205 } 206 207 static inline void task_set_sve_vl_onexec(struct task_struct *task, 208 unsigned long vl) 209 { 210 task_set_vl_onexec(task, ARM64_VEC_SVE, vl); 211 } 212 213 #define SCTLR_USER_MASK \ 214 (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \ 215 SCTLR_EL1_TCF0_MASK) 216 217 static inline void arch_thread_struct_whitelist(unsigned long *offset, 218 unsigned long *size) 219 { 220 /* Verify that there is no padding among the whitelisted fields: */ 221 BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) != 222 sizeof_field(struct thread_struct, uw.tp_value) + 223 sizeof_field(struct thread_struct, uw.tp2_value) + 224 sizeof_field(struct thread_struct, uw.fpsimd_state)); 225 226 *offset = offsetof(struct thread_struct, uw); 227 *size = sizeof_field(struct thread_struct, uw); 228 } 229 230 #ifdef CONFIG_COMPAT 231 #define task_user_tls(t) \ 232 ({ \ 233 unsigned long *__tls; \ 234 if (is_compat_thread(task_thread_info(t))) \ 235 __tls = &(t)->thread.uw.tp2_value; \ 236 else \ 237 __tls = &(t)->thread.uw.tp_value; \ 238 __tls; \ 239 }) 240 #else 241 #define task_user_tls(t) (&(t)->thread.uw.tp_value) 242 #endif 243 244 /* Sync TPIDR_EL0 back to thread_struct for current */ 245 void tls_preserve_current_state(void); 246 247 #define INIT_THREAD { \ 248 .fpsimd_cpu = NR_CPUS, \ 249 } 250 251 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc) 252 { 253 memset(regs, 0, sizeof(*regs)); 254 forget_syscall(regs); 255 regs->pc = pc; 256 257 if (system_uses_irq_prio_masking()) 258 regs->pmr_save = GIC_PRIO_IRQON; 259 } 260 261 static inline void start_thread(struct pt_regs *regs, unsigned long pc, 262 unsigned long sp) 263 { 264 start_thread_common(regs, pc); 265 regs->pstate = PSR_MODE_EL0t; 266 spectre_v4_enable_task_mitigation(current); 267 regs->sp = sp; 268 } 269 270 #ifdef CONFIG_COMPAT 271 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc, 272 unsigned long sp) 273 { 274 start_thread_common(regs, pc); 275 regs->pstate = PSR_AA32_MODE_USR; 276 if (pc & 1) 277 regs->pstate |= PSR_AA32_T_BIT; 278 279 #ifdef __AARCH64EB__ 280 regs->pstate |= PSR_AA32_E_BIT; 281 #endif 282 283 spectre_v4_enable_task_mitigation(current); 284 regs->compat_sp = sp; 285 } 286 #endif 287 288 static inline bool is_ttbr0_addr(unsigned long addr) 289 { 290 /* entry assembly clears tags for TTBR0 addrs */ 291 return addr < TASK_SIZE; 292 } 293 294 static inline bool is_ttbr1_addr(unsigned long addr) 295 { 296 /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */ 297 return arch_kasan_reset_tag(addr) >= PAGE_OFFSET; 298 } 299 300 /* Forward declaration, a strange C thing */ 301 struct task_struct; 302 303 /* Free all resources held by a thread. */ 304 extern void release_thread(struct task_struct *); 305 306 unsigned long __get_wchan(struct task_struct *p); 307 308 void update_sctlr_el1(u64 sctlr); 309 310 /* Thread switching */ 311 extern struct task_struct *cpu_switch_to(struct task_struct *prev, 312 struct task_struct *next); 313 314 #define task_pt_regs(p) \ 315 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1) 316 317 #define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc) 318 #define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk)) 319 320 /* 321 * Prefetching support 322 */ 323 #define ARCH_HAS_PREFETCH 324 static inline void prefetch(const void *ptr) 325 { 326 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr)); 327 } 328 329 #define ARCH_HAS_PREFETCHW 330 static inline void prefetchw(const void *ptr) 331 { 332 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr)); 333 } 334 335 #define ARCH_HAS_SPINLOCK_PREFETCH 336 static inline void spin_lock_prefetch(const void *ptr) 337 { 338 asm volatile(ARM64_LSE_ATOMIC_INSN( 339 "prfm pstl1strm, %a0", 340 "nop") : : "p" (ptr)); 341 } 342 343 extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */ 344 extern void __init minsigstksz_setup(void); 345 346 /* 347 * Not at the top of the file due to a direct #include cycle between 348 * <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include 349 * ensures that contents of processor.h are visible to fpsimd.h even if 350 * processor.h is included first. 351 * 352 * These prctl helpers are the only things in this file that require 353 * fpsimd.h. The core code expects them to be in this header. 354 */ 355 #include <asm/fpsimd.h> 356 357 /* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */ 358 #define SVE_SET_VL(arg) sve_set_current_vl(arg) 359 #define SVE_GET_VL() sve_get_current_vl() 360 361 /* PR_PAC_RESET_KEYS prctl */ 362 #define PAC_RESET_KEYS(tsk, arg) ptrauth_prctl_reset_keys(tsk, arg) 363 364 /* PR_PAC_{SET,GET}_ENABLED_KEYS prctl */ 365 #define PAC_SET_ENABLED_KEYS(tsk, keys, enabled) \ 366 ptrauth_set_enabled_keys(tsk, keys, enabled) 367 #define PAC_GET_ENABLED_KEYS(tsk) ptrauth_get_enabled_keys(tsk) 368 369 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 370 /* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */ 371 long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg); 372 long get_tagged_addr_ctrl(struct task_struct *task); 373 #define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg) 374 #define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current) 375 #endif 376 377 /* 378 * For CONFIG_GCC_PLUGIN_STACKLEAK 379 * 380 * These need to be macros because otherwise we get stuck in a nightmare 381 * of header definitions for the use of task_stack_page. 382 */ 383 384 #define current_top_of_stack() \ 385 ({ \ 386 struct stack_info _info; \ 387 BUG_ON(!on_accessible_stack(current, current_stack_pointer, 1, &_info)); \ 388 _info.high; \ 389 }) 390 #define on_thread_stack() (on_task_stack(current, current_stack_pointer, 1, NULL)) 391 392 #endif /* __ASSEMBLY__ */ 393 #endif /* __ASM_PROCESSOR_H */ 394