1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/processor.h 4 * 5 * Copyright (C) 1995-1999 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASM_PROCESSOR_H 9 #define __ASM_PROCESSOR_H 10 11 /* 12 * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is 13 * no point in shifting all network buffers by 2 bytes just to make some IP 14 * header fields appear aligned in memory, potentially sacrificing some DMA 15 * performance on some platforms. 16 */ 17 #define NET_IP_ALIGN 0 18 19 #define MTE_CTRL_GCR_USER_EXCL_SHIFT 0 20 #define MTE_CTRL_GCR_USER_EXCL_MASK 0xffff 21 22 #define MTE_CTRL_TCF_SYNC (1UL << 16) 23 #define MTE_CTRL_TCF_ASYNC (1UL << 17) 24 25 #ifndef __ASSEMBLY__ 26 27 #include <linux/build_bug.h> 28 #include <linux/cache.h> 29 #include <linux/init.h> 30 #include <linux/stddef.h> 31 #include <linux/string.h> 32 #include <linux/thread_info.h> 33 34 #include <vdso/processor.h> 35 36 #include <asm/alternative.h> 37 #include <asm/cpufeature.h> 38 #include <asm/hw_breakpoint.h> 39 #include <asm/kasan.h> 40 #include <asm/lse.h> 41 #include <asm/pgtable-hwdef.h> 42 #include <asm/pointer_auth.h> 43 #include <asm/ptrace.h> 44 #include <asm/spectre.h> 45 #include <asm/types.h> 46 47 /* 48 * TASK_SIZE - the maximum size of a user space task. 49 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. 50 */ 51 52 #define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN) 53 #define TASK_SIZE_64 (UL(1) << vabits_actual) 54 #define TASK_SIZE_MAX (UL(1) << VA_BITS) 55 56 #ifdef CONFIG_COMPAT 57 #if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS) 58 /* 59 * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied 60 * by the compat vectors page. 61 */ 62 #define TASK_SIZE_32 UL(0x100000000) 63 #else 64 #define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE) 65 #endif /* CONFIG_ARM64_64K_PAGES */ 66 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ 67 TASK_SIZE_32 : TASK_SIZE_64) 68 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ 69 TASK_SIZE_32 : TASK_SIZE_64) 70 #define DEFAULT_MAP_WINDOW (test_thread_flag(TIF_32BIT) ? \ 71 TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64) 72 #else 73 #define TASK_SIZE TASK_SIZE_64 74 #define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64 75 #endif /* CONFIG_COMPAT */ 76 77 #ifdef CONFIG_ARM64_FORCE_52BIT 78 #define STACK_TOP_MAX TASK_SIZE_64 79 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4)) 80 #else 81 #define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64 82 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4)) 83 #endif /* CONFIG_ARM64_FORCE_52BIT */ 84 85 #ifdef CONFIG_COMPAT 86 #define AARCH32_VECTORS_BASE 0xffff0000 87 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ 88 AARCH32_VECTORS_BASE : STACK_TOP_MAX) 89 #else 90 #define STACK_TOP STACK_TOP_MAX 91 #endif /* CONFIG_COMPAT */ 92 93 #ifndef CONFIG_ARM64_FORCE_52BIT 94 #define arch_get_mmap_end(addr) ((addr > DEFAULT_MAP_WINDOW) ? TASK_SIZE :\ 95 DEFAULT_MAP_WINDOW) 96 97 #define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \ 98 base + TASK_SIZE - DEFAULT_MAP_WINDOW :\ 99 base) 100 #endif /* CONFIG_ARM64_FORCE_52BIT */ 101 102 extern phys_addr_t arm64_dma_phys_limit; 103 #define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1) 104 105 struct debug_info { 106 #ifdef CONFIG_HAVE_HW_BREAKPOINT 107 /* Have we suspended stepping by a debugger? */ 108 int suspended_step; 109 /* Allow breakpoints and watchpoints to be disabled for this thread. */ 110 int bps_disabled; 111 int wps_disabled; 112 /* Hardware breakpoints pinned to this task. */ 113 struct perf_event *hbp_break[ARM_MAX_BRP]; 114 struct perf_event *hbp_watch[ARM_MAX_WRP]; 115 #endif 116 }; 117 118 enum vec_type { 119 ARM64_VEC_SVE = 0, 120 ARM64_VEC_MAX, 121 }; 122 123 struct cpu_context { 124 unsigned long x19; 125 unsigned long x20; 126 unsigned long x21; 127 unsigned long x22; 128 unsigned long x23; 129 unsigned long x24; 130 unsigned long x25; 131 unsigned long x26; 132 unsigned long x27; 133 unsigned long x28; 134 unsigned long fp; 135 unsigned long sp; 136 unsigned long pc; 137 }; 138 139 struct thread_struct { 140 struct cpu_context cpu_context; /* cpu context */ 141 142 /* 143 * Whitelisted fields for hardened usercopy: 144 * Maintainers must ensure manually that this contains no 145 * implicit padding. 146 */ 147 struct { 148 unsigned long tp_value; /* TLS register */ 149 unsigned long tp2_value; 150 struct user_fpsimd_state fpsimd_state; 151 } uw; 152 153 unsigned int fpsimd_cpu; 154 void *sve_state; /* SVE registers, if any */ 155 unsigned int vl[ARM64_VEC_MAX]; /* vector length */ 156 unsigned int vl_onexec[ARM64_VEC_MAX]; /* vl after next exec */ 157 unsigned long fault_address; /* fault info */ 158 unsigned long fault_code; /* ESR_EL1 value */ 159 struct debug_info debug; /* debugging */ 160 #ifdef CONFIG_ARM64_PTR_AUTH 161 struct ptrauth_keys_user keys_user; 162 #ifdef CONFIG_ARM64_PTR_AUTH_KERNEL 163 struct ptrauth_keys_kernel keys_kernel; 164 #endif 165 #endif 166 #ifdef CONFIG_ARM64_MTE 167 u64 mte_ctrl; 168 #endif 169 u64 sctlr_user; 170 }; 171 172 static inline unsigned int thread_get_vl(struct thread_struct *thread, 173 enum vec_type type) 174 { 175 return thread->vl[type]; 176 } 177 178 static inline unsigned int thread_get_sve_vl(struct thread_struct *thread) 179 { 180 return thread_get_vl(thread, ARM64_VEC_SVE); 181 } 182 183 unsigned int task_get_vl(const struct task_struct *task, enum vec_type type); 184 void task_set_vl(struct task_struct *task, enum vec_type type, 185 unsigned long vl); 186 void task_set_vl_onexec(struct task_struct *task, enum vec_type type, 187 unsigned long vl); 188 unsigned int task_get_vl_onexec(const struct task_struct *task, 189 enum vec_type type); 190 191 static inline unsigned int task_get_sve_vl(const struct task_struct *task) 192 { 193 return task_get_vl(task, ARM64_VEC_SVE); 194 } 195 196 static inline void task_set_sve_vl(struct task_struct *task, unsigned long vl) 197 { 198 task_set_vl(task, ARM64_VEC_SVE, vl); 199 } 200 201 static inline unsigned int task_get_sve_vl_onexec(const struct task_struct *task) 202 { 203 return task_get_vl_onexec(task, ARM64_VEC_SVE); 204 } 205 206 static inline void task_set_sve_vl_onexec(struct task_struct *task, 207 unsigned long vl) 208 { 209 task_set_vl_onexec(task, ARM64_VEC_SVE, vl); 210 } 211 212 #define SCTLR_USER_MASK \ 213 (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \ 214 SCTLR_EL1_TCF0_MASK) 215 216 static inline void arch_thread_struct_whitelist(unsigned long *offset, 217 unsigned long *size) 218 { 219 /* Verify that there is no padding among the whitelisted fields: */ 220 BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) != 221 sizeof_field(struct thread_struct, uw.tp_value) + 222 sizeof_field(struct thread_struct, uw.tp2_value) + 223 sizeof_field(struct thread_struct, uw.fpsimd_state)); 224 225 *offset = offsetof(struct thread_struct, uw); 226 *size = sizeof_field(struct thread_struct, uw); 227 } 228 229 #ifdef CONFIG_COMPAT 230 #define task_user_tls(t) \ 231 ({ \ 232 unsigned long *__tls; \ 233 if (is_compat_thread(task_thread_info(t))) \ 234 __tls = &(t)->thread.uw.tp2_value; \ 235 else \ 236 __tls = &(t)->thread.uw.tp_value; \ 237 __tls; \ 238 }) 239 #else 240 #define task_user_tls(t) (&(t)->thread.uw.tp_value) 241 #endif 242 243 /* Sync TPIDR_EL0 back to thread_struct for current */ 244 void tls_preserve_current_state(void); 245 246 #define INIT_THREAD { \ 247 .fpsimd_cpu = NR_CPUS, \ 248 } 249 250 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc) 251 { 252 memset(regs, 0, sizeof(*regs)); 253 forget_syscall(regs); 254 regs->pc = pc; 255 256 if (system_uses_irq_prio_masking()) 257 regs->pmr_save = GIC_PRIO_IRQON; 258 } 259 260 static inline void start_thread(struct pt_regs *regs, unsigned long pc, 261 unsigned long sp) 262 { 263 start_thread_common(regs, pc); 264 regs->pstate = PSR_MODE_EL0t; 265 spectre_v4_enable_task_mitigation(current); 266 regs->sp = sp; 267 } 268 269 #ifdef CONFIG_COMPAT 270 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc, 271 unsigned long sp) 272 { 273 start_thread_common(regs, pc); 274 regs->pstate = PSR_AA32_MODE_USR; 275 if (pc & 1) 276 regs->pstate |= PSR_AA32_T_BIT; 277 278 #ifdef __AARCH64EB__ 279 regs->pstate |= PSR_AA32_E_BIT; 280 #endif 281 282 spectre_v4_enable_task_mitigation(current); 283 regs->compat_sp = sp; 284 } 285 #endif 286 287 static inline bool is_ttbr0_addr(unsigned long addr) 288 { 289 /* entry assembly clears tags for TTBR0 addrs */ 290 return addr < TASK_SIZE; 291 } 292 293 static inline bool is_ttbr1_addr(unsigned long addr) 294 { 295 /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */ 296 return arch_kasan_reset_tag(addr) >= PAGE_OFFSET; 297 } 298 299 /* Forward declaration, a strange C thing */ 300 struct task_struct; 301 302 /* Free all resources held by a thread. */ 303 extern void release_thread(struct task_struct *); 304 305 unsigned long __get_wchan(struct task_struct *p); 306 307 void update_sctlr_el1(u64 sctlr); 308 309 /* Thread switching */ 310 extern struct task_struct *cpu_switch_to(struct task_struct *prev, 311 struct task_struct *next); 312 313 #define task_pt_regs(p) \ 314 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1) 315 316 #define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc) 317 #define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk)) 318 319 /* 320 * Prefetching support 321 */ 322 #define ARCH_HAS_PREFETCH 323 static inline void prefetch(const void *ptr) 324 { 325 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr)); 326 } 327 328 #define ARCH_HAS_PREFETCHW 329 static inline void prefetchw(const void *ptr) 330 { 331 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr)); 332 } 333 334 #define ARCH_HAS_SPINLOCK_PREFETCH 335 static inline void spin_lock_prefetch(const void *ptr) 336 { 337 asm volatile(ARM64_LSE_ATOMIC_INSN( 338 "prfm pstl1strm, %a0", 339 "nop") : : "p" (ptr)); 340 } 341 342 extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */ 343 extern void __init minsigstksz_setup(void); 344 345 /* 346 * Not at the top of the file due to a direct #include cycle between 347 * <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include 348 * ensures that contents of processor.h are visible to fpsimd.h even if 349 * processor.h is included first. 350 * 351 * These prctl helpers are the only things in this file that require 352 * fpsimd.h. The core code expects them to be in this header. 353 */ 354 #include <asm/fpsimd.h> 355 356 /* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */ 357 #define SVE_SET_VL(arg) sve_set_current_vl(arg) 358 #define SVE_GET_VL() sve_get_current_vl() 359 360 /* PR_PAC_RESET_KEYS prctl */ 361 #define PAC_RESET_KEYS(tsk, arg) ptrauth_prctl_reset_keys(tsk, arg) 362 363 /* PR_PAC_{SET,GET}_ENABLED_KEYS prctl */ 364 #define PAC_SET_ENABLED_KEYS(tsk, keys, enabled) \ 365 ptrauth_set_enabled_keys(tsk, keys, enabled) 366 #define PAC_GET_ENABLED_KEYS(tsk) ptrauth_get_enabled_keys(tsk) 367 368 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 369 /* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */ 370 long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg); 371 long get_tagged_addr_ctrl(struct task_struct *task); 372 #define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg) 373 #define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current) 374 #endif 375 376 /* 377 * For CONFIG_GCC_PLUGIN_STACKLEAK 378 * 379 * These need to be macros because otherwise we get stuck in a nightmare 380 * of header definitions for the use of task_stack_page. 381 */ 382 383 #define current_top_of_stack() \ 384 ({ \ 385 struct stack_info _info; \ 386 BUG_ON(!on_accessible_stack(current, current_stack_pointer, 1, &_info)); \ 387 _info.high; \ 388 }) 389 #define on_thread_stack() (on_task_stack(current, current_stack_pointer, 1, NULL)) 390 391 #endif /* __ASSEMBLY__ */ 392 #endif /* __ASM_PROCESSOR_H */ 393