1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/pgtable-hwdef.h> 13 #include <asm/pgtable-prot.h> 14 #include <asm/tlbflush.h> 15 16 /* 17 * VMALLOC range. 18 * 19 * VMALLOC_START: beginning of the kernel vmalloc space 20 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space 21 * and fixed mappings 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #define VMALLOC_END (- PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 25 26 #define FIRST_USER_ADDRESS 0UL 27 28 #ifndef __ASSEMBLY__ 29 30 #include <asm/cmpxchg.h> 31 #include <asm/fixmap.h> 32 #include <linux/mmdebug.h> 33 #include <linux/mm_types.h> 34 #include <linux/sched.h> 35 36 extern struct page *vmemmap; 37 38 extern void __pte_error(const char *file, int line, unsigned long val); 39 extern void __pmd_error(const char *file, int line, unsigned long val); 40 extern void __pud_error(const char *file, int line, unsigned long val); 41 extern void __pgd_error(const char *file, int line, unsigned long val); 42 43 /* 44 * ZERO_PAGE is a global shared page that is always zero: used 45 * for zero-mapped memory areas etc.. 46 */ 47 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 48 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 49 50 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 51 52 /* 53 * Macros to convert between a physical address and its placement in a 54 * page table entry, taking care of 52-bit addresses. 55 */ 56 #ifdef CONFIG_ARM64_PA_BITS_52 57 #define __pte_to_phys(pte) \ 58 ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 59 #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 60 #else 61 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 62 #define __phys_to_pte_val(phys) (phys) 63 #endif 64 65 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 66 #define pfn_pte(pfn,prot) \ 67 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 68 69 #define pte_none(pte) (!pte_val(pte)) 70 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 71 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 72 73 /* 74 * The following only work if pte_present(). Undefined behaviour otherwise. 75 */ 76 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 77 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 78 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 79 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 80 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 81 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 82 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 83 84 #define pte_cont_addr_end(addr, end) \ 85 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 86 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 87 }) 88 89 #define pmd_cont_addr_end(addr, end) \ 90 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 91 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 92 }) 93 94 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 95 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 96 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 97 98 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 99 /* 100 * Execute-only user mappings do not have the PTE_USER bit set. All valid 101 * kernel mappings have the PTE_UXN bit set. 102 */ 103 #define pte_valid_not_user(pte) \ 104 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 105 #define pte_valid_young(pte) \ 106 ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 107 #define pte_valid_user(pte) \ 108 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 109 110 /* 111 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 112 * so that we don't erroneously return false for pages that have been 113 * remapped as PROT_NONE but are yet to be flushed from the TLB. 114 */ 115 #define pte_accessible(mm, pte) \ 116 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 117 118 /* 119 * p??_access_permitted() is true for valid user mappings (subject to the 120 * write permission check) other than user execute-only which do not have the 121 * PTE_USER bit set. PROT_NONE mappings do not have the PTE_VALID bit set. 122 */ 123 #define pte_access_permitted(pte, write) \ 124 (pte_valid_user(pte) && (!(write) || pte_write(pte))) 125 #define pmd_access_permitted(pmd, write) \ 126 (pte_access_permitted(pmd_pte(pmd), (write))) 127 #define pud_access_permitted(pud, write) \ 128 (pte_access_permitted(pud_pte(pud), (write))) 129 130 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 131 { 132 pte_val(pte) &= ~pgprot_val(prot); 133 return pte; 134 } 135 136 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 137 { 138 pte_val(pte) |= pgprot_val(prot); 139 return pte; 140 } 141 142 static inline pte_t pte_wrprotect(pte_t pte) 143 { 144 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 145 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 146 return pte; 147 } 148 149 static inline pte_t pte_mkwrite(pte_t pte) 150 { 151 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 152 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 153 return pte; 154 } 155 156 static inline pte_t pte_mkclean(pte_t pte) 157 { 158 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 159 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 160 161 return pte; 162 } 163 164 static inline pte_t pte_mkdirty(pte_t pte) 165 { 166 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 167 168 if (pte_write(pte)) 169 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 170 171 return pte; 172 } 173 174 static inline pte_t pte_mkold(pte_t pte) 175 { 176 return clear_pte_bit(pte, __pgprot(PTE_AF)); 177 } 178 179 static inline pte_t pte_mkyoung(pte_t pte) 180 { 181 return set_pte_bit(pte, __pgprot(PTE_AF)); 182 } 183 184 static inline pte_t pte_mkspecial(pte_t pte) 185 { 186 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 187 } 188 189 static inline pte_t pte_mkcont(pte_t pte) 190 { 191 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 192 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 193 } 194 195 static inline pte_t pte_mknoncont(pte_t pte) 196 { 197 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 198 } 199 200 static inline pte_t pte_mkpresent(pte_t pte) 201 { 202 return set_pte_bit(pte, __pgprot(PTE_VALID)); 203 } 204 205 static inline pmd_t pmd_mkcont(pmd_t pmd) 206 { 207 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 208 } 209 210 static inline pte_t pte_mkdevmap(pte_t pte) 211 { 212 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 213 } 214 215 static inline void set_pte(pte_t *ptep, pte_t pte) 216 { 217 WRITE_ONCE(*ptep, pte); 218 219 /* 220 * Only if the new pte is valid and kernel, otherwise TLB maintenance 221 * or update_mmu_cache() have the necessary barriers. 222 */ 223 if (pte_valid_not_user(pte)) { 224 dsb(ishst); 225 isb(); 226 } 227 } 228 229 extern void __sync_icache_dcache(pte_t pteval); 230 231 /* 232 * PTE bits configuration in the presence of hardware Dirty Bit Management 233 * (PTE_WRITE == PTE_DBM): 234 * 235 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 236 * 0 0 | 1 0 0 237 * 0 1 | 1 1 0 238 * 1 0 | 1 0 1 239 * 1 1 | 0 1 x 240 * 241 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 242 * the page fault mechanism. Checking the dirty status of a pte becomes: 243 * 244 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 245 */ 246 247 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, 248 pte_t pte) 249 { 250 pte_t old_pte; 251 252 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 253 return; 254 255 old_pte = READ_ONCE(*ptep); 256 257 if (!pte_valid(old_pte) || !pte_valid(pte)) 258 return; 259 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 260 return; 261 262 /* 263 * Check for potential race with hardware updates of the pte 264 * (ptep_set_access_flags safely changes valid ptes without going 265 * through an invalid entry). 266 */ 267 VM_WARN_ONCE(!pte_young(pte), 268 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 269 __func__, pte_val(old_pte), pte_val(pte)); 270 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 271 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 272 __func__, pte_val(old_pte), pte_val(pte)); 273 } 274 275 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 276 pte_t *ptep, pte_t pte) 277 { 278 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 279 __sync_icache_dcache(pte); 280 281 __check_racy_pte_update(mm, ptep, pte); 282 283 set_pte(ptep, pte); 284 } 285 286 /* 287 * Huge pte definitions. 288 */ 289 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 290 291 /* 292 * Hugetlb definitions. 293 */ 294 #define HUGE_MAX_HSTATE 4 295 #define HPAGE_SHIFT PMD_SHIFT 296 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 297 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 298 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 299 300 static inline pte_t pgd_pte(pgd_t pgd) 301 { 302 return __pte(pgd_val(pgd)); 303 } 304 305 static inline pte_t pud_pte(pud_t pud) 306 { 307 return __pte(pud_val(pud)); 308 } 309 310 static inline pud_t pte_pud(pte_t pte) 311 { 312 return __pud(pte_val(pte)); 313 } 314 315 static inline pmd_t pud_pmd(pud_t pud) 316 { 317 return __pmd(pud_val(pud)); 318 } 319 320 static inline pte_t pmd_pte(pmd_t pmd) 321 { 322 return __pte(pmd_val(pmd)); 323 } 324 325 static inline pmd_t pte_pmd(pte_t pte) 326 { 327 return __pmd(pte_val(pte)); 328 } 329 330 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 331 { 332 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 333 } 334 335 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 336 { 337 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 338 } 339 340 #ifdef CONFIG_NUMA_BALANCING 341 /* 342 * See the comment in include/asm-generic/pgtable.h 343 */ 344 static inline int pte_protnone(pte_t pte) 345 { 346 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 347 } 348 349 static inline int pmd_protnone(pmd_t pmd) 350 { 351 return pte_protnone(pmd_pte(pmd)); 352 } 353 #endif 354 355 /* 356 * THP definitions. 357 */ 358 359 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 360 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 361 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 362 363 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 364 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 365 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 366 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 367 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 368 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 369 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 370 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 371 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 372 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 373 #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) 374 375 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 376 377 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 378 379 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 380 381 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 382 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 383 #endif 384 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 385 { 386 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 387 } 388 389 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 390 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 391 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 392 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 393 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 394 395 #define pud_young(pud) pte_young(pud_pte(pud)) 396 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 397 #define pud_write(pud) pte_write(pud_pte(pud)) 398 399 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 400 401 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 402 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 403 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 404 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 405 406 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 407 408 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 409 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 410 411 #define __pgprot_modify(prot,mask,bits) \ 412 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 413 414 /* 415 * Mark the prot value as uncacheable and unbufferable. 416 */ 417 #define pgprot_noncached(prot) \ 418 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 419 #define pgprot_writecombine(prot) \ 420 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 421 #define pgprot_device(prot) \ 422 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 423 /* 424 * DMA allocations for non-coherent devices use what the Arm architecture calls 425 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 426 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 427 * is intended for MMIO and thus forbids speculation, preserves access size, 428 * requires strict alignment and can also force write responses to come from the 429 * endpoint. 430 */ 431 #define pgprot_dmacoherent(prot) \ 432 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 433 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 434 435 #define __HAVE_PHYS_MEM_ACCESS_PROT 436 struct file; 437 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 438 unsigned long size, pgprot_t vma_prot); 439 440 #define pmd_none(pmd) (!pmd_val(pmd)) 441 442 #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 443 444 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 445 PMD_TYPE_TABLE) 446 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 447 PMD_TYPE_SECT) 448 449 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 450 static inline bool pud_sect(pud_t pud) { return false; } 451 static inline bool pud_table(pud_t pud) { return true; } 452 #else 453 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 454 PUD_TYPE_SECT) 455 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 456 PUD_TYPE_TABLE) 457 #endif 458 459 extern pgd_t init_pg_dir[PTRS_PER_PGD]; 460 extern pgd_t init_pg_end[]; 461 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 462 extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 463 extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 464 465 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 466 467 static inline bool in_swapper_pgdir(void *addr) 468 { 469 return ((unsigned long)addr & PAGE_MASK) == 470 ((unsigned long)swapper_pg_dir & PAGE_MASK); 471 } 472 473 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 474 { 475 #ifdef __PAGETABLE_PMD_FOLDED 476 if (in_swapper_pgdir(pmdp)) { 477 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 478 return; 479 } 480 #endif /* __PAGETABLE_PMD_FOLDED */ 481 482 WRITE_ONCE(*pmdp, pmd); 483 484 if (pmd_valid(pmd)) { 485 dsb(ishst); 486 isb(); 487 } 488 } 489 490 static inline void pmd_clear(pmd_t *pmdp) 491 { 492 set_pmd(pmdp, __pmd(0)); 493 } 494 495 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 496 { 497 return __pmd_to_phys(pmd); 498 } 499 500 static inline void pte_unmap(pte_t *pte) { } 501 502 /* Find an entry in the third-level page table. */ 503 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 504 505 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 506 #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) 507 508 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 509 510 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 511 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 512 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 513 514 #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(__pmd_to_phys(pmd))) 515 516 /* use ONLY for statically allocated translation tables */ 517 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 518 519 /* 520 * Conversion functions: convert a page and protection to a page entry, 521 * and a page entry and page directory to the page they refer to. 522 */ 523 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 524 525 #if CONFIG_PGTABLE_LEVELS > 2 526 527 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 528 529 #define pud_none(pud) (!pud_val(pud)) 530 #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 531 #define pud_present(pud) pte_present(pud_pte(pud)) 532 #define pud_valid(pud) pte_valid(pud_pte(pud)) 533 534 static inline void set_pud(pud_t *pudp, pud_t pud) 535 { 536 #ifdef __PAGETABLE_PUD_FOLDED 537 if (in_swapper_pgdir(pudp)) { 538 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 539 return; 540 } 541 #endif /* __PAGETABLE_PUD_FOLDED */ 542 543 WRITE_ONCE(*pudp, pud); 544 545 if (pud_valid(pud)) { 546 dsb(ishst); 547 isb(); 548 } 549 } 550 551 static inline void pud_clear(pud_t *pudp) 552 { 553 set_pud(pudp, __pud(0)); 554 } 555 556 static inline phys_addr_t pud_page_paddr(pud_t pud) 557 { 558 return __pud_to_phys(pud); 559 } 560 561 /* Find an entry in the second-level page table. */ 562 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 563 564 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 565 #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) 566 567 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 568 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 569 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 570 571 #define pud_page(pud) pfn_to_page(__phys_to_pfn(__pud_to_phys(pud))) 572 573 /* use ONLY for statically allocated translation tables */ 574 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 575 576 #else 577 578 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 579 580 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 581 #define pmd_set_fixmap(addr) NULL 582 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 583 #define pmd_clear_fixmap() 584 585 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 586 587 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 588 589 #if CONFIG_PGTABLE_LEVELS > 3 590 591 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 592 593 #define pgd_none(pgd) (!pgd_val(pgd)) 594 #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 595 #define pgd_present(pgd) (pgd_val(pgd)) 596 597 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 598 { 599 if (in_swapper_pgdir(pgdp)) { 600 set_swapper_pgd(pgdp, pgd); 601 return; 602 } 603 604 WRITE_ONCE(*pgdp, pgd); 605 dsb(ishst); 606 isb(); 607 } 608 609 static inline void pgd_clear(pgd_t *pgdp) 610 { 611 set_pgd(pgdp, __pgd(0)); 612 } 613 614 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 615 { 616 return __pgd_to_phys(pgd); 617 } 618 619 /* Find an entry in the frst-level page table. */ 620 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 621 622 #define pud_offset_phys(dir, addr) (pgd_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 623 #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) 624 625 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 626 #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) 627 #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 628 629 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 630 631 /* use ONLY for statically allocated translation tables */ 632 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 633 634 #else 635 636 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 637 638 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 639 #define pud_set_fixmap(addr) NULL 640 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 641 #define pud_clear_fixmap() 642 643 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 644 645 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 646 647 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 648 649 /* to find an entry in a page-table-directory */ 650 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 651 652 #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) 653 654 #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) 655 656 /* to find an entry in a kernel page-table-directory */ 657 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 658 659 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 660 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 661 662 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 663 { 664 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 665 PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 666 /* preserve the hardware dirty information */ 667 if (pte_hw_dirty(pte)) 668 pte = pte_mkdirty(pte); 669 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 670 return pte; 671 } 672 673 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 674 { 675 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 676 } 677 678 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 679 extern int ptep_set_access_flags(struct vm_area_struct *vma, 680 unsigned long address, pte_t *ptep, 681 pte_t entry, int dirty); 682 683 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 684 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 685 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 686 unsigned long address, pmd_t *pmdp, 687 pmd_t entry, int dirty) 688 { 689 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 690 } 691 692 static inline int pud_devmap(pud_t pud) 693 { 694 return 0; 695 } 696 697 static inline int pgd_devmap(pgd_t pgd) 698 { 699 return 0; 700 } 701 #endif 702 703 /* 704 * Atomic pte/pmd modifications. 705 */ 706 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 707 static inline int __ptep_test_and_clear_young(pte_t *ptep) 708 { 709 pte_t old_pte, pte; 710 711 pte = READ_ONCE(*ptep); 712 do { 713 old_pte = pte; 714 pte = pte_mkold(pte); 715 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 716 pte_val(old_pte), pte_val(pte)); 717 } while (pte_val(pte) != pte_val(old_pte)); 718 719 return pte_young(pte); 720 } 721 722 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 723 unsigned long address, 724 pte_t *ptep) 725 { 726 return __ptep_test_and_clear_young(ptep); 727 } 728 729 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 730 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 731 unsigned long address, pte_t *ptep) 732 { 733 int young = ptep_test_and_clear_young(vma, address, ptep); 734 735 if (young) { 736 /* 737 * We can elide the trailing DSB here since the worst that can 738 * happen is that a CPU continues to use the young entry in its 739 * TLB and we mistakenly reclaim the associated page. The 740 * window for such an event is bounded by the next 741 * context-switch, which provides a DSB to complete the TLB 742 * invalidation. 743 */ 744 flush_tlb_page_nosync(vma, address); 745 } 746 747 return young; 748 } 749 750 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 751 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 752 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 753 unsigned long address, 754 pmd_t *pmdp) 755 { 756 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 757 } 758 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 759 760 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 761 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 762 unsigned long address, pte_t *ptep) 763 { 764 return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 765 } 766 767 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 768 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 769 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 770 unsigned long address, pmd_t *pmdp) 771 { 772 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 773 } 774 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 775 776 /* 777 * ptep_set_wrprotect - mark read-only while trasferring potential hardware 778 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 779 */ 780 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 781 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 782 { 783 pte_t old_pte, pte; 784 785 pte = READ_ONCE(*ptep); 786 do { 787 old_pte = pte; 788 /* 789 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 790 * clear), set the PTE_DIRTY bit. 791 */ 792 if (pte_hw_dirty(pte)) 793 pte = pte_mkdirty(pte); 794 pte = pte_wrprotect(pte); 795 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 796 pte_val(old_pte), pte_val(pte)); 797 } while (pte_val(pte) != pte_val(old_pte)); 798 } 799 800 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 801 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 802 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 803 unsigned long address, pmd_t *pmdp) 804 { 805 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 806 } 807 808 #define pmdp_establish pmdp_establish 809 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 810 unsigned long address, pmd_t *pmdp, pmd_t pmd) 811 { 812 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 813 } 814 #endif 815 816 /* 817 * Encode and decode a swap entry: 818 * bits 0-1: present (must be zero) 819 * bits 2-7: swap type 820 * bits 8-57: swap offset 821 * bit 58: PTE_PROT_NONE (must be zero) 822 */ 823 #define __SWP_TYPE_SHIFT 2 824 #define __SWP_TYPE_BITS 6 825 #define __SWP_OFFSET_BITS 50 826 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 827 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 828 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 829 830 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 831 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 832 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 833 834 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 835 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 836 837 /* 838 * Ensure that there are not more swap files than can be encoded in the kernel 839 * PTEs. 840 */ 841 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 842 843 extern int kern_addr_valid(unsigned long addr); 844 845 #include <asm-generic/pgtable.h> 846 847 /* 848 * On AArch64, the cache coherency is handled via the set_pte_at() function. 849 */ 850 static inline void update_mmu_cache(struct vm_area_struct *vma, 851 unsigned long addr, pte_t *ptep) 852 { 853 /* 854 * We don't do anything here, so there's a very small chance of 855 * us retaking a user fault which we just fixed up. The alternative 856 * is doing a dsb(ishst), but that penalises the fastpath. 857 */ 858 } 859 860 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 861 862 #ifdef CONFIG_ARM64_PA_BITS_52 863 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 864 #else 865 #define phys_to_ttbr(addr) (addr) 866 #endif 867 868 #endif /* !__ASSEMBLY__ */ 869 870 #endif /* __ASM_PGTABLE_H */ 871