1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __ASM_PGTABLE_H 17 #define __ASM_PGTABLE_H 18 19 #include <asm/bug.h> 20 #include <asm/proc-fns.h> 21 22 #include <asm/memory.h> 23 #include <asm/pgtable-hwdef.h> 24 25 /* 26 * Software defined PTE bits definition. 27 */ 28 #define PTE_VALID (_AT(pteval_t, 1) << 0) 29 #define PTE_DIRTY (_AT(pteval_t, 1) << 55) 30 #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) 31 #ifdef CONFIG_ARM64_HW_AFDBM 32 #define PTE_WRITE (PTE_DBM) /* same as DBM */ 33 #else 34 #define PTE_WRITE (_AT(pteval_t, 1) << 57) 35 #endif 36 #define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */ 37 38 /* 39 * VMALLOC and SPARSEMEM_VMEMMAP ranges. 40 * 41 * VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array 42 * (rounded up to PUD_SIZE). 43 * VMALLOC_START: beginning of the kernel VA space 44 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space, 45 * fixed mappings and modules 46 */ 47 #define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE) 48 #define VMALLOC_START (UL(0xffffffffffffffff) << VA_BITS) 49 #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 50 51 #define vmemmap ((struct page *)(VMALLOC_END + SZ_64K)) 52 53 #define FIRST_USER_ADDRESS 0UL 54 55 #ifndef __ASSEMBLY__ 56 57 #include <linux/mmdebug.h> 58 59 extern void __pte_error(const char *file, int line, unsigned long val); 60 extern void __pmd_error(const char *file, int line, unsigned long val); 61 extern void __pud_error(const char *file, int line, unsigned long val); 62 extern void __pgd_error(const char *file, int line, unsigned long val); 63 64 #define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) 65 #define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) 66 67 #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE)) 68 #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC)) 69 #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL)) 70 71 #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) 72 #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) 73 #define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) 74 75 #define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) 76 77 #define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE) 78 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE) 79 80 #define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP) 81 #define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP) 82 83 #define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY) 84 #define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN) 85 86 #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_PXN | PTE_UXN) 87 #define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE) 88 #define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE) 89 #define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) 90 #define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) 91 #define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) 92 #define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) 93 94 #define __P000 PAGE_NONE 95 #define __P001 PAGE_READONLY 96 #define __P010 PAGE_COPY 97 #define __P011 PAGE_COPY 98 #define __P100 PAGE_READONLY_EXEC 99 #define __P101 PAGE_READONLY_EXEC 100 #define __P110 PAGE_COPY_EXEC 101 #define __P111 PAGE_COPY_EXEC 102 103 #define __S000 PAGE_NONE 104 #define __S001 PAGE_READONLY 105 #define __S010 PAGE_SHARED 106 #define __S011 PAGE_SHARED 107 #define __S100 PAGE_READONLY_EXEC 108 #define __S101 PAGE_READONLY_EXEC 109 #define __S110 PAGE_SHARED_EXEC 110 #define __S111 PAGE_SHARED_EXEC 111 112 /* 113 * ZERO_PAGE is a global shared page that is always zero: used 114 * for zero-mapped memory areas etc.. 115 */ 116 extern struct page *empty_zero_page; 117 #define ZERO_PAGE(vaddr) (empty_zero_page) 118 119 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 120 121 #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) 122 123 #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 124 125 #define pte_none(pte) (!pte_val(pte)) 126 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 127 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 128 129 /* Find an entry in the third-level page table. */ 130 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 131 132 #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr)) 133 134 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 135 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) 136 #define pte_unmap(pte) do { } while (0) 137 #define pte_unmap_nested(pte) do { } while (0) 138 139 /* 140 * The following only work if pte_present(). Undefined behaviour otherwise. 141 */ 142 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 143 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 144 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 145 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 146 #define pte_exec(pte) (!(pte_val(pte) & PTE_UXN)) 147 148 #ifdef CONFIG_ARM64_HW_AFDBM 149 #define pte_hw_dirty(pte) (!(pte_val(pte) & PTE_RDONLY)) 150 #else 151 #define pte_hw_dirty(pte) (0) 152 #endif 153 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 154 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 155 156 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 157 #define pte_valid_user(pte) \ 158 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 159 #define pte_valid_not_user(pte) \ 160 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) 161 162 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 163 { 164 pte_val(pte) &= ~pgprot_val(prot); 165 return pte; 166 } 167 168 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 169 { 170 pte_val(pte) |= pgprot_val(prot); 171 return pte; 172 } 173 174 static inline pte_t pte_wrprotect(pte_t pte) 175 { 176 return clear_pte_bit(pte, __pgprot(PTE_WRITE)); 177 } 178 179 static inline pte_t pte_mkwrite(pte_t pte) 180 { 181 return set_pte_bit(pte, __pgprot(PTE_WRITE)); 182 } 183 184 static inline pte_t pte_mkclean(pte_t pte) 185 { 186 return clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 187 } 188 189 static inline pte_t pte_mkdirty(pte_t pte) 190 { 191 return set_pte_bit(pte, __pgprot(PTE_DIRTY)); 192 } 193 194 static inline pte_t pte_mkold(pte_t pte) 195 { 196 return clear_pte_bit(pte, __pgprot(PTE_AF)); 197 } 198 199 static inline pte_t pte_mkyoung(pte_t pte) 200 { 201 return set_pte_bit(pte, __pgprot(PTE_AF)); 202 } 203 204 static inline pte_t pte_mkspecial(pte_t pte) 205 { 206 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 207 } 208 209 static inline void set_pte(pte_t *ptep, pte_t pte) 210 { 211 *ptep = pte; 212 213 /* 214 * Only if the new pte is valid and kernel, otherwise TLB maintenance 215 * or update_mmu_cache() have the necessary barriers. 216 */ 217 if (pte_valid_not_user(pte)) { 218 dsb(ishst); 219 isb(); 220 } 221 } 222 223 struct mm_struct; 224 struct vm_area_struct; 225 226 extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); 227 228 /* 229 * PTE bits configuration in the presence of hardware Dirty Bit Management 230 * (PTE_WRITE == PTE_DBM): 231 * 232 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 233 * 0 0 | 1 0 0 234 * 0 1 | 1 1 0 235 * 1 0 | 1 0 1 236 * 1 1 | 0 1 x 237 * 238 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 239 * the page fault mechanism. Checking the dirty status of a pte becomes: 240 * 241 * PTE_DIRTY || !PTE_RDONLY 242 */ 243 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 244 pte_t *ptep, pte_t pte) 245 { 246 if (pte_valid_user(pte)) { 247 if (!pte_special(pte) && pte_exec(pte)) 248 __sync_icache_dcache(pte, addr); 249 if (pte_sw_dirty(pte) && pte_write(pte)) 250 pte_val(pte) &= ~PTE_RDONLY; 251 else 252 pte_val(pte) |= PTE_RDONLY; 253 } 254 255 /* 256 * If the existing pte is valid, check for potential race with 257 * hardware updates of the pte (ptep_set_access_flags safely changes 258 * valid ptes without going through an invalid entry). 259 */ 260 if (IS_ENABLED(CONFIG_DEBUG_VM) && IS_ENABLED(CONFIG_ARM64_HW_AFDBM) && 261 pte_valid(*ptep)) { 262 BUG_ON(!pte_young(pte)); 263 BUG_ON(pte_write(*ptep) && !pte_dirty(pte)); 264 } 265 266 set_pte(ptep, pte); 267 } 268 269 /* 270 * Huge pte definitions. 271 */ 272 #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) 273 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 274 275 /* 276 * Hugetlb definitions. 277 */ 278 #define HUGE_MAX_HSTATE 2 279 #define HPAGE_SHIFT PMD_SHIFT 280 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 281 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 282 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 283 284 #define __HAVE_ARCH_PTE_SPECIAL 285 286 static inline pte_t pud_pte(pud_t pud) 287 { 288 return __pte(pud_val(pud)); 289 } 290 291 static inline pmd_t pud_pmd(pud_t pud) 292 { 293 return __pmd(pud_val(pud)); 294 } 295 296 static inline pte_t pmd_pte(pmd_t pmd) 297 { 298 return __pte(pmd_val(pmd)); 299 } 300 301 static inline pmd_t pte_pmd(pte_t pte) 302 { 303 return __pmd(pte_val(pte)); 304 } 305 306 static inline pgprot_t mk_sect_prot(pgprot_t prot) 307 { 308 return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); 309 } 310 311 /* 312 * THP definitions. 313 */ 314 315 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 316 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 317 #define pmd_trans_splitting(pmd) pte_special(pmd_pte(pmd)) 318 #ifdef CONFIG_HAVE_RCU_TABLE_FREE 319 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH 320 struct vm_area_struct; 321 void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address, 322 pmd_t *pmdp); 323 #endif /* CONFIG_HAVE_RCU_TABLE_FREE */ 324 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 325 326 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 327 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 328 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 329 #define pmd_mksplitting(pmd) pte_pmd(pte_mkspecial(pmd_pte(pmd))) 330 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 331 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 332 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 333 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 334 #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK)) 335 336 #define __HAVE_ARCH_PMD_WRITE 337 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 338 339 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 340 341 #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 342 #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 343 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 344 345 #define pud_write(pud) pte_write(pud_pte(pud)) 346 #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 347 348 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 349 350 static inline int has_transparent_hugepage(void) 351 { 352 return 1; 353 } 354 355 #define __pgprot_modify(prot,mask,bits) \ 356 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 357 358 /* 359 * Mark the prot value as uncacheable and unbufferable. 360 */ 361 #define pgprot_noncached(prot) \ 362 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 363 #define pgprot_writecombine(prot) \ 364 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 365 #define pgprot_device(prot) \ 366 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 367 #define __HAVE_PHYS_MEM_ACCESS_PROT 368 struct file; 369 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 370 unsigned long size, pgprot_t vma_prot); 371 372 #define pmd_none(pmd) (!pmd_val(pmd)) 373 #define pmd_present(pmd) (pmd_val(pmd)) 374 375 #define pmd_bad(pmd) (!(pmd_val(pmd) & 2)) 376 377 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 378 PMD_TYPE_TABLE) 379 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 380 PMD_TYPE_SECT) 381 382 #ifdef CONFIG_ARM64_64K_PAGES 383 #define pud_sect(pud) (0) 384 #define pud_table(pud) (1) 385 #else 386 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 387 PUD_TYPE_SECT) 388 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 389 PUD_TYPE_TABLE) 390 #endif 391 392 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 393 { 394 *pmdp = pmd; 395 dsb(ishst); 396 isb(); 397 } 398 399 static inline void pmd_clear(pmd_t *pmdp) 400 { 401 set_pmd(pmdp, __pmd(0)); 402 } 403 404 static inline pte_t *pmd_page_vaddr(pmd_t pmd) 405 { 406 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK); 407 } 408 409 #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) 410 411 /* 412 * Conversion functions: convert a page and protection to a page entry, 413 * and a page entry and page directory to the page they refer to. 414 */ 415 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 416 417 #if CONFIG_PGTABLE_LEVELS > 2 418 419 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 420 421 #define pud_none(pud) (!pud_val(pud)) 422 #define pud_bad(pud) (!(pud_val(pud) & 2)) 423 #define pud_present(pud) (pud_val(pud)) 424 425 static inline void set_pud(pud_t *pudp, pud_t pud) 426 { 427 *pudp = pud; 428 dsb(ishst); 429 isb(); 430 } 431 432 static inline void pud_clear(pud_t *pudp) 433 { 434 set_pud(pudp, __pud(0)); 435 } 436 437 static inline pmd_t *pud_page_vaddr(pud_t pud) 438 { 439 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK); 440 } 441 442 /* Find an entry in the second-level page table. */ 443 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 444 445 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) 446 { 447 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr); 448 } 449 450 #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK)) 451 452 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 453 454 #if CONFIG_PGTABLE_LEVELS > 3 455 456 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 457 458 #define pgd_none(pgd) (!pgd_val(pgd)) 459 #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 460 #define pgd_present(pgd) (pgd_val(pgd)) 461 462 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 463 { 464 *pgdp = pgd; 465 dsb(ishst); 466 } 467 468 static inline void pgd_clear(pgd_t *pgdp) 469 { 470 set_pgd(pgdp, __pgd(0)); 471 } 472 473 static inline pud_t *pgd_page_vaddr(pgd_t pgd) 474 { 475 return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK); 476 } 477 478 /* Find an entry in the frst-level page table. */ 479 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 480 481 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr) 482 { 483 return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr); 484 } 485 486 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK)) 487 488 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 489 490 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 491 492 /* to find an entry in a page-table-directory */ 493 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 494 495 #define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr)) 496 497 /* to find an entry in a kernel page-table-directory */ 498 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 499 500 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 501 { 502 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 503 PTE_PROT_NONE | PTE_WRITE | PTE_TYPE_MASK; 504 /* preserve the hardware dirty information */ 505 if (pte_hw_dirty(pte)) 506 newprot |= PTE_DIRTY; 507 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 508 return pte; 509 } 510 511 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 512 { 513 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 514 } 515 516 #ifdef CONFIG_ARM64_HW_AFDBM 517 /* 518 * Atomic pte/pmd modifications. 519 */ 520 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 521 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 522 unsigned long address, 523 pte_t *ptep) 524 { 525 pteval_t pteval; 526 unsigned int tmp, res; 527 528 asm volatile("// ptep_test_and_clear_young\n" 529 " prfm pstl1strm, %2\n" 530 "1: ldxr %0, %2\n" 531 " ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n" 532 " and %0, %0, %4 // clear PTE_AF\n" 533 " stxr %w1, %0, %2\n" 534 " cbnz %w1, 1b\n" 535 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res) 536 : "L" (~PTE_AF), "I" (ilog2(PTE_AF))); 537 538 return res; 539 } 540 541 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 542 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 543 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 544 unsigned long address, 545 pmd_t *pmdp) 546 { 547 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 548 } 549 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 550 551 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 552 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 553 unsigned long address, pte_t *ptep) 554 { 555 pteval_t old_pteval; 556 unsigned int tmp; 557 558 asm volatile("// ptep_get_and_clear\n" 559 " prfm pstl1strm, %2\n" 560 "1: ldxr %0, %2\n" 561 " stxr %w1, xzr, %2\n" 562 " cbnz %w1, 1b\n" 563 : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))); 564 565 return __pte(old_pteval); 566 } 567 568 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 569 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 570 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 571 unsigned long address, pmd_t *pmdp) 572 { 573 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 574 } 575 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 576 577 /* 578 * ptep_set_wrprotect - mark read-only while trasferring potential hardware 579 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 580 */ 581 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 582 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 583 { 584 pteval_t pteval; 585 unsigned long tmp; 586 587 asm volatile("// ptep_set_wrprotect\n" 588 " prfm pstl1strm, %2\n" 589 "1: ldxr %0, %2\n" 590 " tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n" 591 " csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n" 592 " orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n" 593 " and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n" 594 " stxr %w1, %0, %2\n" 595 " cbnz %w1, 1b\n" 596 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)) 597 : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE) 598 : "cc"); 599 } 600 601 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 602 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 603 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 604 unsigned long address, pmd_t *pmdp) 605 { 606 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 607 } 608 #endif 609 #endif /* CONFIG_ARM64_HW_AFDBM */ 610 611 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 612 extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 613 614 /* 615 * Encode and decode a swap entry: 616 * bits 0-1: present (must be zero) 617 * bits 2-7: swap type 618 * bits 8-57: swap offset 619 */ 620 #define __SWP_TYPE_SHIFT 2 621 #define __SWP_TYPE_BITS 6 622 #define __SWP_OFFSET_BITS 50 623 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 624 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 625 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 626 627 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 628 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 629 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 630 631 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 632 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 633 634 /* 635 * Ensure that there are not more swap files than can be encoded in the kernel 636 * PTEs. 637 */ 638 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 639 640 extern int kern_addr_valid(unsigned long addr); 641 642 #include <asm-generic/pgtable.h> 643 644 #define pgtable_cache_init() do { } while (0) 645 646 /* 647 * On AArch64, the cache coherency is handled via the set_pte_at() function. 648 */ 649 static inline void update_mmu_cache(struct vm_area_struct *vma, 650 unsigned long addr, pte_t *ptep) 651 { 652 /* 653 * set_pte() does not have a DSB for user mappings, so make sure that 654 * the page table write is visible. 655 */ 656 dsb(ishst); 657 } 658 659 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 660 661 #endif /* !__ASSEMBLY__ */ 662 663 #endif /* __ASM_PGTABLE_H */ 664