1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space 22 * and fixed mappings 23 */ 24 #define VMALLOC_START (MODULES_END) 25 #define VMALLOC_END (VMEMMAP_START - SZ_256M) 26 27 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 28 29 #ifndef __ASSEMBLY__ 30 31 #include <asm/cmpxchg.h> 32 #include <asm/fixmap.h> 33 #include <linux/mmdebug.h> 34 #include <linux/mm_types.h> 35 #include <linux/sched.h> 36 37 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 38 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 39 40 /* Set stride and tlb_level in flush_*_tlb_range */ 41 #define flush_pmd_tlb_range(vma, addr, end) \ 42 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 43 #define flush_pud_tlb_range(vma, addr, end) \ 44 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 45 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 46 47 /* 48 * Outside of a few very special situations (e.g. hibernation), we always 49 * use broadcast TLB invalidation instructions, therefore a spurious page 50 * fault on one CPU which has been handled concurrently by another CPU 51 * does not need to perform additional invalidation. 52 */ 53 #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0) 54 55 /* 56 * ZERO_PAGE is a global shared page that is always zero: used 57 * for zero-mapped memory areas etc.. 58 */ 59 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 60 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 61 62 #define pte_ERROR(e) \ 63 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 64 65 /* 66 * Macros to convert between a physical address and its placement in a 67 * page table entry, taking care of 52-bit addresses. 68 */ 69 #ifdef CONFIG_ARM64_PA_BITS_52 70 #define __pte_to_phys(pte) \ 71 ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 72 #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 73 #else 74 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 75 #define __phys_to_pte_val(phys) (phys) 76 #endif 77 78 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 79 #define pfn_pte(pfn,prot) \ 80 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 81 82 #define pte_none(pte) (!pte_val(pte)) 83 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 84 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 85 86 /* 87 * The following only work if pte_present(). Undefined behaviour otherwise. 88 */ 89 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 90 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 91 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 92 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 93 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 94 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 95 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 96 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 97 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 98 99 #define pte_cont_addr_end(addr, end) \ 100 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 101 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 102 }) 103 104 #define pmd_cont_addr_end(addr, end) \ 105 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 106 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 107 }) 108 109 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 110 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 111 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 112 113 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 114 /* 115 * Execute-only user mappings do not have the PTE_USER bit set. All valid 116 * kernel mappings have the PTE_UXN bit set. 117 */ 118 #define pte_valid_not_user(pte) \ 119 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 120 /* 121 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 122 * so that we don't erroneously return false for pages that have been 123 * remapped as PROT_NONE but are yet to be flushed from the TLB. 124 * Note that we can't make any assumptions based on the state of the access 125 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the 126 * TLB. 127 */ 128 #define pte_accessible(mm, pte) \ 129 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 130 131 /* 132 * p??_access_permitted() is true for valid user mappings (PTE_USER 133 * bit set, subject to the write permission check). For execute-only 134 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 135 * not set) must return false. PROT_NONE mappings do not have the 136 * PTE_VALID bit set. 137 */ 138 #define pte_access_permitted(pte, write) \ 139 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 140 #define pmd_access_permitted(pmd, write) \ 141 (pte_access_permitted(pmd_pte(pmd), (write))) 142 #define pud_access_permitted(pud, write) \ 143 (pte_access_permitted(pud_pte(pud), (write))) 144 145 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 146 { 147 pte_val(pte) &= ~pgprot_val(prot); 148 return pte; 149 } 150 151 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 152 { 153 pte_val(pte) |= pgprot_val(prot); 154 return pte; 155 } 156 157 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 158 { 159 pmd_val(pmd) &= ~pgprot_val(prot); 160 return pmd; 161 } 162 163 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 164 { 165 pmd_val(pmd) |= pgprot_val(prot); 166 return pmd; 167 } 168 169 static inline pte_t pte_mkwrite(pte_t pte) 170 { 171 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 172 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 173 return pte; 174 } 175 176 static inline pte_t pte_mkclean(pte_t pte) 177 { 178 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 179 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 180 181 return pte; 182 } 183 184 static inline pte_t pte_mkdirty(pte_t pte) 185 { 186 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 187 188 if (pte_write(pte)) 189 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 190 191 return pte; 192 } 193 194 static inline pte_t pte_wrprotect(pte_t pte) 195 { 196 /* 197 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 198 * clear), set the PTE_DIRTY bit. 199 */ 200 if (pte_hw_dirty(pte)) 201 pte = pte_mkdirty(pte); 202 203 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 204 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 205 return pte; 206 } 207 208 static inline pte_t pte_mkold(pte_t pte) 209 { 210 return clear_pte_bit(pte, __pgprot(PTE_AF)); 211 } 212 213 static inline pte_t pte_mkyoung(pte_t pte) 214 { 215 return set_pte_bit(pte, __pgprot(PTE_AF)); 216 } 217 218 static inline pte_t pte_mkspecial(pte_t pte) 219 { 220 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 221 } 222 223 static inline pte_t pte_mkcont(pte_t pte) 224 { 225 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 226 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 227 } 228 229 static inline pte_t pte_mknoncont(pte_t pte) 230 { 231 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 232 } 233 234 static inline pte_t pte_mkpresent(pte_t pte) 235 { 236 return set_pte_bit(pte, __pgprot(PTE_VALID)); 237 } 238 239 static inline pmd_t pmd_mkcont(pmd_t pmd) 240 { 241 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 242 } 243 244 static inline pte_t pte_mkdevmap(pte_t pte) 245 { 246 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 247 } 248 249 static inline void set_pte(pte_t *ptep, pte_t pte) 250 { 251 WRITE_ONCE(*ptep, pte); 252 253 /* 254 * Only if the new pte is valid and kernel, otherwise TLB maintenance 255 * or update_mmu_cache() have the necessary barriers. 256 */ 257 if (pte_valid_not_user(pte)) { 258 dsb(ishst); 259 isb(); 260 } 261 } 262 263 extern void __sync_icache_dcache(pte_t pteval); 264 265 /* 266 * PTE bits configuration in the presence of hardware Dirty Bit Management 267 * (PTE_WRITE == PTE_DBM): 268 * 269 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 270 * 0 0 | 1 0 0 271 * 0 1 | 1 1 0 272 * 1 0 | 1 0 1 273 * 1 1 | 0 1 x 274 * 275 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 276 * the page fault mechanism. Checking the dirty status of a pte becomes: 277 * 278 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 279 */ 280 281 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, 282 pte_t pte) 283 { 284 pte_t old_pte; 285 286 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 287 return; 288 289 old_pte = READ_ONCE(*ptep); 290 291 if (!pte_valid(old_pte) || !pte_valid(pte)) 292 return; 293 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 294 return; 295 296 /* 297 * Check for potential race with hardware updates of the pte 298 * (ptep_set_access_flags safely changes valid ptes without going 299 * through an invalid entry). 300 */ 301 VM_WARN_ONCE(!pte_young(pte), 302 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 303 __func__, pte_val(old_pte), pte_val(pte)); 304 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 305 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 306 __func__, pte_val(old_pte), pte_val(pte)); 307 } 308 309 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 310 pte_t *ptep, pte_t pte) 311 { 312 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 313 __sync_icache_dcache(pte); 314 315 if (system_supports_mte() && 316 pte_present(pte) && pte_tagged(pte) && !pte_special(pte)) 317 mte_sync_tags(ptep, pte); 318 319 __check_racy_pte_update(mm, ptep, pte); 320 321 set_pte(ptep, pte); 322 } 323 324 /* 325 * Huge pte definitions. 326 */ 327 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 328 329 /* 330 * Hugetlb definitions. 331 */ 332 #define HUGE_MAX_HSTATE 4 333 #define HPAGE_SHIFT PMD_SHIFT 334 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 335 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 336 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 337 338 static inline pte_t pgd_pte(pgd_t pgd) 339 { 340 return __pte(pgd_val(pgd)); 341 } 342 343 static inline pte_t p4d_pte(p4d_t p4d) 344 { 345 return __pte(p4d_val(p4d)); 346 } 347 348 static inline pte_t pud_pte(pud_t pud) 349 { 350 return __pte(pud_val(pud)); 351 } 352 353 static inline pud_t pte_pud(pte_t pte) 354 { 355 return __pud(pte_val(pte)); 356 } 357 358 static inline pmd_t pud_pmd(pud_t pud) 359 { 360 return __pmd(pud_val(pud)); 361 } 362 363 static inline pte_t pmd_pte(pmd_t pmd) 364 { 365 return __pte(pmd_val(pmd)); 366 } 367 368 static inline pmd_t pte_pmd(pte_t pte) 369 { 370 return __pmd(pte_val(pte)); 371 } 372 373 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 374 { 375 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 376 } 377 378 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 379 { 380 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 381 } 382 383 #ifdef CONFIG_NUMA_BALANCING 384 /* 385 * See the comment in include/linux/pgtable.h 386 */ 387 static inline int pte_protnone(pte_t pte) 388 { 389 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 390 } 391 392 static inline int pmd_protnone(pmd_t pmd) 393 { 394 return pte_protnone(pmd_pte(pmd)); 395 } 396 #endif 397 398 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) 399 400 static inline int pmd_present(pmd_t pmd) 401 { 402 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); 403 } 404 405 /* 406 * THP definitions. 407 */ 408 409 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 410 static inline int pmd_trans_huge(pmd_t pmd) 411 { 412 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 413 } 414 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 415 416 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 417 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 418 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 419 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 420 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 421 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 422 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 423 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 424 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 425 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 426 427 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 428 { 429 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); 430 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); 431 432 return pmd; 433 } 434 435 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 436 437 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 438 439 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 440 441 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 442 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 443 #endif 444 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 445 { 446 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 447 } 448 449 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 450 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 451 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 452 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 453 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 454 455 #define pud_young(pud) pte_young(pud_pte(pud)) 456 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 457 #define pud_write(pud) pte_write(pud_pte(pud)) 458 459 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 460 461 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 462 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 463 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 464 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 465 466 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 467 #define set_pud_at(mm, addr, pudp, pud) set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)) 468 469 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 470 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 471 472 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 473 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 474 475 #define __pgprot_modify(prot,mask,bits) \ 476 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 477 478 #define pgprot_nx(prot) \ 479 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 480 481 /* 482 * Mark the prot value as uncacheable and unbufferable. 483 */ 484 #define pgprot_noncached(prot) \ 485 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 486 #define pgprot_writecombine(prot) \ 487 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 488 #define pgprot_device(prot) \ 489 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 490 #define pgprot_tagged(prot) \ 491 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 492 #define pgprot_mhp pgprot_tagged 493 /* 494 * DMA allocations for non-coherent devices use what the Arm architecture calls 495 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 496 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 497 * is intended for MMIO and thus forbids speculation, preserves access size, 498 * requires strict alignment and can also force write responses to come from the 499 * endpoint. 500 */ 501 #define pgprot_dmacoherent(prot) \ 502 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 503 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 504 505 #define __HAVE_PHYS_MEM_ACCESS_PROT 506 struct file; 507 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 508 unsigned long size, pgprot_t vma_prot); 509 510 #define pmd_none(pmd) (!pmd_val(pmd)) 511 512 #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 513 514 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 515 PMD_TYPE_TABLE) 516 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 517 PMD_TYPE_SECT) 518 #define pmd_leaf(pmd) pmd_sect(pmd) 519 520 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 521 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 522 523 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 524 static inline bool pud_sect(pud_t pud) { return false; } 525 static inline bool pud_table(pud_t pud) { return true; } 526 #else 527 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 528 PUD_TYPE_SECT) 529 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 530 PUD_TYPE_TABLE) 531 #endif 532 533 extern pgd_t init_pg_dir[PTRS_PER_PGD]; 534 extern pgd_t init_pg_end[]; 535 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 536 extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 537 extern pgd_t idmap_pg_end[]; 538 extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 539 extern pgd_t reserved_pg_dir[PTRS_PER_PGD]; 540 541 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 542 543 static inline bool in_swapper_pgdir(void *addr) 544 { 545 return ((unsigned long)addr & PAGE_MASK) == 546 ((unsigned long)swapper_pg_dir & PAGE_MASK); 547 } 548 549 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 550 { 551 #ifdef __PAGETABLE_PMD_FOLDED 552 if (in_swapper_pgdir(pmdp)) { 553 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 554 return; 555 } 556 #endif /* __PAGETABLE_PMD_FOLDED */ 557 558 WRITE_ONCE(*pmdp, pmd); 559 560 if (pmd_valid(pmd)) { 561 dsb(ishst); 562 isb(); 563 } 564 } 565 566 static inline void pmd_clear(pmd_t *pmdp) 567 { 568 set_pmd(pmdp, __pmd(0)); 569 } 570 571 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 572 { 573 return __pmd_to_phys(pmd); 574 } 575 576 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 577 { 578 return (unsigned long)__va(pmd_page_paddr(pmd)); 579 } 580 581 /* Find an entry in the third-level page table. */ 582 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 583 584 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 585 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 586 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 587 588 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 589 590 /* use ONLY for statically allocated translation tables */ 591 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 592 593 /* 594 * Conversion functions: convert a page and protection to a page entry, 595 * and a page entry and page directory to the page they refer to. 596 */ 597 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 598 599 #if CONFIG_PGTABLE_LEVELS > 2 600 601 #define pmd_ERROR(e) \ 602 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 603 604 #define pud_none(pud) (!pud_val(pud)) 605 #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 606 #define pud_present(pud) pte_present(pud_pte(pud)) 607 #define pud_leaf(pud) pud_sect(pud) 608 #define pud_valid(pud) pte_valid(pud_pte(pud)) 609 610 static inline void set_pud(pud_t *pudp, pud_t pud) 611 { 612 #ifdef __PAGETABLE_PUD_FOLDED 613 if (in_swapper_pgdir(pudp)) { 614 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 615 return; 616 } 617 #endif /* __PAGETABLE_PUD_FOLDED */ 618 619 WRITE_ONCE(*pudp, pud); 620 621 if (pud_valid(pud)) { 622 dsb(ishst); 623 isb(); 624 } 625 } 626 627 static inline void pud_clear(pud_t *pudp) 628 { 629 set_pud(pudp, __pud(0)); 630 } 631 632 static inline phys_addr_t pud_page_paddr(pud_t pud) 633 { 634 return __pud_to_phys(pud); 635 } 636 637 static inline unsigned long pud_page_vaddr(pud_t pud) 638 { 639 return (unsigned long)__va(pud_page_paddr(pud)); 640 } 641 642 /* Find an entry in the second-level page table. */ 643 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 644 645 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 646 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 647 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 648 649 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 650 651 /* use ONLY for statically allocated translation tables */ 652 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 653 654 #else 655 656 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 657 658 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 659 #define pmd_set_fixmap(addr) NULL 660 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 661 #define pmd_clear_fixmap() 662 663 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 664 665 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 666 667 #if CONFIG_PGTABLE_LEVELS > 3 668 669 #define pud_ERROR(e) \ 670 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 671 672 #define p4d_none(p4d) (!p4d_val(p4d)) 673 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2)) 674 #define p4d_present(p4d) (p4d_val(p4d)) 675 676 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 677 { 678 if (in_swapper_pgdir(p4dp)) { 679 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 680 return; 681 } 682 683 WRITE_ONCE(*p4dp, p4d); 684 dsb(ishst); 685 isb(); 686 } 687 688 static inline void p4d_clear(p4d_t *p4dp) 689 { 690 set_p4d(p4dp, __p4d(0)); 691 } 692 693 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 694 { 695 return __p4d_to_phys(p4d); 696 } 697 698 static inline unsigned long p4d_page_vaddr(p4d_t p4d) 699 { 700 return (unsigned long)__va(p4d_page_paddr(p4d)); 701 } 702 703 /* Find an entry in the frst-level page table. */ 704 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 705 706 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 707 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr)) 708 #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 709 710 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 711 712 /* use ONLY for statically allocated translation tables */ 713 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 714 715 #else 716 717 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 718 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 719 720 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 721 #define pud_set_fixmap(addr) NULL 722 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 723 #define pud_clear_fixmap() 724 725 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 726 727 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 728 729 #define pgd_ERROR(e) \ 730 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 731 732 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 733 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 734 735 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 736 { 737 /* 738 * Normal and Normal-Tagged are two different memory types and indices 739 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 740 */ 741 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 742 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | 743 PTE_ATTRINDX_MASK; 744 /* preserve the hardware dirty information */ 745 if (pte_hw_dirty(pte)) 746 pte = pte_mkdirty(pte); 747 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 748 return pte; 749 } 750 751 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 752 { 753 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 754 } 755 756 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 757 extern int ptep_set_access_flags(struct vm_area_struct *vma, 758 unsigned long address, pte_t *ptep, 759 pte_t entry, int dirty); 760 761 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 762 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 763 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 764 unsigned long address, pmd_t *pmdp, 765 pmd_t entry, int dirty) 766 { 767 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 768 } 769 770 static inline int pud_devmap(pud_t pud) 771 { 772 return 0; 773 } 774 775 static inline int pgd_devmap(pgd_t pgd) 776 { 777 return 0; 778 } 779 #endif 780 781 /* 782 * Atomic pte/pmd modifications. 783 */ 784 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 785 static inline int __ptep_test_and_clear_young(pte_t *ptep) 786 { 787 pte_t old_pte, pte; 788 789 pte = READ_ONCE(*ptep); 790 do { 791 old_pte = pte; 792 pte = pte_mkold(pte); 793 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 794 pte_val(old_pte), pte_val(pte)); 795 } while (pte_val(pte) != pte_val(old_pte)); 796 797 return pte_young(pte); 798 } 799 800 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 801 unsigned long address, 802 pte_t *ptep) 803 { 804 return __ptep_test_and_clear_young(ptep); 805 } 806 807 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 808 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 809 unsigned long address, pte_t *ptep) 810 { 811 int young = ptep_test_and_clear_young(vma, address, ptep); 812 813 if (young) { 814 /* 815 * We can elide the trailing DSB here since the worst that can 816 * happen is that a CPU continues to use the young entry in its 817 * TLB and we mistakenly reclaim the associated page. The 818 * window for such an event is bounded by the next 819 * context-switch, which provides a DSB to complete the TLB 820 * invalidation. 821 */ 822 flush_tlb_page_nosync(vma, address); 823 } 824 825 return young; 826 } 827 828 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 829 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 830 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 831 unsigned long address, 832 pmd_t *pmdp) 833 { 834 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 835 } 836 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 837 838 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 839 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 840 unsigned long address, pte_t *ptep) 841 { 842 return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 843 } 844 845 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 846 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 847 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 848 unsigned long address, pmd_t *pmdp) 849 { 850 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 851 } 852 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 853 854 /* 855 * ptep_set_wrprotect - mark read-only while trasferring potential hardware 856 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 857 */ 858 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 859 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 860 { 861 pte_t old_pte, pte; 862 863 pte = READ_ONCE(*ptep); 864 do { 865 old_pte = pte; 866 pte = pte_wrprotect(pte); 867 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 868 pte_val(old_pte), pte_val(pte)); 869 } while (pte_val(pte) != pte_val(old_pte)); 870 } 871 872 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 873 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 874 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 875 unsigned long address, pmd_t *pmdp) 876 { 877 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 878 } 879 880 #define pmdp_establish pmdp_establish 881 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 882 unsigned long address, pmd_t *pmdp, pmd_t pmd) 883 { 884 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 885 } 886 #endif 887 888 /* 889 * Encode and decode a swap entry: 890 * bits 0-1: present (must be zero) 891 * bits 2-7: swap type 892 * bits 8-57: swap offset 893 * bit 58: PTE_PROT_NONE (must be zero) 894 */ 895 #define __SWP_TYPE_SHIFT 2 896 #define __SWP_TYPE_BITS 6 897 #define __SWP_OFFSET_BITS 50 898 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 899 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 900 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 901 902 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 903 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 904 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 905 906 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 907 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 908 909 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 910 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 911 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 912 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 913 914 /* 915 * Ensure that there are not more swap files than can be encoded in the kernel 916 * PTEs. 917 */ 918 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 919 920 extern int kern_addr_valid(unsigned long addr); 921 922 #ifdef CONFIG_ARM64_MTE 923 924 #define __HAVE_ARCH_PREPARE_TO_SWAP 925 static inline int arch_prepare_to_swap(struct page *page) 926 { 927 if (system_supports_mte()) 928 return mte_save_tags(page); 929 return 0; 930 } 931 932 #define __HAVE_ARCH_SWAP_INVALIDATE 933 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 934 { 935 if (system_supports_mte()) 936 mte_invalidate_tags(type, offset); 937 } 938 939 static inline void arch_swap_invalidate_area(int type) 940 { 941 if (system_supports_mte()) 942 mte_invalidate_tags_area(type); 943 } 944 945 #define __HAVE_ARCH_SWAP_RESTORE 946 static inline void arch_swap_restore(swp_entry_t entry, struct page *page) 947 { 948 if (system_supports_mte() && mte_restore_tags(entry, page)) 949 set_bit(PG_mte_tagged, &page->flags); 950 } 951 952 #endif /* CONFIG_ARM64_MTE */ 953 954 /* 955 * On AArch64, the cache coherency is handled via the set_pte_at() function. 956 */ 957 static inline void update_mmu_cache(struct vm_area_struct *vma, 958 unsigned long addr, pte_t *ptep) 959 { 960 /* 961 * We don't do anything here, so there's a very small chance of 962 * us retaking a user fault which we just fixed up. The alternative 963 * is doing a dsb(ishst), but that penalises the fastpath. 964 */ 965 } 966 967 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 968 969 #ifdef CONFIG_ARM64_PA_BITS_52 970 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 971 #else 972 #define phys_to_ttbr(addr) (addr) 973 #endif 974 975 /* 976 * On arm64 without hardware Access Flag, copying from user will fail because 977 * the pte is old and cannot be marked young. So we always end up with zeroed 978 * page after fork() + CoW for pfn mappings. We don't always have a 979 * hardware-managed access flag on arm64. 980 */ 981 static inline bool arch_faults_on_old_pte(void) 982 { 983 WARN_ON(preemptible()); 984 985 return !cpu_has_hw_af(); 986 } 987 #define arch_faults_on_old_pte arch_faults_on_old_pte 988 989 /* 990 * Experimentally, it's cheap to set the access flag in hardware and we 991 * benefit from prefaulting mappings as 'old' to start with. 992 */ 993 static inline bool arch_wants_old_prefaulted_pte(void) 994 { 995 return !arch_faults_on_old_pte(); 996 } 997 #define arch_wants_old_prefaulted_pte arch_wants_old_prefaulted_pte 998 999 static inline pgprot_t arch_filter_pgprot(pgprot_t prot) 1000 { 1001 if (cpus_have_const_cap(ARM64_HAS_EPAN)) 1002 return prot; 1003 1004 if (pgprot_val(prot) != pgprot_val(PAGE_EXECONLY)) 1005 return prot; 1006 1007 return PAGE_READONLY_EXEC; 1008 } 1009 1010 1011 #endif /* !__ASSEMBLY__ */ 1012 1013 #endif /* __ASM_PGTABLE_H */ 1014