1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space 22 * and fixed mappings 23 */ 24 #define VMALLOC_START (MODULES_END) 25 #define VMALLOC_END (VMEMMAP_START - SZ_256M) 26 27 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 28 29 #ifndef __ASSEMBLY__ 30 31 #include <asm/cmpxchg.h> 32 #include <asm/fixmap.h> 33 #include <linux/mmdebug.h> 34 #include <linux/mm_types.h> 35 #include <linux/sched.h> 36 37 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 38 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 39 40 /* Set stride and tlb_level in flush_*_tlb_range */ 41 #define flush_pmd_tlb_range(vma, addr, end) \ 42 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 43 #define flush_pud_tlb_range(vma, addr, end) \ 44 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 45 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 46 47 /* 48 * Outside of a few very special situations (e.g. hibernation), we always 49 * use broadcast TLB invalidation instructions, therefore a spurious page 50 * fault on one CPU which has been handled concurrently by another CPU 51 * does not need to perform additional invalidation. 52 */ 53 #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0) 54 55 /* 56 * ZERO_PAGE is a global shared page that is always zero: used 57 * for zero-mapped memory areas etc.. 58 */ 59 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 60 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 61 62 #define pte_ERROR(e) \ 63 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 64 65 /* 66 * Macros to convert between a physical address and its placement in a 67 * page table entry, taking care of 52-bit addresses. 68 */ 69 #ifdef CONFIG_ARM64_PA_BITS_52 70 static inline phys_addr_t __pte_to_phys(pte_t pte) 71 { 72 return (pte_val(pte) & PTE_ADDR_LOW) | 73 ((pte_val(pte) & PTE_ADDR_HIGH) << 36); 74 } 75 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 76 { 77 return (phys | (phys >> 36)) & PTE_ADDR_MASK; 78 } 79 #else 80 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 81 #define __phys_to_pte_val(phys) (phys) 82 #endif 83 84 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 85 #define pfn_pte(pfn,prot) \ 86 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 87 88 #define pte_none(pte) (!pte_val(pte)) 89 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 90 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 91 92 /* 93 * The following only work if pte_present(). Undefined behaviour otherwise. 94 */ 95 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 96 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 97 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 98 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 99 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 100 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 101 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 102 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 103 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 104 105 #define pte_cont_addr_end(addr, end) \ 106 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 107 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 108 }) 109 110 #define pmd_cont_addr_end(addr, end) \ 111 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 112 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 113 }) 114 115 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 116 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 117 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 118 119 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 120 /* 121 * Execute-only user mappings do not have the PTE_USER bit set. All valid 122 * kernel mappings have the PTE_UXN bit set. 123 */ 124 #define pte_valid_not_user(pte) \ 125 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 126 /* 127 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 128 * so that we don't erroneously return false for pages that have been 129 * remapped as PROT_NONE but are yet to be flushed from the TLB. 130 * Note that we can't make any assumptions based on the state of the access 131 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the 132 * TLB. 133 */ 134 #define pte_accessible(mm, pte) \ 135 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 136 137 /* 138 * p??_access_permitted() is true for valid user mappings (PTE_USER 139 * bit set, subject to the write permission check). For execute-only 140 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 141 * not set) must return false. PROT_NONE mappings do not have the 142 * PTE_VALID bit set. 143 */ 144 #define pte_access_permitted(pte, write) \ 145 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 146 #define pmd_access_permitted(pmd, write) \ 147 (pte_access_permitted(pmd_pte(pmd), (write))) 148 #define pud_access_permitted(pud, write) \ 149 (pte_access_permitted(pud_pte(pud), (write))) 150 151 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 152 { 153 pte_val(pte) &= ~pgprot_val(prot); 154 return pte; 155 } 156 157 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 158 { 159 pte_val(pte) |= pgprot_val(prot); 160 return pte; 161 } 162 163 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 164 { 165 pmd_val(pmd) &= ~pgprot_val(prot); 166 return pmd; 167 } 168 169 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 170 { 171 pmd_val(pmd) |= pgprot_val(prot); 172 return pmd; 173 } 174 175 static inline pte_t pte_mkwrite(pte_t pte) 176 { 177 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 178 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 179 return pte; 180 } 181 182 static inline pte_t pte_mkclean(pte_t pte) 183 { 184 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 185 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 186 187 return pte; 188 } 189 190 static inline pte_t pte_mkdirty(pte_t pte) 191 { 192 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 193 194 if (pte_write(pte)) 195 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 196 197 return pte; 198 } 199 200 static inline pte_t pte_wrprotect(pte_t pte) 201 { 202 /* 203 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 204 * clear), set the PTE_DIRTY bit. 205 */ 206 if (pte_hw_dirty(pte)) 207 pte = pte_mkdirty(pte); 208 209 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 210 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 211 return pte; 212 } 213 214 static inline pte_t pte_mkold(pte_t pte) 215 { 216 return clear_pte_bit(pte, __pgprot(PTE_AF)); 217 } 218 219 static inline pte_t pte_mkyoung(pte_t pte) 220 { 221 return set_pte_bit(pte, __pgprot(PTE_AF)); 222 } 223 224 static inline pte_t pte_mkspecial(pte_t pte) 225 { 226 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 227 } 228 229 static inline pte_t pte_mkcont(pte_t pte) 230 { 231 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 232 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 233 } 234 235 static inline pte_t pte_mknoncont(pte_t pte) 236 { 237 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 238 } 239 240 static inline pte_t pte_mkpresent(pte_t pte) 241 { 242 return set_pte_bit(pte, __pgprot(PTE_VALID)); 243 } 244 245 static inline pmd_t pmd_mkcont(pmd_t pmd) 246 { 247 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 248 } 249 250 static inline pte_t pte_mkdevmap(pte_t pte) 251 { 252 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 253 } 254 255 static inline void set_pte(pte_t *ptep, pte_t pte) 256 { 257 WRITE_ONCE(*ptep, pte); 258 259 /* 260 * Only if the new pte is valid and kernel, otherwise TLB maintenance 261 * or update_mmu_cache() have the necessary barriers. 262 */ 263 if (pte_valid_not_user(pte)) { 264 dsb(ishst); 265 isb(); 266 } 267 } 268 269 extern void __sync_icache_dcache(pte_t pteval); 270 271 /* 272 * PTE bits configuration in the presence of hardware Dirty Bit Management 273 * (PTE_WRITE == PTE_DBM): 274 * 275 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 276 * 0 0 | 1 0 0 277 * 0 1 | 1 1 0 278 * 1 0 | 1 0 1 279 * 1 1 | 0 1 x 280 * 281 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 282 * the page fault mechanism. Checking the dirty status of a pte becomes: 283 * 284 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 285 */ 286 287 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, 288 pte_t pte) 289 { 290 pte_t old_pte; 291 292 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 293 return; 294 295 old_pte = READ_ONCE(*ptep); 296 297 if (!pte_valid(old_pte) || !pte_valid(pte)) 298 return; 299 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 300 return; 301 302 /* 303 * Check for potential race with hardware updates of the pte 304 * (ptep_set_access_flags safely changes valid ptes without going 305 * through an invalid entry). 306 */ 307 VM_WARN_ONCE(!pte_young(pte), 308 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 309 __func__, pte_val(old_pte), pte_val(pte)); 310 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 311 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 312 __func__, pte_val(old_pte), pte_val(pte)); 313 } 314 315 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 316 pte_t *ptep, pte_t pte) 317 { 318 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 319 __sync_icache_dcache(pte); 320 321 /* 322 * If the PTE would provide user space access to the tags associated 323 * with it then ensure that the MTE tags are synchronised. Although 324 * pte_access_permitted() returns false for exec only mappings, they 325 * don't expose tags (instruction fetches don't check tags). 326 */ 327 if (system_supports_mte() && pte_access_permitted(pte, false) && 328 !pte_special(pte)) { 329 pte_t old_pte = READ_ONCE(*ptep); 330 /* 331 * We only need to synchronise if the new PTE has tags enabled 332 * or if swapping in (in which case another mapping may have 333 * set tags in the past even if this PTE isn't tagged). 334 * (!pte_none() && !pte_present()) is an open coded version of 335 * is_swap_pte() 336 */ 337 if (pte_tagged(pte) || (!pte_none(old_pte) && !pte_present(old_pte))) 338 mte_sync_tags(old_pte, pte); 339 } 340 341 __check_racy_pte_update(mm, ptep, pte); 342 343 set_pte(ptep, pte); 344 } 345 346 /* 347 * Huge pte definitions. 348 */ 349 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 350 351 /* 352 * Hugetlb definitions. 353 */ 354 #define HUGE_MAX_HSTATE 4 355 #define HPAGE_SHIFT PMD_SHIFT 356 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 357 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 358 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 359 360 static inline pte_t pgd_pte(pgd_t pgd) 361 { 362 return __pte(pgd_val(pgd)); 363 } 364 365 static inline pte_t p4d_pte(p4d_t p4d) 366 { 367 return __pte(p4d_val(p4d)); 368 } 369 370 static inline pte_t pud_pte(pud_t pud) 371 { 372 return __pte(pud_val(pud)); 373 } 374 375 static inline pud_t pte_pud(pte_t pte) 376 { 377 return __pud(pte_val(pte)); 378 } 379 380 static inline pmd_t pud_pmd(pud_t pud) 381 { 382 return __pmd(pud_val(pud)); 383 } 384 385 static inline pte_t pmd_pte(pmd_t pmd) 386 { 387 return __pte(pmd_val(pmd)); 388 } 389 390 static inline pmd_t pte_pmd(pte_t pte) 391 { 392 return __pmd(pte_val(pte)); 393 } 394 395 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 396 { 397 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 398 } 399 400 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 401 { 402 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 403 } 404 405 #define __HAVE_ARCH_PTE_SWP_EXCLUSIVE 406 static inline pte_t pte_swp_mkexclusive(pte_t pte) 407 { 408 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 409 } 410 411 static inline int pte_swp_exclusive(pte_t pte) 412 { 413 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 414 } 415 416 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 417 { 418 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 419 } 420 421 #ifdef CONFIG_NUMA_BALANCING 422 /* 423 * See the comment in include/linux/pgtable.h 424 */ 425 static inline int pte_protnone(pte_t pte) 426 { 427 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 428 } 429 430 static inline int pmd_protnone(pmd_t pmd) 431 { 432 return pte_protnone(pmd_pte(pmd)); 433 } 434 #endif 435 436 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) 437 438 static inline int pmd_present(pmd_t pmd) 439 { 440 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); 441 } 442 443 /* 444 * THP definitions. 445 */ 446 447 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 448 static inline int pmd_trans_huge(pmd_t pmd) 449 { 450 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 451 } 452 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 453 454 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 455 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 456 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 457 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 458 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 459 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 460 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 461 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 462 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 463 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 464 465 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 466 { 467 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); 468 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); 469 470 return pmd; 471 } 472 473 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 474 475 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 476 477 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 478 479 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 480 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 481 #endif 482 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 483 { 484 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 485 } 486 487 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 488 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 489 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 490 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 491 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 492 493 #define pud_young(pud) pte_young(pud_pte(pud)) 494 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 495 #define pud_write(pud) pte_write(pud_pte(pud)) 496 497 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 498 499 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 500 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 501 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 502 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 503 504 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 505 #define set_pud_at(mm, addr, pudp, pud) set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)) 506 507 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 508 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 509 510 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 511 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 512 513 #define __pgprot_modify(prot,mask,bits) \ 514 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 515 516 #define pgprot_nx(prot) \ 517 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 518 519 /* 520 * Mark the prot value as uncacheable and unbufferable. 521 */ 522 #define pgprot_noncached(prot) \ 523 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 524 #define pgprot_writecombine(prot) \ 525 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 526 #define pgprot_device(prot) \ 527 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 528 #define pgprot_tagged(prot) \ 529 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 530 #define pgprot_mhp pgprot_tagged 531 /* 532 * DMA allocations for non-coherent devices use what the Arm architecture calls 533 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 534 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 535 * is intended for MMIO and thus forbids speculation, preserves access size, 536 * requires strict alignment and can also force write responses to come from the 537 * endpoint. 538 */ 539 #define pgprot_dmacoherent(prot) \ 540 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 541 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 542 543 #define __HAVE_PHYS_MEM_ACCESS_PROT 544 struct file; 545 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 546 unsigned long size, pgprot_t vma_prot); 547 548 #define pmd_none(pmd) (!pmd_val(pmd)) 549 550 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 551 PMD_TYPE_TABLE) 552 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 553 PMD_TYPE_SECT) 554 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 555 #define pmd_bad(pmd) (!pmd_table(pmd)) 556 557 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 558 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 559 560 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 561 static inline bool pud_sect(pud_t pud) { return false; } 562 static inline bool pud_table(pud_t pud) { return true; } 563 #else 564 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 565 PUD_TYPE_SECT) 566 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 567 PUD_TYPE_TABLE) 568 #endif 569 570 extern pgd_t init_pg_dir[PTRS_PER_PGD]; 571 extern pgd_t init_pg_end[]; 572 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 573 extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 574 extern pgd_t idmap_pg_end[]; 575 extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 576 extern pgd_t reserved_pg_dir[PTRS_PER_PGD]; 577 578 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 579 580 static inline bool in_swapper_pgdir(void *addr) 581 { 582 return ((unsigned long)addr & PAGE_MASK) == 583 ((unsigned long)swapper_pg_dir & PAGE_MASK); 584 } 585 586 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 587 { 588 #ifdef __PAGETABLE_PMD_FOLDED 589 if (in_swapper_pgdir(pmdp)) { 590 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 591 return; 592 } 593 #endif /* __PAGETABLE_PMD_FOLDED */ 594 595 WRITE_ONCE(*pmdp, pmd); 596 597 if (pmd_valid(pmd)) { 598 dsb(ishst); 599 isb(); 600 } 601 } 602 603 static inline void pmd_clear(pmd_t *pmdp) 604 { 605 set_pmd(pmdp, __pmd(0)); 606 } 607 608 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 609 { 610 return __pmd_to_phys(pmd); 611 } 612 613 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 614 { 615 return (unsigned long)__va(pmd_page_paddr(pmd)); 616 } 617 618 /* Find an entry in the third-level page table. */ 619 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 620 621 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 622 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 623 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 624 625 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 626 627 /* use ONLY for statically allocated translation tables */ 628 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 629 630 /* 631 * Conversion functions: convert a page and protection to a page entry, 632 * and a page entry and page directory to the page they refer to. 633 */ 634 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 635 636 #if CONFIG_PGTABLE_LEVELS > 2 637 638 #define pmd_ERROR(e) \ 639 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 640 641 #define pud_none(pud) (!pud_val(pud)) 642 #define pud_bad(pud) (!pud_table(pud)) 643 #define pud_present(pud) pte_present(pud_pte(pud)) 644 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 645 #define pud_valid(pud) pte_valid(pud_pte(pud)) 646 647 static inline void set_pud(pud_t *pudp, pud_t pud) 648 { 649 #ifdef __PAGETABLE_PUD_FOLDED 650 if (in_swapper_pgdir(pudp)) { 651 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 652 return; 653 } 654 #endif /* __PAGETABLE_PUD_FOLDED */ 655 656 WRITE_ONCE(*pudp, pud); 657 658 if (pud_valid(pud)) { 659 dsb(ishst); 660 isb(); 661 } 662 } 663 664 static inline void pud_clear(pud_t *pudp) 665 { 666 set_pud(pudp, __pud(0)); 667 } 668 669 static inline phys_addr_t pud_page_paddr(pud_t pud) 670 { 671 return __pud_to_phys(pud); 672 } 673 674 static inline pmd_t *pud_pgtable(pud_t pud) 675 { 676 return (pmd_t *)__va(pud_page_paddr(pud)); 677 } 678 679 /* Find an entry in the second-level page table. */ 680 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 681 682 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 683 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 684 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 685 686 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 687 688 /* use ONLY for statically allocated translation tables */ 689 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 690 691 #else 692 693 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 694 695 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 696 #define pmd_set_fixmap(addr) NULL 697 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 698 #define pmd_clear_fixmap() 699 700 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 701 702 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 703 704 #if CONFIG_PGTABLE_LEVELS > 3 705 706 #define pud_ERROR(e) \ 707 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 708 709 #define p4d_none(p4d) (!p4d_val(p4d)) 710 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2)) 711 #define p4d_present(p4d) (p4d_val(p4d)) 712 713 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 714 { 715 if (in_swapper_pgdir(p4dp)) { 716 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 717 return; 718 } 719 720 WRITE_ONCE(*p4dp, p4d); 721 dsb(ishst); 722 isb(); 723 } 724 725 static inline void p4d_clear(p4d_t *p4dp) 726 { 727 set_p4d(p4dp, __p4d(0)); 728 } 729 730 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 731 { 732 return __p4d_to_phys(p4d); 733 } 734 735 static inline pud_t *p4d_pgtable(p4d_t p4d) 736 { 737 return (pud_t *)__va(p4d_page_paddr(p4d)); 738 } 739 740 /* Find an entry in the first-level page table. */ 741 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 742 743 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 744 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr)) 745 #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 746 747 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 748 749 /* use ONLY for statically allocated translation tables */ 750 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 751 752 #else 753 754 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 755 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 756 757 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 758 #define pud_set_fixmap(addr) NULL 759 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 760 #define pud_clear_fixmap() 761 762 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 763 764 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 765 766 #define pgd_ERROR(e) \ 767 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 768 769 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 770 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 771 772 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 773 { 774 /* 775 * Normal and Normal-Tagged are two different memory types and indices 776 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 777 */ 778 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 779 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | 780 PTE_ATTRINDX_MASK; 781 /* preserve the hardware dirty information */ 782 if (pte_hw_dirty(pte)) 783 pte = pte_mkdirty(pte); 784 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 785 return pte; 786 } 787 788 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 789 { 790 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 791 } 792 793 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 794 extern int ptep_set_access_flags(struct vm_area_struct *vma, 795 unsigned long address, pte_t *ptep, 796 pte_t entry, int dirty); 797 798 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 799 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 800 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 801 unsigned long address, pmd_t *pmdp, 802 pmd_t entry, int dirty) 803 { 804 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 805 } 806 807 static inline int pud_devmap(pud_t pud) 808 { 809 return 0; 810 } 811 812 static inline int pgd_devmap(pgd_t pgd) 813 { 814 return 0; 815 } 816 #endif 817 818 /* 819 * Atomic pte/pmd modifications. 820 */ 821 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 822 static inline int __ptep_test_and_clear_young(pte_t *ptep) 823 { 824 pte_t old_pte, pte; 825 826 pte = READ_ONCE(*ptep); 827 do { 828 old_pte = pte; 829 pte = pte_mkold(pte); 830 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 831 pte_val(old_pte), pte_val(pte)); 832 } while (pte_val(pte) != pte_val(old_pte)); 833 834 return pte_young(pte); 835 } 836 837 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 838 unsigned long address, 839 pte_t *ptep) 840 { 841 return __ptep_test_and_clear_young(ptep); 842 } 843 844 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 845 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 846 unsigned long address, pte_t *ptep) 847 { 848 int young = ptep_test_and_clear_young(vma, address, ptep); 849 850 if (young) { 851 /* 852 * We can elide the trailing DSB here since the worst that can 853 * happen is that a CPU continues to use the young entry in its 854 * TLB and we mistakenly reclaim the associated page. The 855 * window for such an event is bounded by the next 856 * context-switch, which provides a DSB to complete the TLB 857 * invalidation. 858 */ 859 flush_tlb_page_nosync(vma, address); 860 } 861 862 return young; 863 } 864 865 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 866 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 867 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 868 unsigned long address, 869 pmd_t *pmdp) 870 { 871 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 872 } 873 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 874 875 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 876 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 877 unsigned long address, pte_t *ptep) 878 { 879 return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 880 } 881 882 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 883 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 884 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 885 unsigned long address, pmd_t *pmdp) 886 { 887 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 888 } 889 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 890 891 /* 892 * ptep_set_wrprotect - mark read-only while trasferring potential hardware 893 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 894 */ 895 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 896 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 897 { 898 pte_t old_pte, pte; 899 900 pte = READ_ONCE(*ptep); 901 do { 902 old_pte = pte; 903 pte = pte_wrprotect(pte); 904 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 905 pte_val(old_pte), pte_val(pte)); 906 } while (pte_val(pte) != pte_val(old_pte)); 907 } 908 909 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 910 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 911 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 912 unsigned long address, pmd_t *pmdp) 913 { 914 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 915 } 916 917 #define pmdp_establish pmdp_establish 918 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 919 unsigned long address, pmd_t *pmdp, pmd_t pmd) 920 { 921 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 922 } 923 #endif 924 925 /* 926 * Encode and decode a swap entry: 927 * bits 0-1: present (must be zero) 928 * bits 2: remember PG_anon_exclusive 929 * bits 3-7: swap type 930 * bits 8-57: swap offset 931 * bit 58: PTE_PROT_NONE (must be zero) 932 */ 933 #define __SWP_TYPE_SHIFT 3 934 #define __SWP_TYPE_BITS 5 935 #define __SWP_OFFSET_BITS 50 936 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 937 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 938 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 939 940 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 941 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 942 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 943 944 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 945 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 946 947 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 948 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 949 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 950 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 951 952 /* 953 * Ensure that there are not more swap files than can be encoded in the kernel 954 * PTEs. 955 */ 956 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 957 958 extern int kern_addr_valid(unsigned long addr); 959 960 #ifdef CONFIG_ARM64_MTE 961 962 #define __HAVE_ARCH_PREPARE_TO_SWAP 963 static inline int arch_prepare_to_swap(struct page *page) 964 { 965 if (system_supports_mte()) 966 return mte_save_tags(page); 967 return 0; 968 } 969 970 #define __HAVE_ARCH_SWAP_INVALIDATE 971 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 972 { 973 if (system_supports_mte()) 974 mte_invalidate_tags(type, offset); 975 } 976 977 static inline void arch_swap_invalidate_area(int type) 978 { 979 if (system_supports_mte()) 980 mte_invalidate_tags_area(type); 981 } 982 983 #define __HAVE_ARCH_SWAP_RESTORE 984 static inline void arch_swap_restore(swp_entry_t entry, struct page *page) 985 { 986 if (system_supports_mte() && mte_restore_tags(entry, page)) 987 set_bit(PG_mte_tagged, &page->flags); 988 } 989 990 #endif /* CONFIG_ARM64_MTE */ 991 992 /* 993 * On AArch64, the cache coherency is handled via the set_pte_at() function. 994 */ 995 static inline void update_mmu_cache(struct vm_area_struct *vma, 996 unsigned long addr, pte_t *ptep) 997 { 998 /* 999 * We don't do anything here, so there's a very small chance of 1000 * us retaking a user fault which we just fixed up. The alternative 1001 * is doing a dsb(ishst), but that penalises the fastpath. 1002 */ 1003 } 1004 1005 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1006 1007 #ifdef CONFIG_ARM64_PA_BITS_52 1008 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1009 #else 1010 #define phys_to_ttbr(addr) (addr) 1011 #endif 1012 1013 /* 1014 * On arm64 without hardware Access Flag, copying from user will fail because 1015 * the pte is old and cannot be marked young. So we always end up with zeroed 1016 * page after fork() + CoW for pfn mappings. We don't always have a 1017 * hardware-managed access flag on arm64. 1018 */ 1019 static inline bool arch_faults_on_old_pte(void) 1020 { 1021 WARN_ON(preemptible()); 1022 1023 return !cpu_has_hw_af(); 1024 } 1025 #define arch_faults_on_old_pte arch_faults_on_old_pte 1026 1027 /* 1028 * Experimentally, it's cheap to set the access flag in hardware and we 1029 * benefit from prefaulting mappings as 'old' to start with. 1030 */ 1031 static inline bool arch_wants_old_prefaulted_pte(void) 1032 { 1033 return !arch_faults_on_old_pte(); 1034 } 1035 #define arch_wants_old_prefaulted_pte arch_wants_old_prefaulted_pte 1036 1037 static inline bool pud_sect_supported(void) 1038 { 1039 return PAGE_SIZE == SZ_4K; 1040 } 1041 1042 1043 #endif /* !__ASSEMBLY__ */ 1044 1045 #endif /* __ASM_PGTABLE_H */ 1046