1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/pgtable-hwdef.h> 13 #include <asm/pgtable-prot.h> 14 #include <asm/tlbflush.h> 15 16 /* 17 * VMALLOC range. 18 * 19 * VMALLOC_START: beginning of the kernel vmalloc space 20 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space 21 * and fixed mappings 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #define VMALLOC_END (- PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 25 26 #define FIRST_USER_ADDRESS 0UL 27 28 #ifndef __ASSEMBLY__ 29 30 #include <asm/cmpxchg.h> 31 #include <asm/fixmap.h> 32 #include <linux/mmdebug.h> 33 #include <linux/mm_types.h> 34 #include <linux/sched.h> 35 36 extern struct page *vmemmap; 37 38 extern void __pte_error(const char *file, int line, unsigned long val); 39 extern void __pmd_error(const char *file, int line, unsigned long val); 40 extern void __pud_error(const char *file, int line, unsigned long val); 41 extern void __pgd_error(const char *file, int line, unsigned long val); 42 43 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 44 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 45 46 /* Set stride and tlb_level in flush_*_tlb_range */ 47 #define flush_pmd_tlb_range(vma, addr, end) \ 48 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 49 #define flush_pud_tlb_range(vma, addr, end) \ 50 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 51 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 52 53 /* 54 * ZERO_PAGE is a global shared page that is always zero: used 55 * for zero-mapped memory areas etc.. 56 */ 57 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 58 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 59 60 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 61 62 /* 63 * Macros to convert between a physical address and its placement in a 64 * page table entry, taking care of 52-bit addresses. 65 */ 66 #ifdef CONFIG_ARM64_PA_BITS_52 67 #define __pte_to_phys(pte) \ 68 ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 69 #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 70 #else 71 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 72 #define __phys_to_pte_val(phys) (phys) 73 #endif 74 75 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 76 #define pfn_pte(pfn,prot) \ 77 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 78 79 #define pte_none(pte) (!pte_val(pte)) 80 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 81 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 82 83 /* 84 * The following only work if pte_present(). Undefined behaviour otherwise. 85 */ 86 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 87 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 88 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 89 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 90 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 91 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 92 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 93 94 #define pte_cont_addr_end(addr, end) \ 95 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 96 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 97 }) 98 99 #define pmd_cont_addr_end(addr, end) \ 100 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 101 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 102 }) 103 104 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 105 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 106 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 107 108 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 109 #define pte_valid_not_user(pte) \ 110 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) 111 #define pte_valid_young(pte) \ 112 ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 113 #define pte_valid_user(pte) \ 114 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 115 116 /* 117 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 118 * so that we don't erroneously return false for pages that have been 119 * remapped as PROT_NONE but are yet to be flushed from the TLB. 120 */ 121 #define pte_accessible(mm, pte) \ 122 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 123 124 /* 125 * p??_access_permitted() is true for valid user mappings (subject to the 126 * write permission check). PROT_NONE mappings do not have the PTE_VALID bit 127 * set. 128 */ 129 #define pte_access_permitted(pte, write) \ 130 (pte_valid_user(pte) && (!(write) || pte_write(pte))) 131 #define pmd_access_permitted(pmd, write) \ 132 (pte_access_permitted(pmd_pte(pmd), (write))) 133 #define pud_access_permitted(pud, write) \ 134 (pte_access_permitted(pud_pte(pud), (write))) 135 136 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 137 { 138 pte_val(pte) &= ~pgprot_val(prot); 139 return pte; 140 } 141 142 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 143 { 144 pte_val(pte) |= pgprot_val(prot); 145 return pte; 146 } 147 148 static inline pte_t pte_wrprotect(pte_t pte) 149 { 150 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 151 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 152 return pte; 153 } 154 155 static inline pte_t pte_mkwrite(pte_t pte) 156 { 157 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 158 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 159 return pte; 160 } 161 162 static inline pte_t pte_mkclean(pte_t pte) 163 { 164 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 165 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 166 167 return pte; 168 } 169 170 static inline pte_t pte_mkdirty(pte_t pte) 171 { 172 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 173 174 if (pte_write(pte)) 175 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 176 177 return pte; 178 } 179 180 static inline pte_t pte_mkold(pte_t pte) 181 { 182 return clear_pte_bit(pte, __pgprot(PTE_AF)); 183 } 184 185 static inline pte_t pte_mkyoung(pte_t pte) 186 { 187 return set_pte_bit(pte, __pgprot(PTE_AF)); 188 } 189 190 static inline pte_t pte_mkspecial(pte_t pte) 191 { 192 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 193 } 194 195 static inline pte_t pte_mkcont(pte_t pte) 196 { 197 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 198 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 199 } 200 201 static inline pte_t pte_mknoncont(pte_t pte) 202 { 203 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 204 } 205 206 static inline pte_t pte_mkpresent(pte_t pte) 207 { 208 return set_pte_bit(pte, __pgprot(PTE_VALID)); 209 } 210 211 static inline pmd_t pmd_mkcont(pmd_t pmd) 212 { 213 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 214 } 215 216 static inline pte_t pte_mkdevmap(pte_t pte) 217 { 218 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 219 } 220 221 static inline void set_pte(pte_t *ptep, pte_t pte) 222 { 223 WRITE_ONCE(*ptep, pte); 224 225 /* 226 * Only if the new pte is valid and kernel, otherwise TLB maintenance 227 * or update_mmu_cache() have the necessary barriers. 228 */ 229 if (pte_valid_not_user(pte)) { 230 dsb(ishst); 231 isb(); 232 } 233 } 234 235 extern void __sync_icache_dcache(pte_t pteval); 236 237 /* 238 * PTE bits configuration in the presence of hardware Dirty Bit Management 239 * (PTE_WRITE == PTE_DBM): 240 * 241 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 242 * 0 0 | 1 0 0 243 * 0 1 | 1 1 0 244 * 1 0 | 1 0 1 245 * 1 1 | 0 1 x 246 * 247 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 248 * the page fault mechanism. Checking the dirty status of a pte becomes: 249 * 250 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 251 */ 252 253 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, 254 pte_t pte) 255 { 256 pte_t old_pte; 257 258 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 259 return; 260 261 old_pte = READ_ONCE(*ptep); 262 263 if (!pte_valid(old_pte) || !pte_valid(pte)) 264 return; 265 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 266 return; 267 268 /* 269 * Check for potential race with hardware updates of the pte 270 * (ptep_set_access_flags safely changes valid ptes without going 271 * through an invalid entry). 272 */ 273 VM_WARN_ONCE(!pte_young(pte), 274 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 275 __func__, pte_val(old_pte), pte_val(pte)); 276 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 277 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 278 __func__, pte_val(old_pte), pte_val(pte)); 279 } 280 281 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 282 pte_t *ptep, pte_t pte) 283 { 284 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 285 __sync_icache_dcache(pte); 286 287 __check_racy_pte_update(mm, ptep, pte); 288 289 set_pte(ptep, pte); 290 } 291 292 /* 293 * Huge pte definitions. 294 */ 295 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 296 297 /* 298 * Hugetlb definitions. 299 */ 300 #define HUGE_MAX_HSTATE 4 301 #define HPAGE_SHIFT PMD_SHIFT 302 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 303 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 304 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 305 306 static inline pte_t pgd_pte(pgd_t pgd) 307 { 308 return __pte(pgd_val(pgd)); 309 } 310 311 static inline pte_t p4d_pte(p4d_t p4d) 312 { 313 return __pte(p4d_val(p4d)); 314 } 315 316 static inline pte_t pud_pte(pud_t pud) 317 { 318 return __pte(pud_val(pud)); 319 } 320 321 static inline pud_t pte_pud(pte_t pte) 322 { 323 return __pud(pte_val(pte)); 324 } 325 326 static inline pmd_t pud_pmd(pud_t pud) 327 { 328 return __pmd(pud_val(pud)); 329 } 330 331 static inline pte_t pmd_pte(pmd_t pmd) 332 { 333 return __pte(pmd_val(pmd)); 334 } 335 336 static inline pmd_t pte_pmd(pte_t pte) 337 { 338 return __pmd(pte_val(pte)); 339 } 340 341 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 342 { 343 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 344 } 345 346 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 347 { 348 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 349 } 350 351 #ifdef CONFIG_NUMA_BALANCING 352 /* 353 * See the comment in include/linux/pgtable.h 354 */ 355 static inline int pte_protnone(pte_t pte) 356 { 357 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 358 } 359 360 static inline int pmd_protnone(pmd_t pmd) 361 { 362 return pte_protnone(pmd_pte(pmd)); 363 } 364 #endif 365 366 /* 367 * THP definitions. 368 */ 369 370 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 371 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 372 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 373 374 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 375 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 376 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 377 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 378 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 379 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 380 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 381 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 382 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 383 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 384 #define pmd_mkinvalid(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) 385 386 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 387 388 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 389 390 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 391 392 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 393 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 394 #endif 395 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 396 { 397 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 398 } 399 400 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 401 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 402 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 403 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 404 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 405 406 #define pud_young(pud) pte_young(pud_pte(pud)) 407 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 408 #define pud_write(pud) pte_write(pud_pte(pud)) 409 410 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 411 412 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 413 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 414 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 415 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 416 417 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 418 419 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 420 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 421 422 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 423 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 424 425 #define __pgprot_modify(prot,mask,bits) \ 426 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 427 428 #define pgprot_nx(prot) \ 429 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 430 431 /* 432 * Mark the prot value as uncacheable and unbufferable. 433 */ 434 #define pgprot_noncached(prot) \ 435 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 436 #define pgprot_writecombine(prot) \ 437 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 438 #define pgprot_device(prot) \ 439 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 440 /* 441 * DMA allocations for non-coherent devices use what the Arm architecture calls 442 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 443 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 444 * is intended for MMIO and thus forbids speculation, preserves access size, 445 * requires strict alignment and can also force write responses to come from the 446 * endpoint. 447 */ 448 #define pgprot_dmacoherent(prot) \ 449 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 450 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 451 452 #define __HAVE_PHYS_MEM_ACCESS_PROT 453 struct file; 454 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 455 unsigned long size, pgprot_t vma_prot); 456 457 #define pmd_none(pmd) (!pmd_val(pmd)) 458 459 #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 460 461 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 462 PMD_TYPE_TABLE) 463 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 464 PMD_TYPE_SECT) 465 #define pmd_leaf(pmd) pmd_sect(pmd) 466 467 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 468 static inline bool pud_sect(pud_t pud) { return false; } 469 static inline bool pud_table(pud_t pud) { return true; } 470 #else 471 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 472 PUD_TYPE_SECT) 473 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 474 PUD_TYPE_TABLE) 475 #endif 476 477 extern pgd_t init_pg_dir[PTRS_PER_PGD]; 478 extern pgd_t init_pg_end[]; 479 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 480 extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 481 extern pgd_t idmap_pg_end[]; 482 extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 483 484 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 485 486 static inline bool in_swapper_pgdir(void *addr) 487 { 488 return ((unsigned long)addr & PAGE_MASK) == 489 ((unsigned long)swapper_pg_dir & PAGE_MASK); 490 } 491 492 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 493 { 494 #ifdef __PAGETABLE_PMD_FOLDED 495 if (in_swapper_pgdir(pmdp)) { 496 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 497 return; 498 } 499 #endif /* __PAGETABLE_PMD_FOLDED */ 500 501 WRITE_ONCE(*pmdp, pmd); 502 503 if (pmd_valid(pmd)) { 504 dsb(ishst); 505 isb(); 506 } 507 } 508 509 static inline void pmd_clear(pmd_t *pmdp) 510 { 511 set_pmd(pmdp, __pmd(0)); 512 } 513 514 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 515 { 516 return __pmd_to_phys(pmd); 517 } 518 519 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 520 { 521 return (unsigned long)__va(pmd_page_paddr(pmd)); 522 } 523 524 /* Find an entry in the third-level page table. */ 525 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 526 527 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 528 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 529 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 530 531 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 532 533 /* use ONLY for statically allocated translation tables */ 534 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 535 536 /* 537 * Conversion functions: convert a page and protection to a page entry, 538 * and a page entry and page directory to the page they refer to. 539 */ 540 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 541 542 #if CONFIG_PGTABLE_LEVELS > 2 543 544 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 545 546 #define pud_none(pud) (!pud_val(pud)) 547 #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 548 #define pud_present(pud) pte_present(pud_pte(pud)) 549 #define pud_leaf(pud) pud_sect(pud) 550 #define pud_valid(pud) pte_valid(pud_pte(pud)) 551 552 static inline void set_pud(pud_t *pudp, pud_t pud) 553 { 554 #ifdef __PAGETABLE_PUD_FOLDED 555 if (in_swapper_pgdir(pudp)) { 556 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 557 return; 558 } 559 #endif /* __PAGETABLE_PUD_FOLDED */ 560 561 WRITE_ONCE(*pudp, pud); 562 563 if (pud_valid(pud)) { 564 dsb(ishst); 565 isb(); 566 } 567 } 568 569 static inline void pud_clear(pud_t *pudp) 570 { 571 set_pud(pudp, __pud(0)); 572 } 573 574 static inline phys_addr_t pud_page_paddr(pud_t pud) 575 { 576 return __pud_to_phys(pud); 577 } 578 579 static inline unsigned long pud_page_vaddr(pud_t pud) 580 { 581 return (unsigned long)__va(pud_page_paddr(pud)); 582 } 583 584 /* Find an entry in the second-level page table. */ 585 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 586 587 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 588 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 589 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 590 591 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 592 593 /* use ONLY for statically allocated translation tables */ 594 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 595 596 #else 597 598 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 599 600 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 601 #define pmd_set_fixmap(addr) NULL 602 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 603 #define pmd_clear_fixmap() 604 605 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 606 607 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 608 609 #if CONFIG_PGTABLE_LEVELS > 3 610 611 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 612 613 #define p4d_none(p4d) (!p4d_val(p4d)) 614 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2)) 615 #define p4d_present(p4d) (p4d_val(p4d)) 616 617 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 618 { 619 if (in_swapper_pgdir(p4dp)) { 620 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 621 return; 622 } 623 624 WRITE_ONCE(*p4dp, p4d); 625 dsb(ishst); 626 isb(); 627 } 628 629 static inline void p4d_clear(p4d_t *p4dp) 630 { 631 set_p4d(p4dp, __p4d(0)); 632 } 633 634 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 635 { 636 return __p4d_to_phys(p4d); 637 } 638 639 static inline unsigned long p4d_page_vaddr(p4d_t p4d) 640 { 641 return (unsigned long)__va(p4d_page_paddr(p4d)); 642 } 643 644 /* Find an entry in the frst-level page table. */ 645 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 646 647 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 648 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr)) 649 #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 650 651 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 652 653 /* use ONLY for statically allocated translation tables */ 654 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 655 656 #else 657 658 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 659 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 660 661 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 662 #define pud_set_fixmap(addr) NULL 663 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 664 #define pud_clear_fixmap() 665 666 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 667 668 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 669 670 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 671 672 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 673 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 674 675 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 676 { 677 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 678 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP; 679 /* preserve the hardware dirty information */ 680 if (pte_hw_dirty(pte)) 681 pte = pte_mkdirty(pte); 682 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 683 return pte; 684 } 685 686 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 687 { 688 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 689 } 690 691 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 692 extern int ptep_set_access_flags(struct vm_area_struct *vma, 693 unsigned long address, pte_t *ptep, 694 pte_t entry, int dirty); 695 696 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 697 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 698 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 699 unsigned long address, pmd_t *pmdp, 700 pmd_t entry, int dirty) 701 { 702 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 703 } 704 705 static inline int pud_devmap(pud_t pud) 706 { 707 return 0; 708 } 709 710 static inline int pgd_devmap(pgd_t pgd) 711 { 712 return 0; 713 } 714 #endif 715 716 /* 717 * Atomic pte/pmd modifications. 718 */ 719 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 720 static inline int __ptep_test_and_clear_young(pte_t *ptep) 721 { 722 pte_t old_pte, pte; 723 724 pte = READ_ONCE(*ptep); 725 do { 726 old_pte = pte; 727 pte = pte_mkold(pte); 728 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 729 pte_val(old_pte), pte_val(pte)); 730 } while (pte_val(pte) != pte_val(old_pte)); 731 732 return pte_young(pte); 733 } 734 735 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 736 unsigned long address, 737 pte_t *ptep) 738 { 739 return __ptep_test_and_clear_young(ptep); 740 } 741 742 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 743 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 744 unsigned long address, pte_t *ptep) 745 { 746 int young = ptep_test_and_clear_young(vma, address, ptep); 747 748 if (young) { 749 /* 750 * We can elide the trailing DSB here since the worst that can 751 * happen is that a CPU continues to use the young entry in its 752 * TLB and we mistakenly reclaim the associated page. The 753 * window for such an event is bounded by the next 754 * context-switch, which provides a DSB to complete the TLB 755 * invalidation. 756 */ 757 flush_tlb_page_nosync(vma, address); 758 } 759 760 return young; 761 } 762 763 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 764 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 765 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 766 unsigned long address, 767 pmd_t *pmdp) 768 { 769 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 770 } 771 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 772 773 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 774 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 775 unsigned long address, pte_t *ptep) 776 { 777 return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 778 } 779 780 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 781 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 782 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 783 unsigned long address, pmd_t *pmdp) 784 { 785 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 786 } 787 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 788 789 /* 790 * ptep_set_wrprotect - mark read-only while trasferring potential hardware 791 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 792 */ 793 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 794 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 795 { 796 pte_t old_pte, pte; 797 798 pte = READ_ONCE(*ptep); 799 do { 800 old_pte = pte; 801 /* 802 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 803 * clear), set the PTE_DIRTY bit. 804 */ 805 if (pte_hw_dirty(pte)) 806 pte = pte_mkdirty(pte); 807 pte = pte_wrprotect(pte); 808 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 809 pte_val(old_pte), pte_val(pte)); 810 } while (pte_val(pte) != pte_val(old_pte)); 811 } 812 813 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 814 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 815 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 816 unsigned long address, pmd_t *pmdp) 817 { 818 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 819 } 820 821 #define pmdp_establish pmdp_establish 822 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 823 unsigned long address, pmd_t *pmdp, pmd_t pmd) 824 { 825 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 826 } 827 #endif 828 829 /* 830 * Encode and decode a swap entry: 831 * bits 0-1: present (must be zero) 832 * bits 2-7: swap type 833 * bits 8-57: swap offset 834 * bit 58: PTE_PROT_NONE (must be zero) 835 */ 836 #define __SWP_TYPE_SHIFT 2 837 #define __SWP_TYPE_BITS 6 838 #define __SWP_OFFSET_BITS 50 839 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 840 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 841 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 842 843 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 844 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 845 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 846 847 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 848 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 849 850 /* 851 * Ensure that there are not more swap files than can be encoded in the kernel 852 * PTEs. 853 */ 854 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 855 856 extern int kern_addr_valid(unsigned long addr); 857 858 /* 859 * On AArch64, the cache coherency is handled via the set_pte_at() function. 860 */ 861 static inline void update_mmu_cache(struct vm_area_struct *vma, 862 unsigned long addr, pte_t *ptep) 863 { 864 /* 865 * We don't do anything here, so there's a very small chance of 866 * us retaking a user fault which we just fixed up. The alternative 867 * is doing a dsb(ishst), but that penalises the fastpath. 868 */ 869 } 870 871 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 872 873 #ifdef CONFIG_ARM64_PA_BITS_52 874 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 875 #else 876 #define phys_to_ttbr(addr) (addr) 877 #endif 878 879 /* 880 * On arm64 without hardware Access Flag, copying from user will fail because 881 * the pte is old and cannot be marked young. So we always end up with zeroed 882 * page after fork() + CoW for pfn mappings. We don't always have a 883 * hardware-managed access flag on arm64. 884 */ 885 static inline bool arch_faults_on_old_pte(void) 886 { 887 WARN_ON(preemptible()); 888 889 return !cpu_has_hw_af(); 890 } 891 #define arch_faults_on_old_pte arch_faults_on_old_pte 892 893 #endif /* !__ASSEMBLY__ */ 894 895 #endif /* __ASM_PGTABLE_H */ 896