1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __ASM_PGTABLE_H 17 #define __ASM_PGTABLE_H 18 19 #include <asm/bug.h> 20 #include <asm/proc-fns.h> 21 22 #include <asm/memory.h> 23 #include <asm/pgtable-hwdef.h> 24 25 /* 26 * Software defined PTE bits definition. 27 */ 28 #define PTE_VALID (_AT(pteval_t, 1) << 0) 29 #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ 30 #define PTE_DIRTY (_AT(pteval_t, 1) << 55) 31 #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) 32 #define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */ 33 34 /* 35 * VMALLOC and SPARSEMEM_VMEMMAP ranges. 36 * 37 * VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array 38 * (rounded up to PUD_SIZE). 39 * VMALLOC_START: beginning of the kernel VA space 40 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space, 41 * fixed mappings and modules 42 */ 43 #define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE) 44 #define VMALLOC_START (UL(0xffffffffffffffff) << VA_BITS) 45 #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 46 47 #define vmemmap ((struct page *)(VMALLOC_END + SZ_64K)) 48 49 #define FIRST_USER_ADDRESS 0UL 50 51 #ifndef __ASSEMBLY__ 52 53 #include <linux/mmdebug.h> 54 55 extern void __pte_error(const char *file, int line, unsigned long val); 56 extern void __pmd_error(const char *file, int line, unsigned long val); 57 extern void __pud_error(const char *file, int line, unsigned long val); 58 extern void __pgd_error(const char *file, int line, unsigned long val); 59 60 #define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) 61 #define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) 62 63 #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE)) 64 #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC)) 65 #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL)) 66 67 #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) 68 #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) 69 #define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) 70 71 #define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) 72 73 #define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE) 74 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE) 75 76 #define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP) 77 #define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP) 78 79 #define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY) 80 #define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN) 81 82 #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_PXN | PTE_UXN) 83 #define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE) 84 #define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE) 85 #define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) 86 #define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) 87 #define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) 88 #define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) 89 90 #define __P000 PAGE_NONE 91 #define __P001 PAGE_READONLY 92 #define __P010 PAGE_COPY 93 #define __P011 PAGE_COPY 94 #define __P100 PAGE_READONLY_EXEC 95 #define __P101 PAGE_READONLY_EXEC 96 #define __P110 PAGE_COPY_EXEC 97 #define __P111 PAGE_COPY_EXEC 98 99 #define __S000 PAGE_NONE 100 #define __S001 PAGE_READONLY 101 #define __S010 PAGE_SHARED 102 #define __S011 PAGE_SHARED 103 #define __S100 PAGE_READONLY_EXEC 104 #define __S101 PAGE_READONLY_EXEC 105 #define __S110 PAGE_SHARED_EXEC 106 #define __S111 PAGE_SHARED_EXEC 107 108 /* 109 * ZERO_PAGE is a global shared page that is always zero: used 110 * for zero-mapped memory areas etc.. 111 */ 112 extern struct page *empty_zero_page; 113 #define ZERO_PAGE(vaddr) (empty_zero_page) 114 115 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 116 117 #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) 118 119 #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 120 121 #define pte_none(pte) (!pte_val(pte)) 122 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 123 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 124 125 /* Find an entry in the third-level page table. */ 126 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 127 128 #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr)) 129 130 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 131 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) 132 #define pte_unmap(pte) do { } while (0) 133 #define pte_unmap_nested(pte) do { } while (0) 134 135 /* 136 * The following only work if pte_present(). Undefined behaviour otherwise. 137 */ 138 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 139 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 140 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 141 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 142 #define pte_exec(pte) (!(pte_val(pte) & PTE_UXN)) 143 144 #ifdef CONFIG_ARM64_HW_AFDBM 145 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 146 #else 147 #define pte_hw_dirty(pte) (0) 148 #endif 149 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 150 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 151 152 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 153 #define pte_valid_user(pte) \ 154 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 155 #define pte_valid_not_user(pte) \ 156 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) 157 158 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 159 { 160 pte_val(pte) &= ~pgprot_val(prot); 161 return pte; 162 } 163 164 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 165 { 166 pte_val(pte) |= pgprot_val(prot); 167 return pte; 168 } 169 170 static inline pte_t pte_wrprotect(pte_t pte) 171 { 172 return clear_pte_bit(pte, __pgprot(PTE_WRITE)); 173 } 174 175 static inline pte_t pte_mkwrite(pte_t pte) 176 { 177 return set_pte_bit(pte, __pgprot(PTE_WRITE)); 178 } 179 180 static inline pte_t pte_mkclean(pte_t pte) 181 { 182 return clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 183 } 184 185 static inline pte_t pte_mkdirty(pte_t pte) 186 { 187 return set_pte_bit(pte, __pgprot(PTE_DIRTY)); 188 } 189 190 static inline pte_t pte_mkold(pte_t pte) 191 { 192 return clear_pte_bit(pte, __pgprot(PTE_AF)); 193 } 194 195 static inline pte_t pte_mkyoung(pte_t pte) 196 { 197 return set_pte_bit(pte, __pgprot(PTE_AF)); 198 } 199 200 static inline pte_t pte_mkspecial(pte_t pte) 201 { 202 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 203 } 204 205 static inline void set_pte(pte_t *ptep, pte_t pte) 206 { 207 *ptep = pte; 208 209 /* 210 * Only if the new pte is valid and kernel, otherwise TLB maintenance 211 * or update_mmu_cache() have the necessary barriers. 212 */ 213 if (pte_valid_not_user(pte)) { 214 dsb(ishst); 215 isb(); 216 } 217 } 218 219 struct mm_struct; 220 struct vm_area_struct; 221 222 extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); 223 224 /* 225 * PTE bits configuration in the presence of hardware Dirty Bit Management 226 * (PTE_WRITE == PTE_DBM): 227 * 228 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 229 * 0 0 | 1 0 0 230 * 0 1 | 1 1 0 231 * 1 0 | 1 0 1 232 * 1 1 | 0 1 x 233 * 234 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 235 * the page fault mechanism. Checking the dirty status of a pte becomes: 236 * 237 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 238 */ 239 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 240 pte_t *ptep, pte_t pte) 241 { 242 if (pte_valid_user(pte)) { 243 if (!pte_special(pte) && pte_exec(pte)) 244 __sync_icache_dcache(pte, addr); 245 if (pte_sw_dirty(pte) && pte_write(pte)) 246 pte_val(pte) &= ~PTE_RDONLY; 247 else 248 pte_val(pte) |= PTE_RDONLY; 249 } 250 251 /* 252 * If the existing pte is valid, check for potential race with 253 * hardware updates of the pte (ptep_set_access_flags safely changes 254 * valid ptes without going through an invalid entry). 255 */ 256 if (IS_ENABLED(CONFIG_DEBUG_VM) && IS_ENABLED(CONFIG_ARM64_HW_AFDBM) && 257 pte_valid(*ptep)) { 258 BUG_ON(!pte_young(pte)); 259 BUG_ON(pte_write(*ptep) && !pte_dirty(pte)); 260 } 261 262 set_pte(ptep, pte); 263 } 264 265 /* 266 * Huge pte definitions. 267 */ 268 #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) 269 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 270 271 /* 272 * Hugetlb definitions. 273 */ 274 #define HUGE_MAX_HSTATE 2 275 #define HPAGE_SHIFT PMD_SHIFT 276 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 277 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 278 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 279 280 #define __HAVE_ARCH_PTE_SPECIAL 281 282 static inline pte_t pud_pte(pud_t pud) 283 { 284 return __pte(pud_val(pud)); 285 } 286 287 static inline pmd_t pud_pmd(pud_t pud) 288 { 289 return __pmd(pud_val(pud)); 290 } 291 292 static inline pte_t pmd_pte(pmd_t pmd) 293 { 294 return __pte(pmd_val(pmd)); 295 } 296 297 static inline pmd_t pte_pmd(pte_t pte) 298 { 299 return __pmd(pte_val(pte)); 300 } 301 302 static inline pgprot_t mk_sect_prot(pgprot_t prot) 303 { 304 return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); 305 } 306 307 /* 308 * THP definitions. 309 */ 310 311 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 312 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 313 #define pmd_trans_splitting(pmd) pte_special(pmd_pte(pmd)) 314 #ifdef CONFIG_HAVE_RCU_TABLE_FREE 315 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH 316 struct vm_area_struct; 317 void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address, 318 pmd_t *pmdp); 319 #endif /* CONFIG_HAVE_RCU_TABLE_FREE */ 320 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 321 322 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 323 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 324 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 325 #define pmd_mksplitting(pmd) pte_pmd(pte_mkspecial(pmd_pte(pmd))) 326 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 327 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 328 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 329 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 330 #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK)) 331 332 #define __HAVE_ARCH_PMD_WRITE 333 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 334 335 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 336 337 #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 338 #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 339 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 340 341 #define pud_write(pud) pte_write(pud_pte(pud)) 342 #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 343 344 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 345 346 static inline int has_transparent_hugepage(void) 347 { 348 return 1; 349 } 350 351 #define __pgprot_modify(prot,mask,bits) \ 352 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 353 354 /* 355 * Mark the prot value as uncacheable and unbufferable. 356 */ 357 #define pgprot_noncached(prot) \ 358 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 359 #define pgprot_writecombine(prot) \ 360 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 361 #define pgprot_device(prot) \ 362 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 363 #define __HAVE_PHYS_MEM_ACCESS_PROT 364 struct file; 365 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 366 unsigned long size, pgprot_t vma_prot); 367 368 #define pmd_none(pmd) (!pmd_val(pmd)) 369 #define pmd_present(pmd) (pmd_val(pmd)) 370 371 #define pmd_bad(pmd) (!(pmd_val(pmd) & 2)) 372 373 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 374 PMD_TYPE_TABLE) 375 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 376 PMD_TYPE_SECT) 377 378 #ifdef CONFIG_ARM64_64K_PAGES 379 #define pud_sect(pud) (0) 380 #define pud_table(pud) (1) 381 #else 382 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 383 PUD_TYPE_SECT) 384 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 385 PUD_TYPE_TABLE) 386 #endif 387 388 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 389 { 390 *pmdp = pmd; 391 dsb(ishst); 392 isb(); 393 } 394 395 static inline void pmd_clear(pmd_t *pmdp) 396 { 397 set_pmd(pmdp, __pmd(0)); 398 } 399 400 static inline pte_t *pmd_page_vaddr(pmd_t pmd) 401 { 402 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK); 403 } 404 405 #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) 406 407 /* 408 * Conversion functions: convert a page and protection to a page entry, 409 * and a page entry and page directory to the page they refer to. 410 */ 411 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 412 413 #if CONFIG_PGTABLE_LEVELS > 2 414 415 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 416 417 #define pud_none(pud) (!pud_val(pud)) 418 #define pud_bad(pud) (!(pud_val(pud) & 2)) 419 #define pud_present(pud) (pud_val(pud)) 420 421 static inline void set_pud(pud_t *pudp, pud_t pud) 422 { 423 *pudp = pud; 424 dsb(ishst); 425 isb(); 426 } 427 428 static inline void pud_clear(pud_t *pudp) 429 { 430 set_pud(pudp, __pud(0)); 431 } 432 433 static inline pmd_t *pud_page_vaddr(pud_t pud) 434 { 435 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK); 436 } 437 438 /* Find an entry in the second-level page table. */ 439 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 440 441 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) 442 { 443 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr); 444 } 445 446 #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK)) 447 448 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 449 450 #if CONFIG_PGTABLE_LEVELS > 3 451 452 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 453 454 #define pgd_none(pgd) (!pgd_val(pgd)) 455 #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 456 #define pgd_present(pgd) (pgd_val(pgd)) 457 458 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 459 { 460 *pgdp = pgd; 461 dsb(ishst); 462 } 463 464 static inline void pgd_clear(pgd_t *pgdp) 465 { 466 set_pgd(pgdp, __pgd(0)); 467 } 468 469 static inline pud_t *pgd_page_vaddr(pgd_t pgd) 470 { 471 return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK); 472 } 473 474 /* Find an entry in the frst-level page table. */ 475 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 476 477 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr) 478 { 479 return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr); 480 } 481 482 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK)) 483 484 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 485 486 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 487 488 /* to find an entry in a page-table-directory */ 489 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 490 491 #define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr)) 492 493 /* to find an entry in a kernel page-table-directory */ 494 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 495 496 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 497 { 498 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 499 PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 500 /* preserve the hardware dirty information */ 501 if (pte_hw_dirty(pte)) 502 pte = pte_mkdirty(pte); 503 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 504 return pte; 505 } 506 507 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 508 { 509 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 510 } 511 512 #ifdef CONFIG_ARM64_HW_AFDBM 513 /* 514 * Atomic pte/pmd modifications. 515 */ 516 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 517 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 518 unsigned long address, 519 pte_t *ptep) 520 { 521 pteval_t pteval; 522 unsigned int tmp, res; 523 524 asm volatile("// ptep_test_and_clear_young\n" 525 " prfm pstl1strm, %2\n" 526 "1: ldxr %0, %2\n" 527 " ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n" 528 " and %0, %0, %4 // clear PTE_AF\n" 529 " stxr %w1, %0, %2\n" 530 " cbnz %w1, 1b\n" 531 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res) 532 : "L" (~PTE_AF), "I" (ilog2(PTE_AF))); 533 534 return res; 535 } 536 537 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 538 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 539 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 540 unsigned long address, 541 pmd_t *pmdp) 542 { 543 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 544 } 545 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 546 547 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 548 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 549 unsigned long address, pte_t *ptep) 550 { 551 pteval_t old_pteval; 552 unsigned int tmp; 553 554 asm volatile("// ptep_get_and_clear\n" 555 " prfm pstl1strm, %2\n" 556 "1: ldxr %0, %2\n" 557 " stxr %w1, xzr, %2\n" 558 " cbnz %w1, 1b\n" 559 : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))); 560 561 return __pte(old_pteval); 562 } 563 564 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 565 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 566 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 567 unsigned long address, pmd_t *pmdp) 568 { 569 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 570 } 571 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 572 573 /* 574 * ptep_set_wrprotect - mark read-only while trasferring potential hardware 575 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 576 */ 577 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 578 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 579 { 580 pteval_t pteval; 581 unsigned long tmp; 582 583 asm volatile("// ptep_set_wrprotect\n" 584 " prfm pstl1strm, %2\n" 585 "1: ldxr %0, %2\n" 586 " tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n" 587 " csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n" 588 " orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n" 589 " and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n" 590 " stxr %w1, %0, %2\n" 591 " cbnz %w1, 1b\n" 592 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)) 593 : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE) 594 : "cc"); 595 } 596 597 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 598 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 599 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 600 unsigned long address, pmd_t *pmdp) 601 { 602 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 603 } 604 #endif 605 #endif /* CONFIG_ARM64_HW_AFDBM */ 606 607 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 608 extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 609 610 /* 611 * Encode and decode a swap entry: 612 * bits 0-1: present (must be zero) 613 * bits 2-7: swap type 614 * bits 8-57: swap offset 615 */ 616 #define __SWP_TYPE_SHIFT 2 617 #define __SWP_TYPE_BITS 6 618 #define __SWP_OFFSET_BITS 50 619 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 620 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 621 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 622 623 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 624 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 625 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 626 627 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 628 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 629 630 /* 631 * Ensure that there are not more swap files than can be encoded in the kernel 632 * PTEs. 633 */ 634 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 635 636 extern int kern_addr_valid(unsigned long addr); 637 638 #include <asm-generic/pgtable.h> 639 640 #define pgtable_cache_init() do { } while (0) 641 642 /* 643 * On AArch64, the cache coherency is handled via the set_pte_at() function. 644 */ 645 static inline void update_mmu_cache(struct vm_area_struct *vma, 646 unsigned long addr, pte_t *ptep) 647 { 648 /* 649 * set_pte() does not have a DSB for user mappings, so make sure that 650 * the page table write is visible. 651 */ 652 dsb(ishst); 653 } 654 655 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 656 657 #endif /* !__ASSEMBLY__ */ 658 659 #endif /* __ASM_PGTABLE_H */ 660