1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __ASM_PGTABLE_H 17 #define __ASM_PGTABLE_H 18 19 #include <asm/bug.h> 20 #include <asm/proc-fns.h> 21 22 #include <asm/memory.h> 23 #include <asm/pgtable-hwdef.h> 24 25 /* 26 * Software defined PTE bits definition. 27 */ 28 #define PTE_VALID (_AT(pteval_t, 1) << 0) 29 #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ 30 #define PTE_DIRTY (_AT(pteval_t, 1) << 55) 31 #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) 32 #define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */ 33 34 /* 35 * VMALLOC and SPARSEMEM_VMEMMAP ranges. 36 * 37 * VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array 38 * (rounded up to PUD_SIZE). 39 * VMALLOC_START: beginning of the kernel VA space 40 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space, 41 * fixed mappings and modules 42 */ 43 #define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE) 44 45 #ifndef CONFIG_KASAN 46 #define VMALLOC_START (VA_START) 47 #else 48 #include <asm/kasan.h> 49 #define VMALLOC_START (KASAN_SHADOW_END + SZ_64K) 50 #endif 51 52 #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 53 54 #define vmemmap ((struct page *)(VMALLOC_END + SZ_64K)) 55 56 #define FIRST_USER_ADDRESS 0UL 57 58 #ifndef __ASSEMBLY__ 59 60 #include <linux/mmdebug.h> 61 62 extern void __pte_error(const char *file, int line, unsigned long val); 63 extern void __pmd_error(const char *file, int line, unsigned long val); 64 extern void __pud_error(const char *file, int line, unsigned long val); 65 extern void __pgd_error(const char *file, int line, unsigned long val); 66 67 #define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) 68 #define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) 69 70 #define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE)) 71 #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE)) 72 #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC)) 73 #define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT)) 74 #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL)) 75 76 #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) 77 #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) 78 #define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) 79 80 #define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) 81 82 #define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE) 83 #define PAGE_KERNEL_RO __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_RDONLY) 84 #define PAGE_KERNEL_ROX __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_RDONLY) 85 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE) 86 #define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_CONT) 87 88 #define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP) 89 #define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP) 90 91 #define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY) 92 #define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN) 93 94 #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_PXN | PTE_UXN) 95 #define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE) 96 #define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE) 97 #define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) 98 #define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) 99 #define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) 100 #define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) 101 102 #define __P000 PAGE_NONE 103 #define __P001 PAGE_READONLY 104 #define __P010 PAGE_COPY 105 #define __P011 PAGE_COPY 106 #define __P100 PAGE_READONLY_EXEC 107 #define __P101 PAGE_READONLY_EXEC 108 #define __P110 PAGE_COPY_EXEC 109 #define __P111 PAGE_COPY_EXEC 110 111 #define __S000 PAGE_NONE 112 #define __S001 PAGE_READONLY 113 #define __S010 PAGE_SHARED 114 #define __S011 PAGE_SHARED 115 #define __S100 PAGE_READONLY_EXEC 116 #define __S101 PAGE_READONLY_EXEC 117 #define __S110 PAGE_SHARED_EXEC 118 #define __S111 PAGE_SHARED_EXEC 119 120 /* 121 * ZERO_PAGE is a global shared page that is always zero: used 122 * for zero-mapped memory areas etc.. 123 */ 124 extern struct page *empty_zero_page; 125 #define ZERO_PAGE(vaddr) (empty_zero_page) 126 127 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 128 129 #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) 130 131 #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 132 133 #define pte_none(pte) (!pte_val(pte)) 134 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 135 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 136 137 /* Find an entry in the third-level page table. */ 138 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 139 140 #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr)) 141 142 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 143 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) 144 #define pte_unmap(pte) do { } while (0) 145 #define pte_unmap_nested(pte) do { } while (0) 146 147 /* 148 * The following only work if pte_present(). Undefined behaviour otherwise. 149 */ 150 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 151 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 152 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 153 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 154 #define pte_exec(pte) (!(pte_val(pte) & PTE_UXN)) 155 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 156 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 157 158 #ifdef CONFIG_ARM64_HW_AFDBM 159 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 160 #else 161 #define pte_hw_dirty(pte) (0) 162 #endif 163 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 164 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 165 166 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 167 #define pte_valid_not_user(pte) \ 168 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) 169 #define pte_valid_young(pte) \ 170 ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 171 172 /* 173 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 174 * so that we don't erroneously return false for pages that have been 175 * remapped as PROT_NONE but are yet to be flushed from the TLB. 176 */ 177 #define pte_accessible(mm, pte) \ 178 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 179 180 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 181 { 182 pte_val(pte) &= ~pgprot_val(prot); 183 return pte; 184 } 185 186 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 187 { 188 pte_val(pte) |= pgprot_val(prot); 189 return pte; 190 } 191 192 static inline pte_t pte_wrprotect(pte_t pte) 193 { 194 return clear_pte_bit(pte, __pgprot(PTE_WRITE)); 195 } 196 197 static inline pte_t pte_mkwrite(pte_t pte) 198 { 199 return set_pte_bit(pte, __pgprot(PTE_WRITE)); 200 } 201 202 static inline pte_t pte_mkclean(pte_t pte) 203 { 204 return clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 205 } 206 207 static inline pte_t pte_mkdirty(pte_t pte) 208 { 209 return set_pte_bit(pte, __pgprot(PTE_DIRTY)); 210 } 211 212 static inline pte_t pte_mkold(pte_t pte) 213 { 214 return clear_pte_bit(pte, __pgprot(PTE_AF)); 215 } 216 217 static inline pte_t pte_mkyoung(pte_t pte) 218 { 219 return set_pte_bit(pte, __pgprot(PTE_AF)); 220 } 221 222 static inline pte_t pte_mkspecial(pte_t pte) 223 { 224 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 225 } 226 227 static inline pte_t pte_mkcont(pte_t pte) 228 { 229 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 230 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 231 } 232 233 static inline pte_t pte_mknoncont(pte_t pte) 234 { 235 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 236 } 237 238 static inline pmd_t pmd_mkcont(pmd_t pmd) 239 { 240 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 241 } 242 243 static inline void set_pte(pte_t *ptep, pte_t pte) 244 { 245 *ptep = pte; 246 247 /* 248 * Only if the new pte is valid and kernel, otherwise TLB maintenance 249 * or update_mmu_cache() have the necessary barriers. 250 */ 251 if (pte_valid_not_user(pte)) { 252 dsb(ishst); 253 isb(); 254 } 255 } 256 257 struct mm_struct; 258 struct vm_area_struct; 259 260 extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); 261 262 /* 263 * PTE bits configuration in the presence of hardware Dirty Bit Management 264 * (PTE_WRITE == PTE_DBM): 265 * 266 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 267 * 0 0 | 1 0 0 268 * 0 1 | 1 1 0 269 * 1 0 | 1 0 1 270 * 1 1 | 0 1 x 271 * 272 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 273 * the page fault mechanism. Checking the dirty status of a pte becomes: 274 * 275 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 276 */ 277 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 278 pte_t *ptep, pte_t pte) 279 { 280 if (pte_valid(pte)) { 281 if (pte_sw_dirty(pte) && pte_write(pte)) 282 pte_val(pte) &= ~PTE_RDONLY; 283 else 284 pte_val(pte) |= PTE_RDONLY; 285 if (pte_user(pte) && pte_exec(pte) && !pte_special(pte)) 286 __sync_icache_dcache(pte, addr); 287 } 288 289 /* 290 * If the existing pte is valid, check for potential race with 291 * hardware updates of the pte (ptep_set_access_flags safely changes 292 * valid ptes without going through an invalid entry). 293 */ 294 if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) && 295 pte_valid(*ptep) && pte_valid(pte)) { 296 VM_WARN_ONCE(!pte_young(pte), 297 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 298 __func__, pte_val(*ptep), pte_val(pte)); 299 VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte), 300 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 301 __func__, pte_val(*ptep), pte_val(pte)); 302 } 303 304 set_pte(ptep, pte); 305 } 306 307 /* 308 * Huge pte definitions. 309 */ 310 #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) 311 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 312 313 /* 314 * Hugetlb definitions. 315 */ 316 #define HUGE_MAX_HSTATE 4 317 #define HPAGE_SHIFT PMD_SHIFT 318 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 319 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 320 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 321 322 #define __HAVE_ARCH_PTE_SPECIAL 323 324 static inline pte_t pud_pte(pud_t pud) 325 { 326 return __pte(pud_val(pud)); 327 } 328 329 static inline pmd_t pud_pmd(pud_t pud) 330 { 331 return __pmd(pud_val(pud)); 332 } 333 334 static inline pte_t pmd_pte(pmd_t pmd) 335 { 336 return __pte(pmd_val(pmd)); 337 } 338 339 static inline pmd_t pte_pmd(pte_t pte) 340 { 341 return __pmd(pte_val(pte)); 342 } 343 344 static inline pgprot_t mk_sect_prot(pgprot_t prot) 345 { 346 return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); 347 } 348 349 /* 350 * THP definitions. 351 */ 352 353 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 354 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 355 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 356 357 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 358 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 359 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 360 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 361 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 362 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 363 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 364 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 365 #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK)) 366 367 #define __HAVE_ARCH_PMD_WRITE 368 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 369 370 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 371 372 #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 373 #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 374 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 375 376 #define pud_write(pud) pte_write(pud_pte(pud)) 377 #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 378 379 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 380 381 static inline int has_transparent_hugepage(void) 382 { 383 return 1; 384 } 385 386 #define __pgprot_modify(prot,mask,bits) \ 387 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 388 389 /* 390 * Mark the prot value as uncacheable and unbufferable. 391 */ 392 #define pgprot_noncached(prot) \ 393 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 394 #define pgprot_writecombine(prot) \ 395 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 396 #define pgprot_device(prot) \ 397 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 398 #define __HAVE_PHYS_MEM_ACCESS_PROT 399 struct file; 400 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 401 unsigned long size, pgprot_t vma_prot); 402 403 #define pmd_none(pmd) (!pmd_val(pmd)) 404 #define pmd_present(pmd) (pmd_val(pmd)) 405 406 #define pmd_bad(pmd) (!(pmd_val(pmd) & 2)) 407 408 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 409 PMD_TYPE_TABLE) 410 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 411 PMD_TYPE_SECT) 412 413 #ifdef CONFIG_ARM64_64K_PAGES 414 #define pud_sect(pud) (0) 415 #define pud_table(pud) (1) 416 #else 417 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 418 PUD_TYPE_SECT) 419 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 420 PUD_TYPE_TABLE) 421 #endif 422 423 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 424 { 425 *pmdp = pmd; 426 dsb(ishst); 427 isb(); 428 } 429 430 static inline void pmd_clear(pmd_t *pmdp) 431 { 432 set_pmd(pmdp, __pmd(0)); 433 } 434 435 static inline pte_t *pmd_page_vaddr(pmd_t pmd) 436 { 437 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK); 438 } 439 440 #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) 441 442 /* 443 * Conversion functions: convert a page and protection to a page entry, 444 * and a page entry and page directory to the page they refer to. 445 */ 446 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 447 448 #if CONFIG_PGTABLE_LEVELS > 2 449 450 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 451 452 #define pud_none(pud) (!pud_val(pud)) 453 #define pud_bad(pud) (!(pud_val(pud) & 2)) 454 #define pud_present(pud) (pud_val(pud)) 455 456 static inline void set_pud(pud_t *pudp, pud_t pud) 457 { 458 *pudp = pud; 459 dsb(ishst); 460 isb(); 461 } 462 463 static inline void pud_clear(pud_t *pudp) 464 { 465 set_pud(pudp, __pud(0)); 466 } 467 468 static inline pmd_t *pud_page_vaddr(pud_t pud) 469 { 470 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK); 471 } 472 473 /* Find an entry in the second-level page table. */ 474 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 475 476 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) 477 { 478 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr); 479 } 480 481 #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK)) 482 483 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 484 485 #if CONFIG_PGTABLE_LEVELS > 3 486 487 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 488 489 #define pgd_none(pgd) (!pgd_val(pgd)) 490 #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 491 #define pgd_present(pgd) (pgd_val(pgd)) 492 493 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 494 { 495 *pgdp = pgd; 496 dsb(ishst); 497 } 498 499 static inline void pgd_clear(pgd_t *pgdp) 500 { 501 set_pgd(pgdp, __pgd(0)); 502 } 503 504 static inline pud_t *pgd_page_vaddr(pgd_t pgd) 505 { 506 return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK); 507 } 508 509 /* Find an entry in the frst-level page table. */ 510 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 511 512 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr) 513 { 514 return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr); 515 } 516 517 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK)) 518 519 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 520 521 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 522 523 /* to find an entry in a page-table-directory */ 524 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 525 526 #define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr)) 527 528 /* to find an entry in a kernel page-table-directory */ 529 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 530 531 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 532 { 533 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 534 PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 535 /* preserve the hardware dirty information */ 536 if (pte_hw_dirty(pte)) 537 pte = pte_mkdirty(pte); 538 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 539 return pte; 540 } 541 542 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 543 { 544 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 545 } 546 547 #ifdef CONFIG_ARM64_HW_AFDBM 548 /* 549 * Atomic pte/pmd modifications. 550 */ 551 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 552 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 553 unsigned long address, 554 pte_t *ptep) 555 { 556 pteval_t pteval; 557 unsigned int tmp, res; 558 559 asm volatile("// ptep_test_and_clear_young\n" 560 " prfm pstl1strm, %2\n" 561 "1: ldxr %0, %2\n" 562 " ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n" 563 " and %0, %0, %4 // clear PTE_AF\n" 564 " stxr %w1, %0, %2\n" 565 " cbnz %w1, 1b\n" 566 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res) 567 : "L" (~PTE_AF), "I" (ilog2(PTE_AF))); 568 569 return res; 570 } 571 572 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 573 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 574 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 575 unsigned long address, 576 pmd_t *pmdp) 577 { 578 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 579 } 580 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 581 582 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 583 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 584 unsigned long address, pte_t *ptep) 585 { 586 pteval_t old_pteval; 587 unsigned int tmp; 588 589 asm volatile("// ptep_get_and_clear\n" 590 " prfm pstl1strm, %2\n" 591 "1: ldxr %0, %2\n" 592 " stxr %w1, xzr, %2\n" 593 " cbnz %w1, 1b\n" 594 : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))); 595 596 return __pte(old_pteval); 597 } 598 599 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 600 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 601 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 602 unsigned long address, pmd_t *pmdp) 603 { 604 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 605 } 606 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 607 608 /* 609 * ptep_set_wrprotect - mark read-only while trasferring potential hardware 610 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 611 */ 612 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 613 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 614 { 615 pteval_t pteval; 616 unsigned long tmp; 617 618 asm volatile("// ptep_set_wrprotect\n" 619 " prfm pstl1strm, %2\n" 620 "1: ldxr %0, %2\n" 621 " tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n" 622 " csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n" 623 " orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n" 624 " and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n" 625 " stxr %w1, %0, %2\n" 626 " cbnz %w1, 1b\n" 627 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)) 628 : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE) 629 : "cc"); 630 } 631 632 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 633 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 634 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 635 unsigned long address, pmd_t *pmdp) 636 { 637 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 638 } 639 #endif 640 #endif /* CONFIG_ARM64_HW_AFDBM */ 641 642 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 643 extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 644 645 /* 646 * Encode and decode a swap entry: 647 * bits 0-1: present (must be zero) 648 * bits 2-7: swap type 649 * bits 8-57: swap offset 650 */ 651 #define __SWP_TYPE_SHIFT 2 652 #define __SWP_TYPE_BITS 6 653 #define __SWP_OFFSET_BITS 50 654 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 655 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 656 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 657 658 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 659 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 660 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 661 662 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 663 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 664 665 /* 666 * Ensure that there are not more swap files than can be encoded in the kernel 667 * PTEs. 668 */ 669 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 670 671 extern int kern_addr_valid(unsigned long addr); 672 673 #include <asm-generic/pgtable.h> 674 675 void pgd_cache_init(void); 676 #define pgtable_cache_init pgd_cache_init 677 678 /* 679 * On AArch64, the cache coherency is handled via the set_pte_at() function. 680 */ 681 static inline void update_mmu_cache(struct vm_area_struct *vma, 682 unsigned long addr, pte_t *ptep) 683 { 684 /* 685 * We don't do anything here, so there's a very small chance of 686 * us retaking a user fault which we just fixed up. The alternative 687 * is doing a dsb(ishst), but that penalises the fastpath. 688 */ 689 } 690 691 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 692 693 #define kc_vaddr_to_offset(v) ((v) & ~VA_START) 694 #define kc_offset_to_vaddr(o) ((o) | VA_START) 695 696 #endif /* !__ASSEMBLY__ */ 697 698 #endif /* __ASM_PGTABLE_H */ 699