1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space 22 * and fixed mappings 23 */ 24 #define VMALLOC_START (MODULES_END) 25 #define VMALLOC_END (VMEMMAP_START - SZ_256M) 26 27 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 28 29 #define FIRST_USER_ADDRESS 0UL 30 31 #ifndef __ASSEMBLY__ 32 33 #include <asm/cmpxchg.h> 34 #include <asm/fixmap.h> 35 #include <linux/mmdebug.h> 36 #include <linux/mm_types.h> 37 #include <linux/sched.h> 38 39 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 40 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 41 42 /* Set stride and tlb_level in flush_*_tlb_range */ 43 #define flush_pmd_tlb_range(vma, addr, end) \ 44 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 45 #define flush_pud_tlb_range(vma, addr, end) \ 46 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 47 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 48 49 /* 50 * Outside of a few very special situations (e.g. hibernation), we always 51 * use broadcast TLB invalidation instructions, therefore a spurious page 52 * fault on one CPU which has been handled concurrently by another CPU 53 * does not need to perform additional invalidation. 54 */ 55 #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0) 56 57 /* 58 * ZERO_PAGE is a global shared page that is always zero: used 59 * for zero-mapped memory areas etc.. 60 */ 61 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 62 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 63 64 #define pte_ERROR(e) \ 65 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 66 67 /* 68 * Macros to convert between a physical address and its placement in a 69 * page table entry, taking care of 52-bit addresses. 70 */ 71 #ifdef CONFIG_ARM64_PA_BITS_52 72 #define __pte_to_phys(pte) \ 73 ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 74 #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 75 #else 76 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 77 #define __phys_to_pte_val(phys) (phys) 78 #endif 79 80 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 81 #define pfn_pte(pfn,prot) \ 82 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 83 84 #define pte_none(pte) (!pte_val(pte)) 85 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 86 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 87 88 /* 89 * The following only work if pte_present(). Undefined behaviour otherwise. 90 */ 91 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 92 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 93 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 94 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 95 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 96 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 97 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 98 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 99 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 100 101 #define pte_cont_addr_end(addr, end) \ 102 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 103 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 104 }) 105 106 #define pmd_cont_addr_end(addr, end) \ 107 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 108 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 109 }) 110 111 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 112 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 113 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 114 115 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 116 /* 117 * Execute-only user mappings do not have the PTE_USER bit set. All valid 118 * kernel mappings have the PTE_UXN bit set. 119 */ 120 #define pte_valid_not_user(pte) \ 121 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 122 /* 123 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 124 * so that we don't erroneously return false for pages that have been 125 * remapped as PROT_NONE but are yet to be flushed from the TLB. 126 * Note that we can't make any assumptions based on the state of the access 127 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the 128 * TLB. 129 */ 130 #define pte_accessible(mm, pte) \ 131 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 132 133 /* 134 * p??_access_permitted() is true for valid user mappings (PTE_USER 135 * bit set, subject to the write permission check). For execute-only 136 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 137 * not set) must return false. PROT_NONE mappings do not have the 138 * PTE_VALID bit set. 139 */ 140 #define pte_access_permitted(pte, write) \ 141 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 142 #define pmd_access_permitted(pmd, write) \ 143 (pte_access_permitted(pmd_pte(pmd), (write))) 144 #define pud_access_permitted(pud, write) \ 145 (pte_access_permitted(pud_pte(pud), (write))) 146 147 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 148 { 149 pte_val(pte) &= ~pgprot_val(prot); 150 return pte; 151 } 152 153 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 154 { 155 pte_val(pte) |= pgprot_val(prot); 156 return pte; 157 } 158 159 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 160 { 161 pmd_val(pmd) &= ~pgprot_val(prot); 162 return pmd; 163 } 164 165 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 166 { 167 pmd_val(pmd) |= pgprot_val(prot); 168 return pmd; 169 } 170 171 static inline pte_t pte_mkwrite(pte_t pte) 172 { 173 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 174 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 175 return pte; 176 } 177 178 static inline pte_t pte_mkclean(pte_t pte) 179 { 180 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 181 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 182 183 return pte; 184 } 185 186 static inline pte_t pte_mkdirty(pte_t pte) 187 { 188 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 189 190 if (pte_write(pte)) 191 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 192 193 return pte; 194 } 195 196 static inline pte_t pte_wrprotect(pte_t pte) 197 { 198 /* 199 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 200 * clear), set the PTE_DIRTY bit. 201 */ 202 if (pte_hw_dirty(pte)) 203 pte = pte_mkdirty(pte); 204 205 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 206 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 207 return pte; 208 } 209 210 static inline pte_t pte_mkold(pte_t pte) 211 { 212 return clear_pte_bit(pte, __pgprot(PTE_AF)); 213 } 214 215 static inline pte_t pte_mkyoung(pte_t pte) 216 { 217 return set_pte_bit(pte, __pgprot(PTE_AF)); 218 } 219 220 static inline pte_t pte_mkspecial(pte_t pte) 221 { 222 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 223 } 224 225 static inline pte_t pte_mkcont(pte_t pte) 226 { 227 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 228 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 229 } 230 231 static inline pte_t pte_mknoncont(pte_t pte) 232 { 233 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 234 } 235 236 static inline pte_t pte_mkpresent(pte_t pte) 237 { 238 return set_pte_bit(pte, __pgprot(PTE_VALID)); 239 } 240 241 static inline pmd_t pmd_mkcont(pmd_t pmd) 242 { 243 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 244 } 245 246 static inline pte_t pte_mkdevmap(pte_t pte) 247 { 248 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 249 } 250 251 static inline void set_pte(pte_t *ptep, pte_t pte) 252 { 253 WRITE_ONCE(*ptep, pte); 254 255 /* 256 * Only if the new pte is valid and kernel, otherwise TLB maintenance 257 * or update_mmu_cache() have the necessary barriers. 258 */ 259 if (pte_valid_not_user(pte)) { 260 dsb(ishst); 261 isb(); 262 } 263 } 264 265 extern void __sync_icache_dcache(pte_t pteval); 266 267 /* 268 * PTE bits configuration in the presence of hardware Dirty Bit Management 269 * (PTE_WRITE == PTE_DBM): 270 * 271 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 272 * 0 0 | 1 0 0 273 * 0 1 | 1 1 0 274 * 1 0 | 1 0 1 275 * 1 1 | 0 1 x 276 * 277 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 278 * the page fault mechanism. Checking the dirty status of a pte becomes: 279 * 280 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 281 */ 282 283 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, 284 pte_t pte) 285 { 286 pte_t old_pte; 287 288 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 289 return; 290 291 old_pte = READ_ONCE(*ptep); 292 293 if (!pte_valid(old_pte) || !pte_valid(pte)) 294 return; 295 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 296 return; 297 298 /* 299 * Check for potential race with hardware updates of the pte 300 * (ptep_set_access_flags safely changes valid ptes without going 301 * through an invalid entry). 302 */ 303 VM_WARN_ONCE(!pte_young(pte), 304 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 305 __func__, pte_val(old_pte), pte_val(pte)); 306 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 307 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 308 __func__, pte_val(old_pte), pte_val(pte)); 309 } 310 311 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 312 pte_t *ptep, pte_t pte) 313 { 314 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 315 __sync_icache_dcache(pte); 316 317 /* 318 * If the PTE would provide user space access to the tags associated 319 * with it then ensure that the MTE tags are synchronised. Although 320 * pte_access_permitted() returns false for exec only mappings, they 321 * don't expose tags (instruction fetches don't check tags). 322 */ 323 if (system_supports_mte() && pte_access_permitted(pte, false) && 324 !pte_special(pte)) { 325 pte_t old_pte = READ_ONCE(*ptep); 326 /* 327 * We only need to synchronise if the new PTE has tags enabled 328 * or if swapping in (in which case another mapping may have 329 * set tags in the past even if this PTE isn't tagged). 330 * (!pte_none() && !pte_present()) is an open coded version of 331 * is_swap_pte() 332 */ 333 if (pte_tagged(pte) || (!pte_none(old_pte) && !pte_present(old_pte))) 334 mte_sync_tags(old_pte, pte); 335 } 336 337 __check_racy_pte_update(mm, ptep, pte); 338 339 set_pte(ptep, pte); 340 } 341 342 /* 343 * Huge pte definitions. 344 */ 345 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 346 347 /* 348 * Hugetlb definitions. 349 */ 350 #define HUGE_MAX_HSTATE 4 351 #define HPAGE_SHIFT PMD_SHIFT 352 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 353 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 354 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 355 356 static inline pte_t pgd_pte(pgd_t pgd) 357 { 358 return __pte(pgd_val(pgd)); 359 } 360 361 static inline pte_t p4d_pte(p4d_t p4d) 362 { 363 return __pte(p4d_val(p4d)); 364 } 365 366 static inline pte_t pud_pte(pud_t pud) 367 { 368 return __pte(pud_val(pud)); 369 } 370 371 static inline pud_t pte_pud(pte_t pte) 372 { 373 return __pud(pte_val(pte)); 374 } 375 376 static inline pmd_t pud_pmd(pud_t pud) 377 { 378 return __pmd(pud_val(pud)); 379 } 380 381 static inline pte_t pmd_pte(pmd_t pmd) 382 { 383 return __pte(pmd_val(pmd)); 384 } 385 386 static inline pmd_t pte_pmd(pte_t pte) 387 { 388 return __pmd(pte_val(pte)); 389 } 390 391 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 392 { 393 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 394 } 395 396 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 397 { 398 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 399 } 400 401 #ifdef CONFIG_NUMA_BALANCING 402 /* 403 * See the comment in include/linux/pgtable.h 404 */ 405 static inline int pte_protnone(pte_t pte) 406 { 407 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 408 } 409 410 static inline int pmd_protnone(pmd_t pmd) 411 { 412 return pte_protnone(pmd_pte(pmd)); 413 } 414 #endif 415 416 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) 417 418 static inline int pmd_present(pmd_t pmd) 419 { 420 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); 421 } 422 423 /* 424 * THP definitions. 425 */ 426 427 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 428 static inline int pmd_trans_huge(pmd_t pmd) 429 { 430 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 431 } 432 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 433 434 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 435 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 436 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 437 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 438 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 439 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 440 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 441 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 442 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 443 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 444 445 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 446 { 447 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); 448 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); 449 450 return pmd; 451 } 452 453 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 454 455 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 456 457 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 458 459 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 460 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 461 #endif 462 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 463 { 464 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 465 } 466 467 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 468 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 469 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 470 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 471 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 472 473 #define pud_young(pud) pte_young(pud_pte(pud)) 474 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 475 #define pud_write(pud) pte_write(pud_pte(pud)) 476 477 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 478 479 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 480 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 481 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 482 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 483 484 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 485 #define set_pud_at(mm, addr, pudp, pud) set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)) 486 487 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 488 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 489 490 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 491 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 492 493 #define __pgprot_modify(prot,mask,bits) \ 494 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 495 496 #define pgprot_nx(prot) \ 497 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 498 499 /* 500 * Mark the prot value as uncacheable and unbufferable. 501 */ 502 #define pgprot_noncached(prot) \ 503 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 504 #define pgprot_writecombine(prot) \ 505 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 506 #define pgprot_device(prot) \ 507 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 508 #define pgprot_tagged(prot) \ 509 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 510 #define pgprot_mhp pgprot_tagged 511 /* 512 * DMA allocations for non-coherent devices use what the Arm architecture calls 513 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 514 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 515 * is intended for MMIO and thus forbids speculation, preserves access size, 516 * requires strict alignment and can also force write responses to come from the 517 * endpoint. 518 */ 519 #define pgprot_dmacoherent(prot) \ 520 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 521 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 522 523 #define __HAVE_PHYS_MEM_ACCESS_PROT 524 struct file; 525 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 526 unsigned long size, pgprot_t vma_prot); 527 528 #define pmd_none(pmd) (!pmd_val(pmd)) 529 530 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 531 PMD_TYPE_TABLE) 532 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 533 PMD_TYPE_SECT) 534 #define pmd_leaf(pmd) pmd_sect(pmd) 535 #define pmd_bad(pmd) (!pmd_table(pmd)) 536 537 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 538 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 539 540 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 541 static inline bool pud_sect(pud_t pud) { return false; } 542 static inline bool pud_table(pud_t pud) { return true; } 543 #else 544 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 545 PUD_TYPE_SECT) 546 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 547 PUD_TYPE_TABLE) 548 #endif 549 550 extern pgd_t init_pg_dir[PTRS_PER_PGD]; 551 extern pgd_t init_pg_end[]; 552 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 553 extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 554 extern pgd_t idmap_pg_end[]; 555 extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 556 extern pgd_t reserved_pg_dir[PTRS_PER_PGD]; 557 558 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 559 560 static inline bool in_swapper_pgdir(void *addr) 561 { 562 return ((unsigned long)addr & PAGE_MASK) == 563 ((unsigned long)swapper_pg_dir & PAGE_MASK); 564 } 565 566 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 567 { 568 #ifdef __PAGETABLE_PMD_FOLDED 569 if (in_swapper_pgdir(pmdp)) { 570 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 571 return; 572 } 573 #endif /* __PAGETABLE_PMD_FOLDED */ 574 575 WRITE_ONCE(*pmdp, pmd); 576 577 if (pmd_valid(pmd)) { 578 dsb(ishst); 579 isb(); 580 } 581 } 582 583 static inline void pmd_clear(pmd_t *pmdp) 584 { 585 set_pmd(pmdp, __pmd(0)); 586 } 587 588 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 589 { 590 return __pmd_to_phys(pmd); 591 } 592 593 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 594 { 595 return (unsigned long)__va(pmd_page_paddr(pmd)); 596 } 597 598 /* Find an entry in the third-level page table. */ 599 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 600 601 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 602 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 603 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 604 605 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 606 607 /* use ONLY for statically allocated translation tables */ 608 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 609 610 /* 611 * Conversion functions: convert a page and protection to a page entry, 612 * and a page entry and page directory to the page they refer to. 613 */ 614 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 615 616 #if CONFIG_PGTABLE_LEVELS > 2 617 618 #define pmd_ERROR(e) \ 619 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 620 621 #define pud_none(pud) (!pud_val(pud)) 622 #define pud_bad(pud) (!pud_table(pud)) 623 #define pud_present(pud) pte_present(pud_pte(pud)) 624 #define pud_leaf(pud) pud_sect(pud) 625 #define pud_valid(pud) pte_valid(pud_pte(pud)) 626 627 static inline void set_pud(pud_t *pudp, pud_t pud) 628 { 629 #ifdef __PAGETABLE_PUD_FOLDED 630 if (in_swapper_pgdir(pudp)) { 631 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 632 return; 633 } 634 #endif /* __PAGETABLE_PUD_FOLDED */ 635 636 WRITE_ONCE(*pudp, pud); 637 638 if (pud_valid(pud)) { 639 dsb(ishst); 640 isb(); 641 } 642 } 643 644 static inline void pud_clear(pud_t *pudp) 645 { 646 set_pud(pudp, __pud(0)); 647 } 648 649 static inline phys_addr_t pud_page_paddr(pud_t pud) 650 { 651 return __pud_to_phys(pud); 652 } 653 654 static inline unsigned long pud_page_vaddr(pud_t pud) 655 { 656 return (unsigned long)__va(pud_page_paddr(pud)); 657 } 658 659 /* Find an entry in the second-level page table. */ 660 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 661 662 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 663 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 664 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 665 666 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 667 668 /* use ONLY for statically allocated translation tables */ 669 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 670 671 #else 672 673 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 674 675 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 676 #define pmd_set_fixmap(addr) NULL 677 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 678 #define pmd_clear_fixmap() 679 680 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 681 682 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 683 684 #if CONFIG_PGTABLE_LEVELS > 3 685 686 #define pud_ERROR(e) \ 687 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 688 689 #define p4d_none(p4d) (!p4d_val(p4d)) 690 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2)) 691 #define p4d_present(p4d) (p4d_val(p4d)) 692 693 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 694 { 695 if (in_swapper_pgdir(p4dp)) { 696 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 697 return; 698 } 699 700 WRITE_ONCE(*p4dp, p4d); 701 dsb(ishst); 702 isb(); 703 } 704 705 static inline void p4d_clear(p4d_t *p4dp) 706 { 707 set_p4d(p4dp, __p4d(0)); 708 } 709 710 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 711 { 712 return __p4d_to_phys(p4d); 713 } 714 715 static inline unsigned long p4d_page_vaddr(p4d_t p4d) 716 { 717 return (unsigned long)__va(p4d_page_paddr(p4d)); 718 } 719 720 /* Find an entry in the frst-level page table. */ 721 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 722 723 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 724 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr)) 725 #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 726 727 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 728 729 /* use ONLY for statically allocated translation tables */ 730 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 731 732 #else 733 734 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 735 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 736 737 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 738 #define pud_set_fixmap(addr) NULL 739 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 740 #define pud_clear_fixmap() 741 742 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 743 744 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 745 746 #define pgd_ERROR(e) \ 747 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 748 749 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 750 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 751 752 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 753 { 754 /* 755 * Normal and Normal-Tagged are two different memory types and indices 756 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 757 */ 758 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 759 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | 760 PTE_ATTRINDX_MASK; 761 /* preserve the hardware dirty information */ 762 if (pte_hw_dirty(pte)) 763 pte = pte_mkdirty(pte); 764 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 765 return pte; 766 } 767 768 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 769 { 770 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 771 } 772 773 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 774 extern int ptep_set_access_flags(struct vm_area_struct *vma, 775 unsigned long address, pte_t *ptep, 776 pte_t entry, int dirty); 777 778 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 779 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 780 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 781 unsigned long address, pmd_t *pmdp, 782 pmd_t entry, int dirty) 783 { 784 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 785 } 786 787 static inline int pud_devmap(pud_t pud) 788 { 789 return 0; 790 } 791 792 static inline int pgd_devmap(pgd_t pgd) 793 { 794 return 0; 795 } 796 #endif 797 798 /* 799 * Atomic pte/pmd modifications. 800 */ 801 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 802 static inline int __ptep_test_and_clear_young(pte_t *ptep) 803 { 804 pte_t old_pte, pte; 805 806 pte = READ_ONCE(*ptep); 807 do { 808 old_pte = pte; 809 pte = pte_mkold(pte); 810 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 811 pte_val(old_pte), pte_val(pte)); 812 } while (pte_val(pte) != pte_val(old_pte)); 813 814 return pte_young(pte); 815 } 816 817 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 818 unsigned long address, 819 pte_t *ptep) 820 { 821 return __ptep_test_and_clear_young(ptep); 822 } 823 824 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 825 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 826 unsigned long address, pte_t *ptep) 827 { 828 int young = ptep_test_and_clear_young(vma, address, ptep); 829 830 if (young) { 831 /* 832 * We can elide the trailing DSB here since the worst that can 833 * happen is that a CPU continues to use the young entry in its 834 * TLB and we mistakenly reclaim the associated page. The 835 * window for such an event is bounded by the next 836 * context-switch, which provides a DSB to complete the TLB 837 * invalidation. 838 */ 839 flush_tlb_page_nosync(vma, address); 840 } 841 842 return young; 843 } 844 845 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 846 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 847 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 848 unsigned long address, 849 pmd_t *pmdp) 850 { 851 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 852 } 853 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 854 855 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 856 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 857 unsigned long address, pte_t *ptep) 858 { 859 return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 860 } 861 862 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 863 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 864 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 865 unsigned long address, pmd_t *pmdp) 866 { 867 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 868 } 869 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 870 871 /* 872 * ptep_set_wrprotect - mark read-only while trasferring potential hardware 873 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 874 */ 875 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 876 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 877 { 878 pte_t old_pte, pte; 879 880 pte = READ_ONCE(*ptep); 881 do { 882 old_pte = pte; 883 pte = pte_wrprotect(pte); 884 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 885 pte_val(old_pte), pte_val(pte)); 886 } while (pte_val(pte) != pte_val(old_pte)); 887 } 888 889 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 890 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 891 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 892 unsigned long address, pmd_t *pmdp) 893 { 894 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 895 } 896 897 #define pmdp_establish pmdp_establish 898 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 899 unsigned long address, pmd_t *pmdp, pmd_t pmd) 900 { 901 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 902 } 903 #endif 904 905 /* 906 * Encode and decode a swap entry: 907 * bits 0-1: present (must be zero) 908 * bits 2-7: swap type 909 * bits 8-57: swap offset 910 * bit 58: PTE_PROT_NONE (must be zero) 911 */ 912 #define __SWP_TYPE_SHIFT 2 913 #define __SWP_TYPE_BITS 6 914 #define __SWP_OFFSET_BITS 50 915 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 916 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 917 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 918 919 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 920 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 921 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 922 923 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 924 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 925 926 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 927 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 928 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 929 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 930 931 /* 932 * Ensure that there are not more swap files than can be encoded in the kernel 933 * PTEs. 934 */ 935 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 936 937 extern int kern_addr_valid(unsigned long addr); 938 939 #ifdef CONFIG_ARM64_MTE 940 941 #define __HAVE_ARCH_PREPARE_TO_SWAP 942 static inline int arch_prepare_to_swap(struct page *page) 943 { 944 if (system_supports_mte()) 945 return mte_save_tags(page); 946 return 0; 947 } 948 949 #define __HAVE_ARCH_SWAP_INVALIDATE 950 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 951 { 952 if (system_supports_mte()) 953 mte_invalidate_tags(type, offset); 954 } 955 956 static inline void arch_swap_invalidate_area(int type) 957 { 958 if (system_supports_mte()) 959 mte_invalidate_tags_area(type); 960 } 961 962 #define __HAVE_ARCH_SWAP_RESTORE 963 static inline void arch_swap_restore(swp_entry_t entry, struct page *page) 964 { 965 if (system_supports_mte() && mte_restore_tags(entry, page)) 966 set_bit(PG_mte_tagged, &page->flags); 967 } 968 969 #endif /* CONFIG_ARM64_MTE */ 970 971 /* 972 * On AArch64, the cache coherency is handled via the set_pte_at() function. 973 */ 974 static inline void update_mmu_cache(struct vm_area_struct *vma, 975 unsigned long addr, pte_t *ptep) 976 { 977 /* 978 * We don't do anything here, so there's a very small chance of 979 * us retaking a user fault which we just fixed up. The alternative 980 * is doing a dsb(ishst), but that penalises the fastpath. 981 */ 982 } 983 984 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 985 986 #ifdef CONFIG_ARM64_PA_BITS_52 987 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 988 #else 989 #define phys_to_ttbr(addr) (addr) 990 #endif 991 992 /* 993 * On arm64 without hardware Access Flag, copying from user will fail because 994 * the pte is old and cannot be marked young. So we always end up with zeroed 995 * page after fork() + CoW for pfn mappings. We don't always have a 996 * hardware-managed access flag on arm64. 997 */ 998 static inline bool arch_faults_on_old_pte(void) 999 { 1000 WARN_ON(preemptible()); 1001 1002 return !cpu_has_hw_af(); 1003 } 1004 #define arch_faults_on_old_pte arch_faults_on_old_pte 1005 1006 /* 1007 * Experimentally, it's cheap to set the access flag in hardware and we 1008 * benefit from prefaulting mappings as 'old' to start with. 1009 */ 1010 static inline bool arch_wants_old_prefaulted_pte(void) 1011 { 1012 return !arch_faults_on_old_pte(); 1013 } 1014 #define arch_wants_old_prefaulted_pte arch_wants_old_prefaulted_pte 1015 1016 static inline pgprot_t arch_filter_pgprot(pgprot_t prot) 1017 { 1018 if (cpus_have_const_cap(ARM64_HAS_EPAN)) 1019 return prot; 1020 1021 if (pgprot_val(prot) != pgprot_val(PAGE_EXECONLY)) 1022 return prot; 1023 1024 return PAGE_READONLY_EXEC; 1025 } 1026 1027 1028 #endif /* !__ASSEMBLY__ */ 1029 1030 #endif /* __ASM_PGTABLE_H */ 1031