1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/pgtable-hwdef.h> 13 #include <asm/pgtable-prot.h> 14 #include <asm/tlbflush.h> 15 16 /* 17 * VMALLOC range. 18 * 19 * VMALLOC_START: beginning of the kernel vmalloc space 20 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space 21 * and fixed mappings 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 25 26 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 27 28 #define FIRST_USER_ADDRESS 0UL 29 30 #ifndef __ASSEMBLY__ 31 32 #include <asm/cmpxchg.h> 33 #include <asm/fixmap.h> 34 #include <linux/mmdebug.h> 35 #include <linux/mm_types.h> 36 #include <linux/sched.h> 37 38 extern void __pte_error(const char *file, int line, unsigned long val); 39 extern void __pmd_error(const char *file, int line, unsigned long val); 40 extern void __pud_error(const char *file, int line, unsigned long val); 41 extern void __pgd_error(const char *file, int line, unsigned long val); 42 43 /* 44 * ZERO_PAGE is a global shared page that is always zero: used 45 * for zero-mapped memory areas etc.. 46 */ 47 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 48 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 49 50 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 51 52 /* 53 * Macros to convert between a physical address and its placement in a 54 * page table entry, taking care of 52-bit addresses. 55 */ 56 #ifdef CONFIG_ARM64_PA_BITS_52 57 #define __pte_to_phys(pte) \ 58 ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 59 #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 60 #else 61 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 62 #define __phys_to_pte_val(phys) (phys) 63 #endif 64 65 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 66 #define pfn_pte(pfn,prot) \ 67 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 68 69 #define pte_none(pte) (!pte_val(pte)) 70 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 71 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 72 73 /* 74 * The following only work if pte_present(). Undefined behaviour otherwise. 75 */ 76 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 77 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 78 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 79 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 80 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 81 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 82 83 #define pte_cont_addr_end(addr, end) \ 84 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 85 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 86 }) 87 88 #define pmd_cont_addr_end(addr, end) \ 89 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 90 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 91 }) 92 93 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 94 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 95 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 96 97 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 98 /* 99 * Execute-only user mappings do not have the PTE_USER bit set. All valid 100 * kernel mappings have the PTE_UXN bit set. 101 */ 102 #define pte_valid_not_user(pte) \ 103 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 104 #define pte_valid_young(pte) \ 105 ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 106 #define pte_valid_user(pte) \ 107 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 108 109 /* 110 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 111 * so that we don't erroneously return false for pages that have been 112 * remapped as PROT_NONE but are yet to be flushed from the TLB. 113 */ 114 #define pte_accessible(mm, pte) \ 115 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 116 117 /* 118 * p??_access_permitted() is true for valid user mappings (subject to the 119 * write permission check) other than user execute-only which do not have the 120 * PTE_USER bit set. PROT_NONE mappings do not have the PTE_VALID bit set. 121 */ 122 #define pte_access_permitted(pte, write) \ 123 (pte_valid_user(pte) && (!(write) || pte_write(pte))) 124 #define pmd_access_permitted(pmd, write) \ 125 (pte_access_permitted(pmd_pte(pmd), (write))) 126 #define pud_access_permitted(pud, write) \ 127 (pte_access_permitted(pud_pte(pud), (write))) 128 129 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 130 { 131 pte_val(pte) &= ~pgprot_val(prot); 132 return pte; 133 } 134 135 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 136 { 137 pte_val(pte) |= pgprot_val(prot); 138 return pte; 139 } 140 141 static inline pte_t pte_wrprotect(pte_t pte) 142 { 143 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 144 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 145 return pte; 146 } 147 148 static inline pte_t pte_mkwrite(pte_t pte) 149 { 150 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 151 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 152 return pte; 153 } 154 155 static inline pte_t pte_mkclean(pte_t pte) 156 { 157 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 158 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 159 160 return pte; 161 } 162 163 static inline pte_t pte_mkdirty(pte_t pte) 164 { 165 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 166 167 if (pte_write(pte)) 168 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 169 170 return pte; 171 } 172 173 static inline pte_t pte_mkold(pte_t pte) 174 { 175 return clear_pte_bit(pte, __pgprot(PTE_AF)); 176 } 177 178 static inline pte_t pte_mkyoung(pte_t pte) 179 { 180 return set_pte_bit(pte, __pgprot(PTE_AF)); 181 } 182 183 static inline pte_t pte_mkspecial(pte_t pte) 184 { 185 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 186 } 187 188 static inline pte_t pte_mkcont(pte_t pte) 189 { 190 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 191 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 192 } 193 194 static inline pte_t pte_mknoncont(pte_t pte) 195 { 196 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 197 } 198 199 static inline pte_t pte_mkpresent(pte_t pte) 200 { 201 return set_pte_bit(pte, __pgprot(PTE_VALID)); 202 } 203 204 static inline pmd_t pmd_mkcont(pmd_t pmd) 205 { 206 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 207 } 208 209 static inline void set_pte(pte_t *ptep, pte_t pte) 210 { 211 WRITE_ONCE(*ptep, pte); 212 213 /* 214 * Only if the new pte is valid and kernel, otherwise TLB maintenance 215 * or update_mmu_cache() have the necessary barriers. 216 */ 217 if (pte_valid_not_user(pte)) 218 dsb(ishst); 219 } 220 221 extern void __sync_icache_dcache(pte_t pteval); 222 223 /* 224 * PTE bits configuration in the presence of hardware Dirty Bit Management 225 * (PTE_WRITE == PTE_DBM): 226 * 227 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 228 * 0 0 | 1 0 0 229 * 0 1 | 1 1 0 230 * 1 0 | 1 0 1 231 * 1 1 | 0 1 x 232 * 233 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 234 * the page fault mechanism. Checking the dirty status of a pte becomes: 235 * 236 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 237 */ 238 239 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, 240 pte_t pte) 241 { 242 pte_t old_pte; 243 244 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 245 return; 246 247 old_pte = READ_ONCE(*ptep); 248 249 if (!pte_valid(old_pte) || !pte_valid(pte)) 250 return; 251 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 252 return; 253 254 /* 255 * Check for potential race with hardware updates of the pte 256 * (ptep_set_access_flags safely changes valid ptes without going 257 * through an invalid entry). 258 */ 259 VM_WARN_ONCE(!pte_young(pte), 260 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 261 __func__, pte_val(old_pte), pte_val(pte)); 262 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 263 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 264 __func__, pte_val(old_pte), pte_val(pte)); 265 } 266 267 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 268 pte_t *ptep, pte_t pte) 269 { 270 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 271 __sync_icache_dcache(pte); 272 273 __check_racy_pte_update(mm, ptep, pte); 274 275 set_pte(ptep, pte); 276 } 277 278 #define __HAVE_ARCH_PTE_SAME 279 static inline int pte_same(pte_t pte_a, pte_t pte_b) 280 { 281 pteval_t lhs, rhs; 282 283 lhs = pte_val(pte_a); 284 rhs = pte_val(pte_b); 285 286 if (pte_present(pte_a)) 287 lhs &= ~PTE_RDONLY; 288 289 if (pte_present(pte_b)) 290 rhs &= ~PTE_RDONLY; 291 292 return (lhs == rhs); 293 } 294 295 /* 296 * Huge pte definitions. 297 */ 298 #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) 299 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 300 301 /* 302 * Hugetlb definitions. 303 */ 304 #define HUGE_MAX_HSTATE 4 305 #define HPAGE_SHIFT PMD_SHIFT 306 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 307 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 308 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 309 310 static inline pte_t pgd_pte(pgd_t pgd) 311 { 312 return __pte(pgd_val(pgd)); 313 } 314 315 static inline pte_t pud_pte(pud_t pud) 316 { 317 return __pte(pud_val(pud)); 318 } 319 320 static inline pud_t pte_pud(pte_t pte) 321 { 322 return __pud(pte_val(pte)); 323 } 324 325 static inline pmd_t pud_pmd(pud_t pud) 326 { 327 return __pmd(pud_val(pud)); 328 } 329 330 static inline pte_t pmd_pte(pmd_t pmd) 331 { 332 return __pte(pmd_val(pmd)); 333 } 334 335 static inline pmd_t pte_pmd(pte_t pte) 336 { 337 return __pmd(pte_val(pte)); 338 } 339 340 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 341 { 342 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 343 } 344 345 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 346 { 347 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 348 } 349 350 #ifdef CONFIG_NUMA_BALANCING 351 /* 352 * See the comment in include/asm-generic/pgtable.h 353 */ 354 static inline int pte_protnone(pte_t pte) 355 { 356 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 357 } 358 359 static inline int pmd_protnone(pmd_t pmd) 360 { 361 return pte_protnone(pmd_pte(pmd)); 362 } 363 #endif 364 365 /* 366 * THP definitions. 367 */ 368 369 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 370 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 371 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 372 373 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 374 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 375 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 376 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 377 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 378 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 379 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 380 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 381 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 382 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 383 #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) 384 385 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 386 387 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 388 389 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 390 391 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 392 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 393 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 394 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 395 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 396 397 #define pud_young(pud) pte_young(pud_pte(pud)) 398 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 399 #define pud_write(pud) pte_write(pud_pte(pud)) 400 401 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 402 403 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 404 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 405 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 406 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 407 408 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 409 410 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 411 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 412 413 #define __pgprot_modify(prot,mask,bits) \ 414 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 415 416 /* 417 * Mark the prot value as uncacheable and unbufferable. 418 */ 419 #define pgprot_noncached(prot) \ 420 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 421 #define pgprot_writecombine(prot) \ 422 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 423 #define pgprot_device(prot) \ 424 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 425 #define __HAVE_PHYS_MEM_ACCESS_PROT 426 struct file; 427 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 428 unsigned long size, pgprot_t vma_prot); 429 430 #define pmd_none(pmd) (!pmd_val(pmd)) 431 432 #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 433 434 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 435 PMD_TYPE_TABLE) 436 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 437 PMD_TYPE_SECT) 438 439 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 440 #define pud_sect(pud) (0) 441 #define pud_table(pud) (1) 442 #else 443 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 444 PUD_TYPE_SECT) 445 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 446 PUD_TYPE_TABLE) 447 #endif 448 449 extern pgd_t init_pg_dir[PTRS_PER_PGD]; 450 extern pgd_t init_pg_end[]; 451 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 452 extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 453 extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 454 455 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 456 457 static inline bool in_swapper_pgdir(void *addr) 458 { 459 return ((unsigned long)addr & PAGE_MASK) == 460 ((unsigned long)swapper_pg_dir & PAGE_MASK); 461 } 462 463 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 464 { 465 #ifdef __PAGETABLE_PMD_FOLDED 466 if (in_swapper_pgdir(pmdp)) { 467 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 468 return; 469 } 470 #endif /* __PAGETABLE_PMD_FOLDED */ 471 472 WRITE_ONCE(*pmdp, pmd); 473 474 if (pmd_valid(pmd)) 475 dsb(ishst); 476 } 477 478 static inline void pmd_clear(pmd_t *pmdp) 479 { 480 set_pmd(pmdp, __pmd(0)); 481 } 482 483 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 484 { 485 return __pmd_to_phys(pmd); 486 } 487 488 static inline void pte_unmap(pte_t *pte) { } 489 490 /* Find an entry in the third-level page table. */ 491 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 492 493 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 494 #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) 495 496 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 497 498 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 499 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 500 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 501 502 #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(__pmd_to_phys(pmd))) 503 504 /* use ONLY for statically allocated translation tables */ 505 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 506 507 /* 508 * Conversion functions: convert a page and protection to a page entry, 509 * and a page entry and page directory to the page they refer to. 510 */ 511 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 512 513 #if CONFIG_PGTABLE_LEVELS > 2 514 515 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 516 517 #define pud_none(pud) (!pud_val(pud)) 518 #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 519 #define pud_present(pud) pte_present(pud_pte(pud)) 520 #define pud_valid(pud) pte_valid(pud_pte(pud)) 521 522 static inline void set_pud(pud_t *pudp, pud_t pud) 523 { 524 #ifdef __PAGETABLE_PUD_FOLDED 525 if (in_swapper_pgdir(pudp)) { 526 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 527 return; 528 } 529 #endif /* __PAGETABLE_PUD_FOLDED */ 530 531 WRITE_ONCE(*pudp, pud); 532 533 if (pud_valid(pud)) 534 dsb(ishst); 535 } 536 537 static inline void pud_clear(pud_t *pudp) 538 { 539 set_pud(pudp, __pud(0)); 540 } 541 542 static inline phys_addr_t pud_page_paddr(pud_t pud) 543 { 544 return __pud_to_phys(pud); 545 } 546 547 /* Find an entry in the second-level page table. */ 548 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 549 550 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 551 #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) 552 553 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 554 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 555 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 556 557 #define pud_page(pud) pfn_to_page(__phys_to_pfn(__pud_to_phys(pud))) 558 559 /* use ONLY for statically allocated translation tables */ 560 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 561 562 #else 563 564 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 565 566 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 567 #define pmd_set_fixmap(addr) NULL 568 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 569 #define pmd_clear_fixmap() 570 571 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 572 573 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 574 575 #if CONFIG_PGTABLE_LEVELS > 3 576 577 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 578 579 #define pgd_none(pgd) (!pgd_val(pgd)) 580 #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 581 #define pgd_present(pgd) (pgd_val(pgd)) 582 583 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 584 { 585 if (in_swapper_pgdir(pgdp)) { 586 set_swapper_pgd(pgdp, pgd); 587 return; 588 } 589 590 WRITE_ONCE(*pgdp, pgd); 591 dsb(ishst); 592 } 593 594 static inline void pgd_clear(pgd_t *pgdp) 595 { 596 set_pgd(pgdp, __pgd(0)); 597 } 598 599 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 600 { 601 return __pgd_to_phys(pgd); 602 } 603 604 /* Find an entry in the frst-level page table. */ 605 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 606 607 #define pud_offset_phys(dir, addr) (pgd_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 608 #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) 609 610 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 611 #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) 612 #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 613 614 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 615 616 /* use ONLY for statically allocated translation tables */ 617 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 618 619 #else 620 621 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 622 623 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 624 #define pud_set_fixmap(addr) NULL 625 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 626 #define pud_clear_fixmap() 627 628 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 629 630 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 631 632 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 633 634 /* to find an entry in a page-table-directory */ 635 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 636 637 #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) 638 639 #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) 640 641 /* to find an entry in a kernel page-table-directory */ 642 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 643 644 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 645 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 646 647 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 648 { 649 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 650 PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 651 /* preserve the hardware dirty information */ 652 if (pte_hw_dirty(pte)) 653 pte = pte_mkdirty(pte); 654 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 655 return pte; 656 } 657 658 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 659 { 660 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 661 } 662 663 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 664 extern int ptep_set_access_flags(struct vm_area_struct *vma, 665 unsigned long address, pte_t *ptep, 666 pte_t entry, int dirty); 667 668 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 669 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 670 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 671 unsigned long address, pmd_t *pmdp, 672 pmd_t entry, int dirty) 673 { 674 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 675 } 676 #endif 677 678 /* 679 * Atomic pte/pmd modifications. 680 */ 681 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 682 static inline int __ptep_test_and_clear_young(pte_t *ptep) 683 { 684 pte_t old_pte, pte; 685 686 pte = READ_ONCE(*ptep); 687 do { 688 old_pte = pte; 689 pte = pte_mkold(pte); 690 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 691 pte_val(old_pte), pte_val(pte)); 692 } while (pte_val(pte) != pte_val(old_pte)); 693 694 return pte_young(pte); 695 } 696 697 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 698 unsigned long address, 699 pte_t *ptep) 700 { 701 return __ptep_test_and_clear_young(ptep); 702 } 703 704 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 705 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 706 unsigned long address, pte_t *ptep) 707 { 708 int young = ptep_test_and_clear_young(vma, address, ptep); 709 710 if (young) { 711 /* 712 * We can elide the trailing DSB here since the worst that can 713 * happen is that a CPU continues to use the young entry in its 714 * TLB and we mistakenly reclaim the associated page. The 715 * window for such an event is bounded by the next 716 * context-switch, which provides a DSB to complete the TLB 717 * invalidation. 718 */ 719 flush_tlb_page_nosync(vma, address); 720 } 721 722 return young; 723 } 724 725 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 726 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 727 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 728 unsigned long address, 729 pmd_t *pmdp) 730 { 731 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 732 } 733 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 734 735 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 736 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 737 unsigned long address, pte_t *ptep) 738 { 739 return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 740 } 741 742 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 743 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 744 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 745 unsigned long address, pmd_t *pmdp) 746 { 747 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 748 } 749 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 750 751 /* 752 * ptep_set_wrprotect - mark read-only while trasferring potential hardware 753 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 754 */ 755 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 756 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 757 { 758 pte_t old_pte, pte; 759 760 pte = READ_ONCE(*ptep); 761 do { 762 old_pte = pte; 763 /* 764 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 765 * clear), set the PTE_DIRTY bit. 766 */ 767 if (pte_hw_dirty(pte)) 768 pte = pte_mkdirty(pte); 769 pte = pte_wrprotect(pte); 770 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 771 pte_val(old_pte), pte_val(pte)); 772 } while (pte_val(pte) != pte_val(old_pte)); 773 } 774 775 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 776 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 777 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 778 unsigned long address, pmd_t *pmdp) 779 { 780 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 781 } 782 783 #define pmdp_establish pmdp_establish 784 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 785 unsigned long address, pmd_t *pmdp, pmd_t pmd) 786 { 787 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 788 } 789 #endif 790 791 /* 792 * Encode and decode a swap entry: 793 * bits 0-1: present (must be zero) 794 * bits 2-7: swap type 795 * bits 8-57: swap offset 796 * bit 58: PTE_PROT_NONE (must be zero) 797 */ 798 #define __SWP_TYPE_SHIFT 2 799 #define __SWP_TYPE_BITS 6 800 #define __SWP_OFFSET_BITS 50 801 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 802 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 803 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 804 805 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 806 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 807 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 808 809 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 810 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 811 812 /* 813 * Ensure that there are not more swap files than can be encoded in the kernel 814 * PTEs. 815 */ 816 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 817 818 extern int kern_addr_valid(unsigned long addr); 819 820 #include <asm-generic/pgtable.h> 821 822 static inline void pgtable_cache_init(void) { } 823 824 /* 825 * On AArch64, the cache coherency is handled via the set_pte_at() function. 826 */ 827 static inline void update_mmu_cache(struct vm_area_struct *vma, 828 unsigned long addr, pte_t *ptep) 829 { 830 /* 831 * We don't do anything here, so there's a very small chance of 832 * us retaking a user fault which we just fixed up. The alternative 833 * is doing a dsb(ishst), but that penalises the fastpath. 834 */ 835 } 836 837 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 838 839 #define kc_vaddr_to_offset(v) ((v) & ~VA_START) 840 #define kc_offset_to_vaddr(o) ((o) | VA_START) 841 842 #ifdef CONFIG_ARM64_PA_BITS_52 843 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 844 #else 845 #define phys_to_ttbr(addr) (addr) 846 #endif 847 848 #endif /* !__ASSEMBLY__ */ 849 850 #endif /* __ASM_PGTABLE_H */ 851