1 /*
2  * Copyright (C) 2012 ARM Ltd.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16 #ifndef __ASM_PGTABLE_HWDEF_H
17 #define __ASM_PGTABLE_HWDEF_H
18 
19 /*
20  * Number of page-table levels required to address 'va_bits' wide
21  * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
22  * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
23  *
24  *  levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
25  *
26  * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
27  *
28  * We cannot include linux/kernel.h which defines DIV_ROUND_UP here
29  * due to build issues. So we open code DIV_ROUND_UP here:
30  *
31  *	((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
32  *
33  * which gets simplified as :
34  */
35 #define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))
36 
37 /*
38  * Size mapped by an entry at level n ( 0 <= n <= 3)
39  * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
40  * in the final page. The maximum number of translation levels supported by
41  * the architecture is 4. Hence, starting at at level n, we have further
42  * ((4 - n) - 1) levels of translation excluding the offset within the page.
43  * So, the total number of bits mapped by an entry at level n is :
44  *
45  *  ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT
46  *
47  * Rearranging it a bit we get :
48  *   (4 - n) * (PAGE_SHIFT - 3) + 3
49  */
50 #define ARM64_HW_PGTABLE_LEVEL_SHIFT(n)	((PAGE_SHIFT - 3) * (4 - (n)) + 3)
51 
52 #define PTRS_PER_PTE		(1 << (PAGE_SHIFT - 3))
53 
54 /*
55  * PMD_SHIFT determines the size a level 2 page table entry can map.
56  */
57 #if CONFIG_PGTABLE_LEVELS > 2
58 #define PMD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(2)
59 #define PMD_SIZE		(_AC(1, UL) << PMD_SHIFT)
60 #define PMD_MASK		(~(PMD_SIZE-1))
61 #define PTRS_PER_PMD		PTRS_PER_PTE
62 #endif
63 
64 /*
65  * PUD_SHIFT determines the size a level 1 page table entry can map.
66  */
67 #if CONFIG_PGTABLE_LEVELS > 3
68 #define PUD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(1)
69 #define PUD_SIZE		(_AC(1, UL) << PUD_SHIFT)
70 #define PUD_MASK		(~(PUD_SIZE-1))
71 #define PTRS_PER_PUD		PTRS_PER_PTE
72 #endif
73 
74 /*
75  * PGDIR_SHIFT determines the size a top-level page table entry can map
76  * (depending on the configuration, this level can be 0, 1 or 2).
77  */
78 #define PGDIR_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
79 #define PGDIR_SIZE		(_AC(1, UL) << PGDIR_SHIFT)
80 #define PGDIR_MASK		(~(PGDIR_SIZE-1))
81 #define PTRS_PER_PGD		(1 << (VA_BITS - PGDIR_SHIFT))
82 
83 /*
84  * Section address mask and size definitions.
85  */
86 #define SECTION_SHIFT		PMD_SHIFT
87 #define SECTION_SIZE		(_AC(1, UL) << SECTION_SHIFT)
88 #define SECTION_MASK		(~(SECTION_SIZE-1))
89 
90 /*
91  * Contiguous page definitions.
92  */
93 #ifdef CONFIG_ARM64_64K_PAGES
94 #define CONT_PTE_SHIFT		5
95 #define CONT_PMD_SHIFT		5
96 #elif defined(CONFIG_ARM64_16K_PAGES)
97 #define CONT_PTE_SHIFT		7
98 #define CONT_PMD_SHIFT		5
99 #else
100 #define CONT_PTE_SHIFT		4
101 #define CONT_PMD_SHIFT		4
102 #endif
103 
104 #define CONT_PTES		(1 << CONT_PTE_SHIFT)
105 #define CONT_PTE_SIZE		(CONT_PTES * PAGE_SIZE)
106 #define CONT_PTE_MASK		(~(CONT_PTE_SIZE - 1))
107 #define CONT_PMDS		(1 << CONT_PMD_SHIFT)
108 #define CONT_PMD_SIZE		(CONT_PMDS * PMD_SIZE)
109 #define CONT_PMD_MASK		(~(CONT_PMD_SIZE - 1))
110 /* the the numerical offset of the PTE within a range of CONT_PTES */
111 #define CONT_RANGE_OFFSET(addr) (((addr)>>PAGE_SHIFT)&(CONT_PTES-1))
112 
113 /*
114  * Hardware page table definitions.
115  *
116  * Level 1 descriptor (PUD).
117  */
118 #define PUD_TYPE_TABLE		(_AT(pudval_t, 3) << 0)
119 #define PUD_TABLE_BIT		(_AT(pgdval_t, 1) << 1)
120 #define PUD_TYPE_MASK		(_AT(pgdval_t, 3) << 0)
121 #define PUD_TYPE_SECT		(_AT(pgdval_t, 1) << 0)
122 
123 /*
124  * Level 2 descriptor (PMD).
125  */
126 #define PMD_TYPE_MASK		(_AT(pmdval_t, 3) << 0)
127 #define PMD_TYPE_FAULT		(_AT(pmdval_t, 0) << 0)
128 #define PMD_TYPE_TABLE		(_AT(pmdval_t, 3) << 0)
129 #define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
130 #define PMD_TABLE_BIT		(_AT(pmdval_t, 1) << 1)
131 
132 /*
133  * Section
134  */
135 #define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)
136 #define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */
137 #define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */
138 #define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)
139 #define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
140 #define PMD_SECT_NG		(_AT(pmdval_t, 1) << 11)
141 #define PMD_SECT_CONT		(_AT(pmdval_t, 1) << 52)
142 #define PMD_SECT_PXN		(_AT(pmdval_t, 1) << 53)
143 #define PMD_SECT_UXN		(_AT(pmdval_t, 1) << 54)
144 
145 /*
146  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
147  */
148 #define PMD_ATTRINDX(t)		(_AT(pmdval_t, (t)) << 2)
149 #define PMD_ATTRINDX_MASK	(_AT(pmdval_t, 7) << 2)
150 
151 /*
152  * Level 3 descriptor (PTE).
153  */
154 #define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
155 #define PTE_TYPE_FAULT		(_AT(pteval_t, 0) << 0)
156 #define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
157 #define PTE_TABLE_BIT		(_AT(pteval_t, 1) << 1)
158 #define PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
159 #define PTE_RDONLY		(_AT(pteval_t, 1) << 7)		/* AP[2] */
160 #define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
161 #define PTE_AF			(_AT(pteval_t, 1) << 10)	/* Access Flag */
162 #define PTE_NG			(_AT(pteval_t, 1) << 11)	/* nG */
163 #define PTE_DBM			(_AT(pteval_t, 1) << 51)	/* Dirty Bit Management */
164 #define PTE_CONT		(_AT(pteval_t, 1) << 52)	/* Contiguous range */
165 #define PTE_PXN			(_AT(pteval_t, 1) << 53)	/* Privileged XN */
166 #define PTE_UXN			(_AT(pteval_t, 1) << 54)	/* User XN */
167 
168 /*
169  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
170  */
171 #define PTE_ATTRINDX(t)		(_AT(pteval_t, (t)) << 2)
172 #define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)
173 
174 /*
175  * 2nd stage PTE definitions
176  */
177 #define PTE_S2_RDONLY		(_AT(pteval_t, 1) << 6)   /* HAP[2:1] */
178 #define PTE_S2_RDWR		(_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
179 
180 #define PMD_S2_RDONLY		(_AT(pmdval_t, 1) << 6)   /* HAP[2:1] */
181 #define PMD_S2_RDWR		(_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */
182 
183 /*
184  * Memory Attribute override for Stage-2 (MemAttr[3:0])
185  */
186 #define PTE_S2_MEMATTR(t)	(_AT(pteval_t, (t)) << 2)
187 #define PTE_S2_MEMATTR_MASK	(_AT(pteval_t, 0xf) << 2)
188 
189 /*
190  * EL2/HYP PTE/PMD definitions
191  */
192 #define PMD_HYP			PMD_SECT_USER
193 #define PTE_HYP			PTE_USER
194 
195 /*
196  * Highest possible physical address supported.
197  */
198 #define PHYS_MASK_SHIFT		(48)
199 #define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)
200 
201 /*
202  * TCR flags.
203  */
204 #define TCR_T0SZ_OFFSET		0
205 #define TCR_T1SZ_OFFSET		16
206 #define TCR_T0SZ(x)		((UL(64) - (x)) << TCR_T0SZ_OFFSET)
207 #define TCR_T1SZ(x)		((UL(64) - (x)) << TCR_T1SZ_OFFSET)
208 #define TCR_TxSZ(x)		(TCR_T0SZ(x) | TCR_T1SZ(x))
209 #define TCR_TxSZ_WIDTH		6
210 
211 #define TCR_IRGN0_SHIFT		8
212 #define TCR_IRGN0_MASK		(UL(3) << TCR_IRGN0_SHIFT)
213 #define TCR_IRGN0_NC		(UL(0) << TCR_IRGN0_SHIFT)
214 #define TCR_IRGN0_WBWA		(UL(1) << TCR_IRGN0_SHIFT)
215 #define TCR_IRGN0_WT		(UL(2) << TCR_IRGN0_SHIFT)
216 #define TCR_IRGN0_WBnWA		(UL(3) << TCR_IRGN0_SHIFT)
217 
218 #define TCR_IRGN1_SHIFT		24
219 #define TCR_IRGN1_MASK		(UL(3) << TCR_IRGN1_SHIFT)
220 #define TCR_IRGN1_NC		(UL(0) << TCR_IRGN1_SHIFT)
221 #define TCR_IRGN1_WBWA		(UL(1) << TCR_IRGN1_SHIFT)
222 #define TCR_IRGN1_WT		(UL(2) << TCR_IRGN1_SHIFT)
223 #define TCR_IRGN1_WBnWA		(UL(3) << TCR_IRGN1_SHIFT)
224 
225 #define TCR_IRGN_NC		(TCR_IRGN0_NC | TCR_IRGN1_NC)
226 #define TCR_IRGN_WBWA		(TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
227 #define TCR_IRGN_WT		(TCR_IRGN0_WT | TCR_IRGN1_WT)
228 #define TCR_IRGN_WBnWA		(TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
229 #define TCR_IRGN_MASK		(TCR_IRGN0_MASK | TCR_IRGN1_MASK)
230 
231 
232 #define TCR_ORGN0_SHIFT		10
233 #define TCR_ORGN0_MASK		(UL(3) << TCR_ORGN0_SHIFT)
234 #define TCR_ORGN0_NC		(UL(0) << TCR_ORGN0_SHIFT)
235 #define TCR_ORGN0_WBWA		(UL(1) << TCR_ORGN0_SHIFT)
236 #define TCR_ORGN0_WT		(UL(2) << TCR_ORGN0_SHIFT)
237 #define TCR_ORGN0_WBnWA		(UL(3) << TCR_ORGN0_SHIFT)
238 
239 #define TCR_ORGN1_SHIFT		26
240 #define TCR_ORGN1_MASK		(UL(3) << TCR_ORGN1_SHIFT)
241 #define TCR_ORGN1_NC		(UL(0) << TCR_ORGN1_SHIFT)
242 #define TCR_ORGN1_WBWA		(UL(1) << TCR_ORGN1_SHIFT)
243 #define TCR_ORGN1_WT		(UL(2) << TCR_ORGN1_SHIFT)
244 #define TCR_ORGN1_WBnWA		(UL(3) << TCR_ORGN1_SHIFT)
245 
246 #define TCR_ORGN_NC		(TCR_ORGN0_NC | TCR_ORGN1_NC)
247 #define TCR_ORGN_WBWA		(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
248 #define TCR_ORGN_WT		(TCR_ORGN0_WT | TCR_ORGN1_WT)
249 #define TCR_ORGN_WBnWA		(TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)
250 #define TCR_ORGN_MASK		(TCR_ORGN0_MASK | TCR_ORGN1_MASK)
251 
252 #define TCR_SH0_SHIFT		12
253 #define TCR_SH0_MASK		(UL(3) << TCR_SH0_SHIFT)
254 #define TCR_SH0_INNER		(UL(3) << TCR_SH0_SHIFT)
255 
256 #define TCR_SH1_SHIFT		28
257 #define TCR_SH1_MASK		(UL(3) << TCR_SH1_SHIFT)
258 #define TCR_SH1_INNER		(UL(3) << TCR_SH1_SHIFT)
259 #define TCR_SHARED		(TCR_SH0_INNER | TCR_SH1_INNER)
260 
261 #define TCR_TG0_SHIFT		14
262 #define TCR_TG0_MASK		(UL(3) << TCR_TG0_SHIFT)
263 #define TCR_TG0_4K		(UL(0) << TCR_TG0_SHIFT)
264 #define TCR_TG0_64K		(UL(1) << TCR_TG0_SHIFT)
265 #define TCR_TG0_16K		(UL(2) << TCR_TG0_SHIFT)
266 
267 #define TCR_TG1_SHIFT		30
268 #define TCR_TG1_MASK		(UL(3) << TCR_TG1_SHIFT)
269 #define TCR_TG1_16K		(UL(1) << TCR_TG1_SHIFT)
270 #define TCR_TG1_4K		(UL(2) << TCR_TG1_SHIFT)
271 #define TCR_TG1_64K		(UL(3) << TCR_TG1_SHIFT)
272 
273 #define TCR_ASID16		(UL(1) << 36)
274 #define TCR_TBI0		(UL(1) << 37)
275 #define TCR_HA			(UL(1) << 39)
276 #define TCR_HD			(UL(1) << 40)
277 
278 #endif
279