1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f04d8f0SCatalin Marinas /* 34f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 44f04d8f0SCatalin Marinas */ 54f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_HWDEF_H 64f04d8f0SCatalin Marinas #define __ASM_PGTABLE_HWDEF_H 74f04d8f0SCatalin Marinas 8529c4b05SKristina Martsenko #include <asm/memory.h> 9529c4b05SKristina Martsenko 10686e7838SSuzuki K. Poulose /* 11686e7838SSuzuki K. Poulose * Number of page-table levels required to address 'va_bits' wide 12686e7838SSuzuki K. Poulose * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT) 13686e7838SSuzuki K. Poulose * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence: 14686e7838SSuzuki K. Poulose * 15686e7838SSuzuki K. Poulose * levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3)) 16686e7838SSuzuki K. Poulose * 17686e7838SSuzuki K. Poulose * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d)) 18686e7838SSuzuki K. Poulose * 19686e7838SSuzuki K. Poulose * We cannot include linux/kernel.h which defines DIV_ROUND_UP here 20686e7838SSuzuki K. Poulose * due to build issues. So we open code DIV_ROUND_UP here: 21686e7838SSuzuki K. Poulose * 22686e7838SSuzuki K. Poulose * ((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3)) 23686e7838SSuzuki K. Poulose * 24686e7838SSuzuki K. Poulose * which gets simplified as : 25686e7838SSuzuki K. Poulose */ 26686e7838SSuzuki K. Poulose #define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3)) 27686e7838SSuzuki K. Poulose 28686e7838SSuzuki K. Poulose /* 29686e7838SSuzuki K. Poulose * Size mapped by an entry at level n ( 0 <= n <= 3) 30686e7838SSuzuki K. Poulose * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits 31686e7838SSuzuki K. Poulose * in the final page. The maximum number of translation levels supported by 32686e7838SSuzuki K. Poulose * the architecture is 4. Hence, starting at at level n, we have further 33686e7838SSuzuki K. Poulose * ((4 - n) - 1) levels of translation excluding the offset within the page. 34686e7838SSuzuki K. Poulose * So, the total number of bits mapped by an entry at level n is : 35686e7838SSuzuki K. Poulose * 36686e7838SSuzuki K. Poulose * ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT 37686e7838SSuzuki K. Poulose * 38686e7838SSuzuki K. Poulose * Rearranging it a bit we get : 39686e7838SSuzuki K. Poulose * (4 - n) * (PAGE_SHIFT - 3) + 3 40686e7838SSuzuki K. Poulose */ 41686e7838SSuzuki K. Poulose #define ARM64_HW_PGTABLE_LEVEL_SHIFT(n) ((PAGE_SHIFT - 3) * (4 - (n)) + 3) 42686e7838SSuzuki K. Poulose 436b4fee24SCatalin Marinas #define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3)) 446b4fee24SCatalin Marinas 456b4fee24SCatalin Marinas /* 466b4fee24SCatalin Marinas * PMD_SHIFT determines the size a level 2 page table entry can map. 476b4fee24SCatalin Marinas */ 489f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 49686e7838SSuzuki K. Poulose #define PMD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(2) 506b4fee24SCatalin Marinas #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT) 516b4fee24SCatalin Marinas #define PMD_MASK (~(PMD_SIZE-1)) 526b4fee24SCatalin Marinas #define PTRS_PER_PMD PTRS_PER_PTE 534f04d8f0SCatalin Marinas #endif 544f04d8f0SCatalin Marinas 554f04d8f0SCatalin Marinas /* 566b4fee24SCatalin Marinas * PUD_SHIFT determines the size a level 1 page table entry can map. 576b4fee24SCatalin Marinas */ 589f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 59686e7838SSuzuki K. Poulose #define PUD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(1) 606b4fee24SCatalin Marinas #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT) 616b4fee24SCatalin Marinas #define PUD_MASK (~(PUD_SIZE-1)) 626b4fee24SCatalin Marinas #define PTRS_PER_PUD PTRS_PER_PTE 636b4fee24SCatalin Marinas #endif 646b4fee24SCatalin Marinas 656b4fee24SCatalin Marinas /* 666b4fee24SCatalin Marinas * PGDIR_SHIFT determines the size a top-level page table entry can map 676b4fee24SCatalin Marinas * (depending on the configuration, this level can be 0, 1 or 2). 686b4fee24SCatalin Marinas */ 69686e7838SSuzuki K. Poulose #define PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS) 706b4fee24SCatalin Marinas #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) 716b4fee24SCatalin Marinas #define PGDIR_MASK (~(PGDIR_SIZE-1)) 72218564b1SBhupesh Sharma #define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT)) 736b4fee24SCatalin Marinas 746b4fee24SCatalin Marinas /* 756b4fee24SCatalin Marinas * Section address mask and size definitions. 766b4fee24SCatalin Marinas */ 776b4fee24SCatalin Marinas #define SECTION_SHIFT PMD_SHIFT 786b4fee24SCatalin Marinas #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT) 796b4fee24SCatalin Marinas #define SECTION_MASK (~(SECTION_SIZE-1)) 806b4fee24SCatalin Marinas 816b4fee24SCatalin Marinas /* 82ecf35a23SJeremy Linton * Contiguous page definitions. 83ecf35a23SJeremy Linton */ 8466b3923aSDavid Woods #ifdef CONFIG_ARM64_64K_PAGES 85a1634a54SGavin Shan #define CONT_PTE_SHIFT (5 + PAGE_SHIFT) 86a1634a54SGavin Shan #define CONT_PMD_SHIFT (5 + PMD_SHIFT) 8766b3923aSDavid Woods #elif defined(CONFIG_ARM64_16K_PAGES) 88a1634a54SGavin Shan #define CONT_PTE_SHIFT (7 + PAGE_SHIFT) 89a1634a54SGavin Shan #define CONT_PMD_SHIFT (5 + PMD_SHIFT) 9066b3923aSDavid Woods #else 91a1634a54SGavin Shan #define CONT_PTE_SHIFT (4 + PAGE_SHIFT) 92a1634a54SGavin Shan #define CONT_PMD_SHIFT (4 + PMD_SHIFT) 9366b3923aSDavid Woods #endif 9466b3923aSDavid Woods 95a1634a54SGavin Shan #define CONT_PTES (1 << (CONT_PTE_SHIFT - PAGE_SHIFT)) 9666b3923aSDavid Woods #define CONT_PTE_SIZE (CONT_PTES * PAGE_SIZE) 9766b3923aSDavid Woods #define CONT_PTE_MASK (~(CONT_PTE_SIZE - 1)) 98a1634a54SGavin Shan #define CONT_PMDS (1 << (CONT_PMD_SHIFT - PMD_SHIFT)) 9966b3923aSDavid Woods #define CONT_PMD_SIZE (CONT_PMDS * PMD_SIZE) 10066b3923aSDavid Woods #define CONT_PMD_MASK (~(CONT_PMD_SIZE - 1)) 101ecf35a23SJeremy Linton /* the the numerical offset of the PTE within a range of CONT_PTES */ 102ecf35a23SJeremy Linton #define CONT_RANGE_OFFSET(addr) (((addr)>>PAGE_SHIFT)&(CONT_PTES-1)) 103ecf35a23SJeremy Linton 104ecf35a23SJeremy Linton /* 1054f04d8f0SCatalin Marinas * Hardware page table definitions. 1064f04d8f0SCatalin Marinas * 107084bd298SSteve Capper * Level 1 descriptor (PUD). 108084bd298SSteve Capper */ 109c79b954bSJungseok Lee #define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0) 11029d9bef1SPunit Agrawal #define PUD_TABLE_BIT (_AT(pudval_t, 1) << 1) 11129d9bef1SPunit Agrawal #define PUD_TYPE_MASK (_AT(pudval_t, 3) << 0) 11229d9bef1SPunit Agrawal #define PUD_TYPE_SECT (_AT(pudval_t, 1) << 0) 1137ea40889SPavel Tatashin #define PUD_SECT_RDONLY (_AT(pudval_t, 1) << 7) /* AP[2] */ 114084bd298SSteve Capper 115084bd298SSteve Capper /* 1164f04d8f0SCatalin Marinas * Level 2 descriptor (PMD). 1174f04d8f0SCatalin Marinas */ 1184f04d8f0SCatalin Marinas #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 1194f04d8f0SCatalin Marinas #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 1204f04d8f0SCatalin Marinas #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 121084bd298SSteve Capper #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 1224f04d8f0SCatalin Marinas 1234f04d8f0SCatalin Marinas /* 1244f04d8f0SCatalin Marinas * Section 1254f04d8f0SCatalin Marinas */ 126af074848SSteve Capper #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 127af074848SSteve Capper #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 128af074848SSteve Capper #define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */ 1294f04d8f0SCatalin Marinas #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 1304f04d8f0SCatalin Marinas #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 1314f04d8f0SCatalin Marinas #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 132ecf35a23SJeremy Linton #define PMD_SECT_CONT (_AT(pmdval_t, 1) << 52) 1338e620b04SCatalin Marinas #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 1348e620b04SCatalin Marinas #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) 1354f04d8f0SCatalin Marinas 1364f04d8f0SCatalin Marinas /* 1374f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 1384f04d8f0SCatalin Marinas */ 1394f04d8f0SCatalin Marinas #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) 1404f04d8f0SCatalin Marinas #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) 1414f04d8f0SCatalin Marinas 1424f04d8f0SCatalin Marinas /* 1434f04d8f0SCatalin Marinas * Level 3 descriptor (PTE). 1444f04d8f0SCatalin Marinas */ 145201d355cSAnshuman Khandual #define PTE_VALID (_AT(pteval_t, 1) << 0) 1464f04d8f0SCatalin Marinas #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 1474f04d8f0SCatalin Marinas #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 148084bd298SSteve Capper #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 1494f04d8f0SCatalin Marinas #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 1504f04d8f0SCatalin Marinas #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 1514f04d8f0SCatalin Marinas #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 1524f04d8f0SCatalin Marinas #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 1534f04d8f0SCatalin Marinas #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 1548ef8f360SDave Martin #define PTE_GP (_AT(pteval_t, 1) << 50) /* BTI guarded */ 1552f4b829cSCatalin Marinas #define PTE_DBM (_AT(pteval_t, 1) << 51) /* Dirty Bit Management */ 156ecf35a23SJeremy Linton #define PTE_CONT (_AT(pteval_t, 1) << 52) /* Contiguous range */ 1578e620b04SCatalin Marinas #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ 1588e620b04SCatalin Marinas #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ 1591166f3feSMarc Zyngier #define PTE_HYP_XN (_AT(pteval_t, 1) << 54) /* HYP XN */ 1604f04d8f0SCatalin Marinas 161e6d588a8SKristina Martsenko #define PTE_ADDR_LOW (((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT) 16275387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 163e6d588a8SKristina Martsenko #define PTE_ADDR_HIGH (_AT(pteval_t, 0xf) << 12) 16475387b92SKristina Martsenko #define PTE_ADDR_MASK (PTE_ADDR_LOW | PTE_ADDR_HIGH) 16575387b92SKristina Martsenko #else 16675387b92SKristina Martsenko #define PTE_ADDR_MASK PTE_ADDR_LOW 167e6d588a8SKristina Martsenko #endif 168e6d588a8SKristina Martsenko 1694f04d8f0SCatalin Marinas /* 1704f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 1714f04d8f0SCatalin Marinas */ 1724f04d8f0SCatalin Marinas #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) 1734f04d8f0SCatalin Marinas #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) 1744f04d8f0SCatalin Marinas 1754f04d8f0SCatalin Marinas /* 17636311607SMarc Zyngier * 2nd stage PTE definitions 17736311607SMarc Zyngier */ 17836311607SMarc Zyngier #define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */ 17936311607SMarc Zyngier #define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */ 180fefb876bSMarc Zyngier #define PTE_S2_XN (_AT(pteval_t, 2) << 53) /* XN[1:0] */ 18136311607SMarc Zyngier 1828199ed0eSMario Smarduch #define PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[2:1] */ 183ad361f09SChristoffer Dall #define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */ 184fefb876bSMarc Zyngier #define PMD_S2_XN (_AT(pmdval_t, 2) << 53) /* XN[1:0] */ 185ad361f09SChristoffer Dall 186b8e0ba7cSPunit Agrawal #define PUD_S2_RDONLY (_AT(pudval_t, 1) << 6) /* HAP[2:1] */ 187b8e0ba7cSPunit Agrawal #define PUD_S2_RDWR (_AT(pudval_t, 3) << 6) /* HAP[2:1] */ 18886d1c55eSPunit Agrawal #define PUD_S2_XN (_AT(pudval_t, 2) << 53) /* XN[1:0] */ 18986d1c55eSPunit Agrawal 19036311607SMarc Zyngier /* 19136311607SMarc Zyngier * Memory Attribute override for Stage-2 (MemAttr[3:0]) 19236311607SMarc Zyngier */ 19336311607SMarc Zyngier #define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2) 19436311607SMarc Zyngier 19536311607SMarc Zyngier /* 19636311607SMarc Zyngier * EL2/HYP PTE/PMD definitions 19736311607SMarc Zyngier */ 19836311607SMarc Zyngier #define PMD_HYP PMD_SECT_USER 19936311607SMarc Zyngier #define PTE_HYP PTE_USER 20036311607SMarc Zyngier 20136311607SMarc Zyngier /* 20287366d8cSRadha Mohan Chintakuntla * Highest possible physical address supported. 2034f04d8f0SCatalin Marinas */ 204982aa7c5SKristina Martsenko #define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS) 2054f04d8f0SCatalin Marinas #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) 2064f04d8f0SCatalin Marinas 2075ffdfaedSVladimir Murzin #define TTBR_CNP_BIT (UL(1) << 0) 2085ffdfaedSVladimir Murzin 2094f04d8f0SCatalin Marinas /* 2104f04d8f0SCatalin Marinas * TCR flags. 2114f04d8f0SCatalin Marinas */ 212dd006da2SArd Biesheuvel #define TCR_T0SZ_OFFSET 0 213dd006da2SArd Biesheuvel #define TCR_T1SZ_OFFSET 16 214dd006da2SArd Biesheuvel #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET) 215dd006da2SArd Biesheuvel #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET) 216dd006da2SArd Biesheuvel #define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) 217dd006da2SArd Biesheuvel #define TCR_TxSZ_WIDTH 6 218adf75899SMark Rutland #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET) 219a563f759SSuzuki K Poulose 220793d5d92SMarc Zyngier #define TCR_EPD0_SHIFT 7 221793d5d92SMarc Zyngier #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT) 222a563f759SSuzuki K Poulose #define TCR_IRGN0_SHIFT 8 223a563f759SSuzuki K Poulose #define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT) 224a563f759SSuzuki K Poulose #define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT) 225a563f759SSuzuki K Poulose #define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT) 226a563f759SSuzuki K Poulose #define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT) 227a563f759SSuzuki K Poulose #define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT) 228a563f759SSuzuki K Poulose 229793d5d92SMarc Zyngier #define TCR_EPD1_SHIFT 23 230793d5d92SMarc Zyngier #define TCR_EPD1_MASK (UL(1) << TCR_EPD1_SHIFT) 231a563f759SSuzuki K Poulose #define TCR_IRGN1_SHIFT 24 232a563f759SSuzuki K Poulose #define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT) 233a563f759SSuzuki K Poulose #define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT) 234a563f759SSuzuki K Poulose #define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT) 235a563f759SSuzuki K Poulose #define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT) 236a563f759SSuzuki K Poulose #define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT) 237a563f759SSuzuki K Poulose 238a563f759SSuzuki K Poulose #define TCR_IRGN_NC (TCR_IRGN0_NC | TCR_IRGN1_NC) 239a563f759SSuzuki K Poulose #define TCR_IRGN_WBWA (TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) 240a563f759SSuzuki K Poulose #define TCR_IRGN_WT (TCR_IRGN0_WT | TCR_IRGN1_WT) 241a563f759SSuzuki K Poulose #define TCR_IRGN_WBnWA (TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA) 242a563f759SSuzuki K Poulose #define TCR_IRGN_MASK (TCR_IRGN0_MASK | TCR_IRGN1_MASK) 243a563f759SSuzuki K Poulose 244a563f759SSuzuki K Poulose 245a563f759SSuzuki K Poulose #define TCR_ORGN0_SHIFT 10 246a563f759SSuzuki K Poulose #define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT) 247a563f759SSuzuki K Poulose #define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT) 248a563f759SSuzuki K Poulose #define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT) 249a563f759SSuzuki K Poulose #define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT) 250a563f759SSuzuki K Poulose #define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT) 251a563f759SSuzuki K Poulose 252a563f759SSuzuki K Poulose #define TCR_ORGN1_SHIFT 26 253a563f759SSuzuki K Poulose #define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT) 254a563f759SSuzuki K Poulose #define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT) 255a563f759SSuzuki K Poulose #define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT) 256a563f759SSuzuki K Poulose #define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT) 257a563f759SSuzuki K Poulose #define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT) 258a563f759SSuzuki K Poulose 259a563f759SSuzuki K Poulose #define TCR_ORGN_NC (TCR_ORGN0_NC | TCR_ORGN1_NC) 260a563f759SSuzuki K Poulose #define TCR_ORGN_WBWA (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA) 261a563f759SSuzuki K Poulose #define TCR_ORGN_WT (TCR_ORGN0_WT | TCR_ORGN1_WT) 262a563f759SSuzuki K Poulose #define TCR_ORGN_WBnWA (TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA) 263a563f759SSuzuki K Poulose #define TCR_ORGN_MASK (TCR_ORGN0_MASK | TCR_ORGN1_MASK) 264a563f759SSuzuki K Poulose 265a563f759SSuzuki K Poulose #define TCR_SH0_SHIFT 12 266a563f759SSuzuki K Poulose #define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT) 267a563f759SSuzuki K Poulose #define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT) 268a563f759SSuzuki K Poulose 269a563f759SSuzuki K Poulose #define TCR_SH1_SHIFT 28 270a563f759SSuzuki K Poulose #define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT) 271a563f759SSuzuki K Poulose #define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT) 272a563f759SSuzuki K Poulose #define TCR_SHARED (TCR_SH0_INNER | TCR_SH1_INNER) 273a563f759SSuzuki K Poulose 274a563f759SSuzuki K Poulose #define TCR_TG0_SHIFT 14 275a563f759SSuzuki K Poulose #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT) 276a563f759SSuzuki K Poulose #define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT) 277a563f759SSuzuki K Poulose #define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT) 278a563f759SSuzuki K Poulose #define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT) 279a563f759SSuzuki K Poulose 280a563f759SSuzuki K Poulose #define TCR_TG1_SHIFT 30 281a563f759SSuzuki K Poulose #define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT) 282a563f759SSuzuki K Poulose #define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT) 283a563f759SSuzuki K Poulose #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) 284a563f759SSuzuki K Poulose #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) 285a563f759SSuzuki K Poulose 286787fd1d0SKristina Martsenko #define TCR_IPS_SHIFT 32 287787fd1d0SKristina Martsenko #define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT) 2887655abb9SWill Deacon #define TCR_A1 (UL(1) << 22) 2894f04d8f0SCatalin Marinas #define TCR_ASID16 (UL(1) << 36) 290d50240a5SWill Deacon #define TCR_TBI0 (UL(1) << 37) 29121696c16SAndrey Konovalov #define TCR_TBI1 (UL(1) << 38) 2922f4b829cSCatalin Marinas #define TCR_HA (UL(1) << 39) 2932f4b829cSCatalin Marinas #define TCR_HD (UL(1) << 40) 2943e32131aSZhang Lei #define TCR_NFD0 (UL(1) << 53) 295e03e61c3SWill Deacon #define TCR_NFD1 (UL(1) << 54) 2963e6c69a0SMark Brown #define TCR_E0PD0 (UL(1) << 55) 2973e6c69a0SMark Brown #define TCR_E0PD1 (UL(1) << 56) 2984f04d8f0SCatalin Marinas 299529c4b05SKristina Martsenko /* 300529c4b05SKristina Martsenko * TTBR. 301529c4b05SKristina Martsenko */ 302529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 303529c4b05SKristina Martsenko /* 304529c4b05SKristina Martsenko * This should be GENMASK_ULL(47, 2). 305529c4b05SKristina Martsenko * TTBR_ELx[1] is RES0 in this configuration. 306529c4b05SKristina Martsenko */ 307529c4b05SKristina Martsenko #define TTBR_BADDR_MASK_52 (((UL(1) << 46) - 1) << 2) 308529c4b05SKristina Martsenko #endif 309529c4b05SKristina Martsenko 310b6d00d47SSteve Capper #ifdef CONFIG_ARM64_VA_BITS_52 311e842dfb5SSteve Capper /* Must be at least 64-byte aligned to prevent corruption of the TTBR */ 312e842dfb5SSteve Capper #define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \ 313e842dfb5SSteve Capper (UL(1) << (48 - PGDIR_SHIFT))) * 8) 314e842dfb5SSteve Capper #endif 315e842dfb5SSteve Capper 3164f04d8f0SCatalin Marinas #endif 317