14f04d8f0SCatalin Marinas /* 24f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 34f04d8f0SCatalin Marinas * 44f04d8f0SCatalin Marinas * This program is free software; you can redistribute it and/or modify 54f04d8f0SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 64f04d8f0SCatalin Marinas * published by the Free Software Foundation. 74f04d8f0SCatalin Marinas * 84f04d8f0SCatalin Marinas * This program is distributed in the hope that it will be useful, 94f04d8f0SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 104f04d8f0SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 114f04d8f0SCatalin Marinas * GNU General Public License for more details. 124f04d8f0SCatalin Marinas * 134f04d8f0SCatalin Marinas * You should have received a copy of the GNU General Public License 144f04d8f0SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 154f04d8f0SCatalin Marinas */ 164f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_HWDEF_H 174f04d8f0SCatalin Marinas #define __ASM_PGTABLE_HWDEF_H 184f04d8f0SCatalin Marinas 196b4fee24SCatalin Marinas #define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3)) 206b4fee24SCatalin Marinas 216b4fee24SCatalin Marinas /* 226b4fee24SCatalin Marinas * PMD_SHIFT determines the size a level 2 page table entry can map. 236b4fee24SCatalin Marinas */ 246b4fee24SCatalin Marinas #if CONFIG_ARM64_PGTABLE_LEVELS > 2 256b4fee24SCatalin Marinas #define PMD_SHIFT ((PAGE_SHIFT - 3) * 2 + 3) 266b4fee24SCatalin Marinas #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT) 276b4fee24SCatalin Marinas #define PMD_MASK (~(PMD_SIZE-1)) 286b4fee24SCatalin Marinas #define PTRS_PER_PMD PTRS_PER_PTE 294f04d8f0SCatalin Marinas #endif 304f04d8f0SCatalin Marinas 314f04d8f0SCatalin Marinas /* 326b4fee24SCatalin Marinas * PUD_SHIFT determines the size a level 1 page table entry can map. 336b4fee24SCatalin Marinas */ 346b4fee24SCatalin Marinas #if CONFIG_ARM64_PGTABLE_LEVELS > 3 356b4fee24SCatalin Marinas #define PUD_SHIFT ((PAGE_SHIFT - 3) * 3 + 3) 366b4fee24SCatalin Marinas #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT) 376b4fee24SCatalin Marinas #define PUD_MASK (~(PUD_SIZE-1)) 386b4fee24SCatalin Marinas #define PTRS_PER_PUD PTRS_PER_PTE 396b4fee24SCatalin Marinas #endif 406b4fee24SCatalin Marinas 416b4fee24SCatalin Marinas /* 426b4fee24SCatalin Marinas * PGDIR_SHIFT determines the size a top-level page table entry can map 436b4fee24SCatalin Marinas * (depending on the configuration, this level can be 0, 1 or 2). 446b4fee24SCatalin Marinas */ 456b4fee24SCatalin Marinas #define PGDIR_SHIFT ((PAGE_SHIFT - 3) * CONFIG_ARM64_PGTABLE_LEVELS + 3) 466b4fee24SCatalin Marinas #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) 476b4fee24SCatalin Marinas #define PGDIR_MASK (~(PGDIR_SIZE-1)) 486b4fee24SCatalin Marinas #define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT)) 496b4fee24SCatalin Marinas 506b4fee24SCatalin Marinas /* 516b4fee24SCatalin Marinas * Section address mask and size definitions. 526b4fee24SCatalin Marinas */ 536b4fee24SCatalin Marinas #define SECTION_SHIFT PMD_SHIFT 546b4fee24SCatalin Marinas #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT) 556b4fee24SCatalin Marinas #define SECTION_MASK (~(SECTION_SIZE-1)) 566b4fee24SCatalin Marinas 576b4fee24SCatalin Marinas /* 584f04d8f0SCatalin Marinas * Hardware page table definitions. 594f04d8f0SCatalin Marinas * 60084bd298SSteve Capper * Level 1 descriptor (PUD). 61084bd298SSteve Capper */ 62c79b954bSJungseok Lee #define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0) 63084bd298SSteve Capper #define PUD_TABLE_BIT (_AT(pgdval_t, 1) << 1) 64206a2a73SSteve Capper #define PUD_TYPE_MASK (_AT(pgdval_t, 3) << 0) 65206a2a73SSteve Capper #define PUD_TYPE_SECT (_AT(pgdval_t, 1) << 0) 66084bd298SSteve Capper 67084bd298SSteve Capper /* 684f04d8f0SCatalin Marinas * Level 2 descriptor (PMD). 694f04d8f0SCatalin Marinas */ 704f04d8f0SCatalin Marinas #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 714f04d8f0SCatalin Marinas #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 724f04d8f0SCatalin Marinas #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 734f04d8f0SCatalin Marinas #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 74084bd298SSteve Capper #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 754f04d8f0SCatalin Marinas 764f04d8f0SCatalin Marinas /* 774f04d8f0SCatalin Marinas * Section 784f04d8f0SCatalin Marinas */ 79af074848SSteve Capper #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 80db4ed53cSSteve Capper #define PMD_SECT_PROT_NONE (_AT(pmdval_t, 1) << 58) 81af074848SSteve Capper #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 82af074848SSteve Capper #define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */ 834f04d8f0SCatalin Marinas #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 844f04d8f0SCatalin Marinas #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 854f04d8f0SCatalin Marinas #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 868e620b04SCatalin Marinas #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 878e620b04SCatalin Marinas #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) 884f04d8f0SCatalin Marinas 894f04d8f0SCatalin Marinas /* 904f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 914f04d8f0SCatalin Marinas */ 924f04d8f0SCatalin Marinas #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) 934f04d8f0SCatalin Marinas #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) 944f04d8f0SCatalin Marinas 954f04d8f0SCatalin Marinas /* 964f04d8f0SCatalin Marinas * Level 3 descriptor (PTE). 974f04d8f0SCatalin Marinas */ 984f04d8f0SCatalin Marinas #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 994f04d8f0SCatalin Marinas #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 1004f04d8f0SCatalin Marinas #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 101084bd298SSteve Capper #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 1024f04d8f0SCatalin Marinas #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 1034f04d8f0SCatalin Marinas #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 1044f04d8f0SCatalin Marinas #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 1054f04d8f0SCatalin Marinas #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 1064f04d8f0SCatalin Marinas #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 1078e620b04SCatalin Marinas #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ 1088e620b04SCatalin Marinas #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ 1094f04d8f0SCatalin Marinas 1104f04d8f0SCatalin Marinas /* 1114f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 1124f04d8f0SCatalin Marinas */ 1134f04d8f0SCatalin Marinas #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) 1144f04d8f0SCatalin Marinas #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) 1154f04d8f0SCatalin Marinas 1164f04d8f0SCatalin Marinas /* 11736311607SMarc Zyngier * 2nd stage PTE definitions 11836311607SMarc Zyngier */ 11936311607SMarc Zyngier #define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */ 12036311607SMarc Zyngier #define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */ 12136311607SMarc Zyngier 122ad361f09SChristoffer Dall #define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */ 123ad361f09SChristoffer Dall 12436311607SMarc Zyngier /* 12536311607SMarc Zyngier * Memory Attribute override for Stage-2 (MemAttr[3:0]) 12636311607SMarc Zyngier */ 12736311607SMarc Zyngier #define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2) 12836311607SMarc Zyngier #define PTE_S2_MEMATTR_MASK (_AT(pteval_t, 0xf) << 2) 12936311607SMarc Zyngier 13036311607SMarc Zyngier /* 13136311607SMarc Zyngier * EL2/HYP PTE/PMD definitions 13236311607SMarc Zyngier */ 13336311607SMarc Zyngier #define PMD_HYP PMD_SECT_USER 13436311607SMarc Zyngier #define PTE_HYP PTE_USER 13536311607SMarc Zyngier 13636311607SMarc Zyngier /* 13787366d8cSRadha Mohan Chintakuntla * Highest possible physical address supported. 1384f04d8f0SCatalin Marinas */ 13987366d8cSRadha Mohan Chintakuntla #define PHYS_MASK_SHIFT (48) 1404f04d8f0SCatalin Marinas #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) 1414f04d8f0SCatalin Marinas 1424f04d8f0SCatalin Marinas /* 1434f04d8f0SCatalin Marinas * TCR flags. 1444f04d8f0SCatalin Marinas */ 1454f04d8f0SCatalin Marinas #define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0)) 1464f04d8f0SCatalin Marinas #define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24)) 1474f04d8f0SCatalin Marinas #define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24)) 1484f04d8f0SCatalin Marinas #define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24)) 1494f04d8f0SCatalin Marinas #define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24)) 1504f04d8f0SCatalin Marinas #define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24)) 1514f04d8f0SCatalin Marinas #define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26)) 1524f04d8f0SCatalin Marinas #define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26)) 1534f04d8f0SCatalin Marinas #define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26)) 1544f04d8f0SCatalin Marinas #define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26)) 1554f04d8f0SCatalin Marinas #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26)) 1564f04d8f0SCatalin Marinas #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28)) 15735a86976SCatalin Marinas #define TCR_TG0_4K (UL(0) << 14) 1584f04d8f0SCatalin Marinas #define TCR_TG0_64K (UL(1) << 14) 15935a86976SCatalin Marinas #define TCR_TG0_16K (UL(2) << 14) 16035a86976SCatalin Marinas #define TCR_TG1_16K (UL(1) << 30) 16135a86976SCatalin Marinas #define TCR_TG1_4K (UL(2) << 30) 16235a86976SCatalin Marinas #define TCR_TG1_64K (UL(3) << 30) 1634f04d8f0SCatalin Marinas #define TCR_ASID16 (UL(1) << 36) 164d50240a5SWill Deacon #define TCR_TBI0 (UL(1) << 37) 1654f04d8f0SCatalin Marinas 1664f04d8f0SCatalin Marinas #endif 167