14f04d8f0SCatalin Marinas /* 24f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 34f04d8f0SCatalin Marinas * 44f04d8f0SCatalin Marinas * This program is free software; you can redistribute it and/or modify 54f04d8f0SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 64f04d8f0SCatalin Marinas * published by the Free Software Foundation. 74f04d8f0SCatalin Marinas * 84f04d8f0SCatalin Marinas * This program is distributed in the hope that it will be useful, 94f04d8f0SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 104f04d8f0SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 114f04d8f0SCatalin Marinas * GNU General Public License for more details. 124f04d8f0SCatalin Marinas * 134f04d8f0SCatalin Marinas * You should have received a copy of the GNU General Public License 144f04d8f0SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 154f04d8f0SCatalin Marinas */ 164f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_HWDEF_H 174f04d8f0SCatalin Marinas #define __ASM_PGTABLE_HWDEF_H 184f04d8f0SCatalin Marinas 19529c4b05SKristina Martsenko #include <asm/memory.h> 20529c4b05SKristina Martsenko 21686e7838SSuzuki K. Poulose /* 22686e7838SSuzuki K. Poulose * Number of page-table levels required to address 'va_bits' wide 23686e7838SSuzuki K. Poulose * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT) 24686e7838SSuzuki K. Poulose * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence: 25686e7838SSuzuki K. Poulose * 26686e7838SSuzuki K. Poulose * levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3)) 27686e7838SSuzuki K. Poulose * 28686e7838SSuzuki K. Poulose * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d)) 29686e7838SSuzuki K. Poulose * 30686e7838SSuzuki K. Poulose * We cannot include linux/kernel.h which defines DIV_ROUND_UP here 31686e7838SSuzuki K. Poulose * due to build issues. So we open code DIV_ROUND_UP here: 32686e7838SSuzuki K. Poulose * 33686e7838SSuzuki K. Poulose * ((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3)) 34686e7838SSuzuki K. Poulose * 35686e7838SSuzuki K. Poulose * which gets simplified as : 36686e7838SSuzuki K. Poulose */ 37686e7838SSuzuki K. Poulose #define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3)) 38686e7838SSuzuki K. Poulose 39686e7838SSuzuki K. Poulose /* 40686e7838SSuzuki K. Poulose * Size mapped by an entry at level n ( 0 <= n <= 3) 41686e7838SSuzuki K. Poulose * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits 42686e7838SSuzuki K. Poulose * in the final page. The maximum number of translation levels supported by 43686e7838SSuzuki K. Poulose * the architecture is 4. Hence, starting at at level n, we have further 44686e7838SSuzuki K. Poulose * ((4 - n) - 1) levels of translation excluding the offset within the page. 45686e7838SSuzuki K. Poulose * So, the total number of bits mapped by an entry at level n is : 46686e7838SSuzuki K. Poulose * 47686e7838SSuzuki K. Poulose * ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT 48686e7838SSuzuki K. Poulose * 49686e7838SSuzuki K. Poulose * Rearranging it a bit we get : 50686e7838SSuzuki K. Poulose * (4 - n) * (PAGE_SHIFT - 3) + 3 51686e7838SSuzuki K. Poulose */ 52686e7838SSuzuki K. Poulose #define ARM64_HW_PGTABLE_LEVEL_SHIFT(n) ((PAGE_SHIFT - 3) * (4 - (n)) + 3) 53686e7838SSuzuki K. Poulose 546b4fee24SCatalin Marinas #define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3)) 556b4fee24SCatalin Marinas 566b4fee24SCatalin Marinas /* 576b4fee24SCatalin Marinas * PMD_SHIFT determines the size a level 2 page table entry can map. 586b4fee24SCatalin Marinas */ 599f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 60686e7838SSuzuki K. Poulose #define PMD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(2) 616b4fee24SCatalin Marinas #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT) 626b4fee24SCatalin Marinas #define PMD_MASK (~(PMD_SIZE-1)) 636b4fee24SCatalin Marinas #define PTRS_PER_PMD PTRS_PER_PTE 644f04d8f0SCatalin Marinas #endif 654f04d8f0SCatalin Marinas 664f04d8f0SCatalin Marinas /* 676b4fee24SCatalin Marinas * PUD_SHIFT determines the size a level 1 page table entry can map. 686b4fee24SCatalin Marinas */ 699f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 70686e7838SSuzuki K. Poulose #define PUD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(1) 716b4fee24SCatalin Marinas #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT) 726b4fee24SCatalin Marinas #define PUD_MASK (~(PUD_SIZE-1)) 736b4fee24SCatalin Marinas #define PTRS_PER_PUD PTRS_PER_PTE 746b4fee24SCatalin Marinas #endif 756b4fee24SCatalin Marinas 766b4fee24SCatalin Marinas /* 776b4fee24SCatalin Marinas * PGDIR_SHIFT determines the size a top-level page table entry can map 786b4fee24SCatalin Marinas * (depending on the configuration, this level can be 0, 1 or 2). 796b4fee24SCatalin Marinas */ 80686e7838SSuzuki K. Poulose #define PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS) 816b4fee24SCatalin Marinas #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) 826b4fee24SCatalin Marinas #define PGDIR_MASK (~(PGDIR_SIZE-1)) 8368d23da4SWill Deacon #ifdef CONFIG_ARM64_USER_VA_BITS_52 84e842dfb5SSteve Capper #define PTRS_PER_PGD (1 << (52 - PGDIR_SHIFT)) 85e842dfb5SSteve Capper #else 866b4fee24SCatalin Marinas #define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT)) 87e842dfb5SSteve Capper #endif 886b4fee24SCatalin Marinas 896b4fee24SCatalin Marinas /* 906b4fee24SCatalin Marinas * Section address mask and size definitions. 916b4fee24SCatalin Marinas */ 926b4fee24SCatalin Marinas #define SECTION_SHIFT PMD_SHIFT 936b4fee24SCatalin Marinas #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT) 946b4fee24SCatalin Marinas #define SECTION_MASK (~(SECTION_SIZE-1)) 956b4fee24SCatalin Marinas 966b4fee24SCatalin Marinas /* 97ecf35a23SJeremy Linton * Contiguous page definitions. 98ecf35a23SJeremy Linton */ 9966b3923aSDavid Woods #ifdef CONFIG_ARM64_64K_PAGES 10066b3923aSDavid Woods #define CONT_PTE_SHIFT 5 10166b3923aSDavid Woods #define CONT_PMD_SHIFT 5 10266b3923aSDavid Woods #elif defined(CONFIG_ARM64_16K_PAGES) 10366b3923aSDavid Woods #define CONT_PTE_SHIFT 7 10466b3923aSDavid Woods #define CONT_PMD_SHIFT 5 10566b3923aSDavid Woods #else 10666b3923aSDavid Woods #define CONT_PTE_SHIFT 4 10766b3923aSDavid Woods #define CONT_PMD_SHIFT 4 10866b3923aSDavid Woods #endif 10966b3923aSDavid Woods 11066b3923aSDavid Woods #define CONT_PTES (1 << CONT_PTE_SHIFT) 11166b3923aSDavid Woods #define CONT_PTE_SIZE (CONT_PTES * PAGE_SIZE) 11266b3923aSDavid Woods #define CONT_PTE_MASK (~(CONT_PTE_SIZE - 1)) 11366b3923aSDavid Woods #define CONT_PMDS (1 << CONT_PMD_SHIFT) 11466b3923aSDavid Woods #define CONT_PMD_SIZE (CONT_PMDS * PMD_SIZE) 11566b3923aSDavid Woods #define CONT_PMD_MASK (~(CONT_PMD_SIZE - 1)) 116ecf35a23SJeremy Linton /* the the numerical offset of the PTE within a range of CONT_PTES */ 117ecf35a23SJeremy Linton #define CONT_RANGE_OFFSET(addr) (((addr)>>PAGE_SHIFT)&(CONT_PTES-1)) 118ecf35a23SJeremy Linton 119ecf35a23SJeremy Linton /* 1204f04d8f0SCatalin Marinas * Hardware page table definitions. 1214f04d8f0SCatalin Marinas * 122084bd298SSteve Capper * Level 1 descriptor (PUD). 123084bd298SSteve Capper */ 124c79b954bSJungseok Lee #define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0) 12529d9bef1SPunit Agrawal #define PUD_TABLE_BIT (_AT(pudval_t, 1) << 1) 12629d9bef1SPunit Agrawal #define PUD_TYPE_MASK (_AT(pudval_t, 3) << 0) 12729d9bef1SPunit Agrawal #define PUD_TYPE_SECT (_AT(pudval_t, 1) << 0) 128084bd298SSteve Capper 129084bd298SSteve Capper /* 1304f04d8f0SCatalin Marinas * Level 2 descriptor (PMD). 1314f04d8f0SCatalin Marinas */ 1324f04d8f0SCatalin Marinas #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 1334f04d8f0SCatalin Marinas #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 1344f04d8f0SCatalin Marinas #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 1354f04d8f0SCatalin Marinas #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 136084bd298SSteve Capper #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 1374f04d8f0SCatalin Marinas 1384f04d8f0SCatalin Marinas /* 1394f04d8f0SCatalin Marinas * Section 1404f04d8f0SCatalin Marinas */ 141af074848SSteve Capper #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 142af074848SSteve Capper #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 143af074848SSteve Capper #define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */ 1444f04d8f0SCatalin Marinas #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 1454f04d8f0SCatalin Marinas #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 1464f04d8f0SCatalin Marinas #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 147ecf35a23SJeremy Linton #define PMD_SECT_CONT (_AT(pmdval_t, 1) << 52) 1488e620b04SCatalin Marinas #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 1498e620b04SCatalin Marinas #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) 1504f04d8f0SCatalin Marinas 1514f04d8f0SCatalin Marinas /* 1524f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 1534f04d8f0SCatalin Marinas */ 1544f04d8f0SCatalin Marinas #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) 1554f04d8f0SCatalin Marinas #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) 1564f04d8f0SCatalin Marinas 1574f04d8f0SCatalin Marinas /* 1584f04d8f0SCatalin Marinas * Level 3 descriptor (PTE). 1594f04d8f0SCatalin Marinas */ 1604f04d8f0SCatalin Marinas #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 1614f04d8f0SCatalin Marinas #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 1624f04d8f0SCatalin Marinas #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 163084bd298SSteve Capper #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 1644f04d8f0SCatalin Marinas #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 1654f04d8f0SCatalin Marinas #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 1664f04d8f0SCatalin Marinas #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 1674f04d8f0SCatalin Marinas #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 1684f04d8f0SCatalin Marinas #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 1692f4b829cSCatalin Marinas #define PTE_DBM (_AT(pteval_t, 1) << 51) /* Dirty Bit Management */ 170ecf35a23SJeremy Linton #define PTE_CONT (_AT(pteval_t, 1) << 52) /* Contiguous range */ 1718e620b04SCatalin Marinas #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ 1728e620b04SCatalin Marinas #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ 1731166f3feSMarc Zyngier #define PTE_HYP_XN (_AT(pteval_t, 1) << 54) /* HYP XN */ 1744f04d8f0SCatalin Marinas 175e6d588a8SKristina Martsenko #define PTE_ADDR_LOW (((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT) 17675387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 177e6d588a8SKristina Martsenko #define PTE_ADDR_HIGH (_AT(pteval_t, 0xf) << 12) 17875387b92SKristina Martsenko #define PTE_ADDR_MASK (PTE_ADDR_LOW | PTE_ADDR_HIGH) 17975387b92SKristina Martsenko #else 18075387b92SKristina Martsenko #define PTE_ADDR_MASK PTE_ADDR_LOW 181e6d588a8SKristina Martsenko #endif 182e6d588a8SKristina Martsenko 1834f04d8f0SCatalin Marinas /* 1844f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 1854f04d8f0SCatalin Marinas */ 1864f04d8f0SCatalin Marinas #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) 1874f04d8f0SCatalin Marinas #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) 1884f04d8f0SCatalin Marinas 1894f04d8f0SCatalin Marinas /* 19036311607SMarc Zyngier * 2nd stage PTE definitions 19136311607SMarc Zyngier */ 19236311607SMarc Zyngier #define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */ 19336311607SMarc Zyngier #define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */ 194fefb876bSMarc Zyngier #define PTE_S2_XN (_AT(pteval_t, 2) << 53) /* XN[1:0] */ 19536311607SMarc Zyngier 1968199ed0eSMario Smarduch #define PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[2:1] */ 197ad361f09SChristoffer Dall #define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */ 198fefb876bSMarc Zyngier #define PMD_S2_XN (_AT(pmdval_t, 2) << 53) /* XN[1:0] */ 199ad361f09SChristoffer Dall 20036311607SMarc Zyngier /* 20136311607SMarc Zyngier * Memory Attribute override for Stage-2 (MemAttr[3:0]) 20236311607SMarc Zyngier */ 20336311607SMarc Zyngier #define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2) 20436311607SMarc Zyngier #define PTE_S2_MEMATTR_MASK (_AT(pteval_t, 0xf) << 2) 20536311607SMarc Zyngier 20636311607SMarc Zyngier /* 20736311607SMarc Zyngier * EL2/HYP PTE/PMD definitions 20836311607SMarc Zyngier */ 20936311607SMarc Zyngier #define PMD_HYP PMD_SECT_USER 21036311607SMarc Zyngier #define PTE_HYP PTE_USER 21136311607SMarc Zyngier 21236311607SMarc Zyngier /* 21387366d8cSRadha Mohan Chintakuntla * Highest possible physical address supported. 2144f04d8f0SCatalin Marinas */ 215982aa7c5SKristina Martsenko #define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS) 2164f04d8f0SCatalin Marinas #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) 2174f04d8f0SCatalin Marinas 2185ffdfaedSVladimir Murzin #define TTBR_CNP_BIT (UL(1) << 0) 2195ffdfaedSVladimir Murzin 2204f04d8f0SCatalin Marinas /* 2214f04d8f0SCatalin Marinas * TCR flags. 2224f04d8f0SCatalin Marinas */ 223dd006da2SArd Biesheuvel #define TCR_T0SZ_OFFSET 0 224dd006da2SArd Biesheuvel #define TCR_T1SZ_OFFSET 16 225dd006da2SArd Biesheuvel #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET) 226dd006da2SArd Biesheuvel #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET) 227dd006da2SArd Biesheuvel #define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) 228dd006da2SArd Biesheuvel #define TCR_TxSZ_WIDTH 6 229adf75899SMark Rutland #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET) 230a563f759SSuzuki K Poulose 231a563f759SSuzuki K Poulose #define TCR_IRGN0_SHIFT 8 232a563f759SSuzuki K Poulose #define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT) 233a563f759SSuzuki K Poulose #define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT) 234a563f759SSuzuki K Poulose #define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT) 235a563f759SSuzuki K Poulose #define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT) 236a563f759SSuzuki K Poulose #define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT) 237a563f759SSuzuki K Poulose 238a563f759SSuzuki K Poulose #define TCR_IRGN1_SHIFT 24 239a563f759SSuzuki K Poulose #define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT) 240a563f759SSuzuki K Poulose #define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT) 241a563f759SSuzuki K Poulose #define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT) 242a563f759SSuzuki K Poulose #define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT) 243a563f759SSuzuki K Poulose #define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT) 244a563f759SSuzuki K Poulose 245a563f759SSuzuki K Poulose #define TCR_IRGN_NC (TCR_IRGN0_NC | TCR_IRGN1_NC) 246a563f759SSuzuki K Poulose #define TCR_IRGN_WBWA (TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) 247a563f759SSuzuki K Poulose #define TCR_IRGN_WT (TCR_IRGN0_WT | TCR_IRGN1_WT) 248a563f759SSuzuki K Poulose #define TCR_IRGN_WBnWA (TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA) 249a563f759SSuzuki K Poulose #define TCR_IRGN_MASK (TCR_IRGN0_MASK | TCR_IRGN1_MASK) 250a563f759SSuzuki K Poulose 251a563f759SSuzuki K Poulose 252a563f759SSuzuki K Poulose #define TCR_ORGN0_SHIFT 10 253a563f759SSuzuki K Poulose #define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT) 254a563f759SSuzuki K Poulose #define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT) 255a563f759SSuzuki K Poulose #define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT) 256a563f759SSuzuki K Poulose #define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT) 257a563f759SSuzuki K Poulose #define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT) 258a563f759SSuzuki K Poulose 259a563f759SSuzuki K Poulose #define TCR_ORGN1_SHIFT 26 260a563f759SSuzuki K Poulose #define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT) 261a563f759SSuzuki K Poulose #define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT) 262a563f759SSuzuki K Poulose #define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT) 263a563f759SSuzuki K Poulose #define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT) 264a563f759SSuzuki K Poulose #define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT) 265a563f759SSuzuki K Poulose 266a563f759SSuzuki K Poulose #define TCR_ORGN_NC (TCR_ORGN0_NC | TCR_ORGN1_NC) 267a563f759SSuzuki K Poulose #define TCR_ORGN_WBWA (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA) 268a563f759SSuzuki K Poulose #define TCR_ORGN_WT (TCR_ORGN0_WT | TCR_ORGN1_WT) 269a563f759SSuzuki K Poulose #define TCR_ORGN_WBnWA (TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA) 270a563f759SSuzuki K Poulose #define TCR_ORGN_MASK (TCR_ORGN0_MASK | TCR_ORGN1_MASK) 271a563f759SSuzuki K Poulose 272a563f759SSuzuki K Poulose #define TCR_SH0_SHIFT 12 273a563f759SSuzuki K Poulose #define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT) 274a563f759SSuzuki K Poulose #define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT) 275a563f759SSuzuki K Poulose 276a563f759SSuzuki K Poulose #define TCR_SH1_SHIFT 28 277a563f759SSuzuki K Poulose #define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT) 278a563f759SSuzuki K Poulose #define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT) 279a563f759SSuzuki K Poulose #define TCR_SHARED (TCR_SH0_INNER | TCR_SH1_INNER) 280a563f759SSuzuki K Poulose 281a563f759SSuzuki K Poulose #define TCR_TG0_SHIFT 14 282a563f759SSuzuki K Poulose #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT) 283a563f759SSuzuki K Poulose #define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT) 284a563f759SSuzuki K Poulose #define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT) 285a563f759SSuzuki K Poulose #define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT) 286a563f759SSuzuki K Poulose 287a563f759SSuzuki K Poulose #define TCR_TG1_SHIFT 30 288a563f759SSuzuki K Poulose #define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT) 289a563f759SSuzuki K Poulose #define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT) 290a563f759SSuzuki K Poulose #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) 291a563f759SSuzuki K Poulose #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) 292a563f759SSuzuki K Poulose 293787fd1d0SKristina Martsenko #define TCR_IPS_SHIFT 32 294787fd1d0SKristina Martsenko #define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT) 2957655abb9SWill Deacon #define TCR_A1 (UL(1) << 22) 2964f04d8f0SCatalin Marinas #define TCR_ASID16 (UL(1) << 36) 297d50240a5SWill Deacon #define TCR_TBI0 (UL(1) << 37) 2982f4b829cSCatalin Marinas #define TCR_HA (UL(1) << 39) 2992f4b829cSCatalin Marinas #define TCR_HD (UL(1) << 40) 300e03e61c3SWill Deacon #define TCR_NFD1 (UL(1) << 54) 3014f04d8f0SCatalin Marinas 302529c4b05SKristina Martsenko /* 303529c4b05SKristina Martsenko * TTBR. 304529c4b05SKristina Martsenko */ 305529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 306529c4b05SKristina Martsenko /* 307529c4b05SKristina Martsenko * This should be GENMASK_ULL(47, 2). 308529c4b05SKristina Martsenko * TTBR_ELx[1] is RES0 in this configuration. 309529c4b05SKristina Martsenko */ 310529c4b05SKristina Martsenko #define TTBR_BADDR_MASK_52 (((UL(1) << 46) - 1) << 2) 311529c4b05SKristina Martsenko #endif 312529c4b05SKristina Martsenko 31368d23da4SWill Deacon #ifdef CONFIG_ARM64_USER_VA_BITS_52 314e842dfb5SSteve Capper /* Must be at least 64-byte aligned to prevent corruption of the TTBR */ 315e842dfb5SSteve Capper #define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \ 316e842dfb5SSteve Capper (UL(1) << (48 - PGDIR_SHIFT))) * 8) 317e842dfb5SSteve Capper #endif 318e842dfb5SSteve Capper 3194f04d8f0SCatalin Marinas #endif 320