14f04d8f0SCatalin Marinas /* 24f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 34f04d8f0SCatalin Marinas * 44f04d8f0SCatalin Marinas * This program is free software; you can redistribute it and/or modify 54f04d8f0SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 64f04d8f0SCatalin Marinas * published by the Free Software Foundation. 74f04d8f0SCatalin Marinas * 84f04d8f0SCatalin Marinas * This program is distributed in the hope that it will be useful, 94f04d8f0SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 104f04d8f0SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 114f04d8f0SCatalin Marinas * GNU General Public License for more details. 124f04d8f0SCatalin Marinas * 134f04d8f0SCatalin Marinas * You should have received a copy of the GNU General Public License 144f04d8f0SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 154f04d8f0SCatalin Marinas */ 164f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_HWDEF_H 174f04d8f0SCatalin Marinas #define __ASM_PGTABLE_HWDEF_H 184f04d8f0SCatalin Marinas 194f04d8f0SCatalin Marinas #ifdef CONFIG_ARM64_64K_PAGES 204f04d8f0SCatalin Marinas #include <asm/pgtable-2level-hwdef.h> 214f04d8f0SCatalin Marinas #else 224f04d8f0SCatalin Marinas #include <asm/pgtable-3level-hwdef.h> 234f04d8f0SCatalin Marinas #endif 244f04d8f0SCatalin Marinas 254f04d8f0SCatalin Marinas /* 264f04d8f0SCatalin Marinas * Hardware page table definitions. 274f04d8f0SCatalin Marinas * 28084bd298SSteve Capper * Level 1 descriptor (PUD). 29084bd298SSteve Capper */ 30084bd298SSteve Capper 31084bd298SSteve Capper #define PUD_TABLE_BIT (_AT(pgdval_t, 1) << 1) 32206a2a73SSteve Capper #define PUD_TYPE_MASK (_AT(pgdval_t, 3) << 0) 33206a2a73SSteve Capper #define PUD_TYPE_SECT (_AT(pgdval_t, 1) << 0) 34084bd298SSteve Capper 35084bd298SSteve Capper /* 364f04d8f0SCatalin Marinas * Level 2 descriptor (PMD). 374f04d8f0SCatalin Marinas */ 384f04d8f0SCatalin Marinas #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) 394f04d8f0SCatalin Marinas #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) 404f04d8f0SCatalin Marinas #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) 414f04d8f0SCatalin Marinas #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) 42084bd298SSteve Capper #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) 434f04d8f0SCatalin Marinas 444f04d8f0SCatalin Marinas /* 454f04d8f0SCatalin Marinas * Section 464f04d8f0SCatalin Marinas */ 47af074848SSteve Capper #define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 48db4ed53cSSteve Capper #define PMD_SECT_PROT_NONE (_AT(pmdval_t, 1) << 58) 49af074848SSteve Capper #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ 50af074848SSteve Capper #define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */ 514f04d8f0SCatalin Marinas #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) 524f04d8f0SCatalin Marinas #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) 534f04d8f0SCatalin Marinas #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) 548e620b04SCatalin Marinas #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) 558e620b04SCatalin Marinas #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) 564f04d8f0SCatalin Marinas 574f04d8f0SCatalin Marinas /* 584f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 594f04d8f0SCatalin Marinas */ 604f04d8f0SCatalin Marinas #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) 614f04d8f0SCatalin Marinas #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) 624f04d8f0SCatalin Marinas 634f04d8f0SCatalin Marinas /* 644f04d8f0SCatalin Marinas * Level 3 descriptor (PTE). 654f04d8f0SCatalin Marinas */ 664f04d8f0SCatalin Marinas #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) 674f04d8f0SCatalin Marinas #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) 684f04d8f0SCatalin Marinas #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) 69084bd298SSteve Capper #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) 704f04d8f0SCatalin Marinas #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 714f04d8f0SCatalin Marinas #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ 724f04d8f0SCatalin Marinas #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 734f04d8f0SCatalin Marinas #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ 744f04d8f0SCatalin Marinas #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ 758e620b04SCatalin Marinas #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ 768e620b04SCatalin Marinas #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ 774f04d8f0SCatalin Marinas 784f04d8f0SCatalin Marinas /* 794f04d8f0SCatalin Marinas * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 804f04d8f0SCatalin Marinas */ 814f04d8f0SCatalin Marinas #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) 824f04d8f0SCatalin Marinas #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) 834f04d8f0SCatalin Marinas 844f04d8f0SCatalin Marinas /* 8536311607SMarc Zyngier * 2nd stage PTE definitions 8636311607SMarc Zyngier */ 8736311607SMarc Zyngier #define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */ 8836311607SMarc Zyngier #define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */ 8936311607SMarc Zyngier 90ad361f09SChristoffer Dall #define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */ 91ad361f09SChristoffer Dall 9236311607SMarc Zyngier /* 9336311607SMarc Zyngier * Memory Attribute override for Stage-2 (MemAttr[3:0]) 9436311607SMarc Zyngier */ 9536311607SMarc Zyngier #define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2) 9636311607SMarc Zyngier #define PTE_S2_MEMATTR_MASK (_AT(pteval_t, 0xf) << 2) 9736311607SMarc Zyngier 9836311607SMarc Zyngier /* 9936311607SMarc Zyngier * EL2/HYP PTE/PMD definitions 10036311607SMarc Zyngier */ 10136311607SMarc Zyngier #define PMD_HYP PMD_SECT_USER 10236311607SMarc Zyngier #define PTE_HYP PTE_USER 10336311607SMarc Zyngier 10436311607SMarc Zyngier /* 10587366d8cSRadha Mohan Chintakuntla * Highest possible physical address supported. 1064f04d8f0SCatalin Marinas */ 10787366d8cSRadha Mohan Chintakuntla #define PHYS_MASK_SHIFT (48) 1084f04d8f0SCatalin Marinas #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) 1094f04d8f0SCatalin Marinas 1104f04d8f0SCatalin Marinas /* 1114f04d8f0SCatalin Marinas * TCR flags. 1124f04d8f0SCatalin Marinas */ 1134f04d8f0SCatalin Marinas #define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0)) 1144f04d8f0SCatalin Marinas #define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24)) 1154f04d8f0SCatalin Marinas #define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24)) 1164f04d8f0SCatalin Marinas #define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24)) 1174f04d8f0SCatalin Marinas #define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24)) 1184f04d8f0SCatalin Marinas #define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24)) 1194f04d8f0SCatalin Marinas #define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26)) 1204f04d8f0SCatalin Marinas #define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26)) 1214f04d8f0SCatalin Marinas #define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26)) 1224f04d8f0SCatalin Marinas #define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26)) 1234f04d8f0SCatalin Marinas #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26)) 1244f04d8f0SCatalin Marinas #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28)) 12535a86976SCatalin Marinas #define TCR_TG0_4K (UL(0) << 14) 1264f04d8f0SCatalin Marinas #define TCR_TG0_64K (UL(1) << 14) 12735a86976SCatalin Marinas #define TCR_TG0_16K (UL(2) << 14) 12835a86976SCatalin Marinas #define TCR_TG1_16K (UL(1) << 30) 12935a86976SCatalin Marinas #define TCR_TG1_4K (UL(2) << 30) 13035a86976SCatalin Marinas #define TCR_TG1_64K (UL(3) << 30) 1314f04d8f0SCatalin Marinas #define TCR_ASID16 (UL(1) << 36) 132d50240a5SWill Deacon #define TCR_TBI0 (UL(1) << 37) 1334f04d8f0SCatalin Marinas 1344f04d8f0SCatalin Marinas #endif 135