1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2012 ARM Ltd.
4  */
5 
6 #ifndef __ASM_PERF_EVENT_H
7 #define __ASM_PERF_EVENT_H
8 
9 #include <asm/stack_pointer.h>
10 #include <asm/ptrace.h>
11 
12 #define	ARMV8_PMU_MAX_COUNTERS	32
13 #define	ARMV8_PMU_COUNTER_MASK	(ARMV8_PMU_MAX_COUNTERS - 1)
14 
15 /*
16  * Common architectural and microarchitectural event numbers.
17  */
18 #define ARMV8_PMUV3_PERFCTR_SW_INCR				0x00
19 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL			0x01
20 #define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL			0x02
21 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL			0x03
22 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE				0x04
23 #define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL			0x05
24 #define ARMV8_PMUV3_PERFCTR_LD_RETIRED				0x06
25 #define ARMV8_PMUV3_PERFCTR_ST_RETIRED				0x07
26 #define ARMV8_PMUV3_PERFCTR_INST_RETIRED			0x08
27 #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN				0x09
28 #define ARMV8_PMUV3_PERFCTR_EXC_RETURN				0x0A
29 #define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED			0x0B
30 #define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED			0x0C
31 #define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED			0x0D
32 #define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED			0x0E
33 #define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED		0x0F
34 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED				0x10
35 #define ARMV8_PMUV3_PERFCTR_CPU_CYCLES				0x11
36 #define ARMV8_PMUV3_PERFCTR_BR_PRED				0x12
37 #define ARMV8_PMUV3_PERFCTR_MEM_ACCESS				0x13
38 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE				0x14
39 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB			0x15
40 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE				0x16
41 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL			0x17
42 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB			0x18
43 #define ARMV8_PMUV3_PERFCTR_BUS_ACCESS				0x19
44 #define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR			0x1A
45 #define ARMV8_PMUV3_PERFCTR_INST_SPEC				0x1B
46 #define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED			0x1C
47 #define ARMV8_PMUV3_PERFCTR_BUS_CYCLES				0x1D
48 #define ARMV8_PMUV3_PERFCTR_CHAIN				0x1E
49 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE			0x1F
50 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE			0x20
51 #define ARMV8_PMUV3_PERFCTR_BR_RETIRED				0x21
52 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED			0x22
53 #define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND			0x23
54 #define ARMV8_PMUV3_PERFCTR_STALL_BACKEND			0x24
55 #define ARMV8_PMUV3_PERFCTR_L1D_TLB				0x25
56 #define ARMV8_PMUV3_PERFCTR_L1I_TLB				0x26
57 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE				0x27
58 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL			0x28
59 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE			0x29
60 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL			0x2A
61 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE				0x2B
62 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB			0x2C
63 #define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL			0x2D
64 #define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL			0x2E
65 #define ARMV8_PMUV3_PERFCTR_L2D_TLB				0x2F
66 #define ARMV8_PMUV3_PERFCTR_L2I_TLB				0x30
67 #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS			0x31
68 #define ARMV8_PMUV3_PERFCTR_LL_CACHE				0x32
69 #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS			0x33
70 #define ARMV8_PMUV3_PERFCTR_DTLB_WALK				0x34
71 #define ARMV8_PMUV3_PERFCTR_ITLB_WALK				0x35
72 #define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD				0x36
73 #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD			0x37
74 #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD			0x38
75 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD			0x39
76 #define ARMV8_PMUV3_PERFCTR_OP_RETIRED				0x3A
77 #define ARMV8_PMUV3_PERFCTR_OP_SPEC				0x3B
78 #define ARMV8_PMUV3_PERFCTR_STALL				0x3C
79 #define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND			0x3D
80 #define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND			0x3E
81 #define ARMV8_PMUV3_PERFCTR_STALL_SLOT				0x3F
82 
83 /* Statistical profiling extension microarchitectural events */
84 #define	ARMV8_SPE_PERFCTR_SAMPLE_POP				0x4000
85 #define	ARMV8_SPE_PERFCTR_SAMPLE_FEED				0x4001
86 #define	ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE			0x4002
87 #define	ARMV8_SPE_PERFCTR_SAMPLE_COLLISION			0x4003
88 
89 /* AMUv1 architecture events */
90 #define	ARMV8_AMU_PERFCTR_CNT_CYCLES				0x4004
91 #define	ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM			0x4005
92 
93 /* long-latency read miss events */
94 #define	ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS			0x4006
95 #define	ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD			0x4009
96 #define	ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS			0x400A
97 #define	ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD			0x400B
98 
99 /* additional latency from alignment events */
100 #define	ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT			0x4020
101 #define	ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT			0x4021
102 #define	ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT			0x4022
103 
104 /* Armv8.5 Memory Tagging Extension events */
105 #define	ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED			0x4024
106 #define	ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD			0x4025
107 #define	ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR			0x4026
108 
109 /* ARMv8 recommended implementation defined event types */
110 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD			0x40
111 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR			0x41
112 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD		0x42
113 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR		0x43
114 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER		0x44
115 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER		0x45
116 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM		0x46
117 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN			0x47
118 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL			0x48
119 
120 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD			0x4C
121 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR			0x4D
122 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD				0x4E
123 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR				0x4F
124 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD			0x50
125 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR			0x51
126 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD		0x52
127 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR		0x53
128 
129 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM		0x56
130 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN			0x57
131 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL			0x58
132 
133 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD			0x5C
134 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR			0x5D
135 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD				0x5E
136 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR				0x5F
137 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD			0x60
138 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR			0x61
139 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED			0x62
140 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED		0x63
141 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL			0x64
142 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH			0x65
143 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD			0x66
144 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR			0x67
145 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC			0x68
146 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC			0x69
147 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC		0x6A
148 
149 #define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC				0x6C
150 #define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC			0x6D
151 #define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC			0x6E
152 #define ARMV8_IMPDEF_PERFCTR_STREX_SPEC				0x6F
153 #define ARMV8_IMPDEF_PERFCTR_LD_SPEC				0x70
154 #define ARMV8_IMPDEF_PERFCTR_ST_SPEC				0x71
155 #define ARMV8_IMPDEF_PERFCTR_LDST_SPEC				0x72
156 #define ARMV8_IMPDEF_PERFCTR_DP_SPEC				0x73
157 #define ARMV8_IMPDEF_PERFCTR_ASE_SPEC				0x74
158 #define ARMV8_IMPDEF_PERFCTR_VFP_SPEC				0x75
159 #define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC			0x76
160 #define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC			0x77
161 #define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC			0x78
162 #define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC			0x79
163 #define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC			0x7A
164 
165 #define ARMV8_IMPDEF_PERFCTR_ISB_SPEC				0x7C
166 #define ARMV8_IMPDEF_PERFCTR_DSB_SPEC				0x7D
167 #define ARMV8_IMPDEF_PERFCTR_DMB_SPEC				0x7E
168 
169 #define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF				0x81
170 #define ARMV8_IMPDEF_PERFCTR_EXC_SVC				0x82
171 #define ARMV8_IMPDEF_PERFCTR_EXC_PABORT				0x83
172 #define ARMV8_IMPDEF_PERFCTR_EXC_DABORT				0x84
173 
174 #define ARMV8_IMPDEF_PERFCTR_EXC_IRQ				0x86
175 #define ARMV8_IMPDEF_PERFCTR_EXC_FIQ				0x87
176 #define ARMV8_IMPDEF_PERFCTR_EXC_SMC				0x88
177 
178 #define ARMV8_IMPDEF_PERFCTR_EXC_HVC				0x8A
179 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT			0x8B
180 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT			0x8C
181 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER			0x8D
182 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ			0x8E
183 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ			0x8F
184 #define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC				0x90
185 #define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC				0x91
186 
187 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD			0xA0
188 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR			0xA1
189 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD		0xA2
190 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR		0xA3
191 
192 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM		0xA6
193 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN			0xA7
194 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL			0xA8
195 
196 /*
197  * Per-CPU PMCR: config reg
198  */
199 #define ARMV8_PMU_PMCR_E	(1 << 0) /* Enable all counters */
200 #define ARMV8_PMU_PMCR_P	(1 << 1) /* Reset all counters */
201 #define ARMV8_PMU_PMCR_C	(1 << 2) /* Cycle counter reset */
202 #define ARMV8_PMU_PMCR_D	(1 << 3) /* CCNT counts every 64th cpu cycle */
203 #define ARMV8_PMU_PMCR_X	(1 << 4) /* Export to ETM */
204 #define ARMV8_PMU_PMCR_DP	(1 << 5) /* Disable CCNT if non-invasive debug*/
205 #define ARMV8_PMU_PMCR_LC	(1 << 6) /* Overflow on 64 bit cycle counter */
206 #define ARMV8_PMU_PMCR_LP	(1 << 7) /* Long event counter enable */
207 #define	ARMV8_PMU_PMCR_N_SHIFT	11	 /* Number of counters supported */
208 #define	ARMV8_PMU_PMCR_N_MASK	0x1f
209 #define	ARMV8_PMU_PMCR_MASK	0xff	 /* Mask for writable bits */
210 
211 /*
212  * PMOVSR: counters overflow flag status reg
213  */
214 #define	ARMV8_PMU_OVSR_MASK		0xffffffff	/* Mask for writable bits */
215 #define	ARMV8_PMU_OVERFLOWED_MASK	ARMV8_PMU_OVSR_MASK
216 
217 /*
218  * PMXEVTYPER: Event selection reg
219  */
220 #define	ARMV8_PMU_EVTYPE_MASK	0xc800ffff	/* Mask for writable bits */
221 #define	ARMV8_PMU_EVTYPE_EVENT	0xffff		/* Mask for EVENT bits */
222 
223 /*
224  * Event filters for PMUv3
225  */
226 #define	ARMV8_PMU_EXCLUDE_EL1	(1U << 31)
227 #define	ARMV8_PMU_EXCLUDE_EL0	(1U << 30)
228 #define	ARMV8_PMU_INCLUDE_EL2	(1U << 27)
229 
230 /*
231  * PMUSERENR: user enable reg
232  */
233 #define ARMV8_PMU_USERENR_MASK	0xf		/* Mask for writable bits */
234 #define ARMV8_PMU_USERENR_EN	(1 << 0) /* PMU regs can be accessed at EL0 */
235 #define ARMV8_PMU_USERENR_SW	(1 << 1) /* PMSWINC can be written at EL0 */
236 #define ARMV8_PMU_USERENR_CR	(1 << 2) /* Cycle counter can be read at EL0 */
237 #define ARMV8_PMU_USERENR_ER	(1 << 3) /* Event counter can be read at EL0 */
238 
239 #ifdef CONFIG_PERF_EVENTS
240 struct pt_regs;
241 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
242 extern unsigned long perf_misc_flags(struct pt_regs *regs);
243 #define perf_misc_flags(regs)	perf_misc_flags(regs)
244 #define perf_arch_bpf_user_pt_regs(regs) &regs->user_regs
245 #endif
246 
247 #define perf_arch_fetch_caller_regs(regs, __ip) { \
248 	(regs)->pc = (__ip);    \
249 	(regs)->regs[29] = (unsigned long) __builtin_frame_address(0); \
250 	(regs)->sp = current_stack_pointer; \
251 	(regs)->pstate = PSR_MODE_EL1h;	\
252 }
253 
254 #endif
255