1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __ASM_PERF_EVENT_H 18 #define __ASM_PERF_EVENT_H 19 20 #include <asm/stack_pointer.h> 21 #include <asm/ptrace.h> 22 23 #define ARMV8_PMU_MAX_COUNTERS 32 24 #define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1) 25 26 /* 27 * Common architectural and microarchitectural event numbers. 28 */ 29 #define ARMV8_PMUV3_PERFCTR_SW_INCR 0x00 30 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x01 31 #define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x02 32 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x03 33 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x04 34 #define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x05 35 #define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x06 36 #define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x07 37 #define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x08 38 #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x09 39 #define ARMV8_PMUV3_PERFCTR_EXC_RETURN 0x0A 40 #define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED 0x0B 41 #define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED 0x0C 42 #define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED 0x0D 43 #define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED 0x0E 44 #define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED 0x0F 45 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x10 46 #define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x11 47 #define ARMV8_PMUV3_PERFCTR_BR_PRED 0x12 48 #define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x13 49 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE 0x14 50 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB 0x15 51 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE 0x16 52 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL 0x17 53 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB 0x18 54 #define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x19 55 #define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR 0x1A 56 #define ARMV8_PMUV3_PERFCTR_INST_SPEC 0x1B 57 #define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED 0x1C 58 #define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x1D 59 #define ARMV8_PMUV3_PERFCTR_CHAIN 0x1E 60 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x1F 61 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x20 62 #define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x21 63 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x22 64 #define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x23 65 #define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x24 66 #define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x25 67 #define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x26 68 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x27 69 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x28 70 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x29 71 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x2A 72 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x2B 73 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x2C 74 #define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x2D 75 #define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL 0x2E 76 #define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x2F 77 #define ARMV8_PMUV3_PERFCTR_L2I_TLB 0x30 78 #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS 0x31 79 #define ARMV8_PMUV3_PERFCTR_LL_CACHE 0x32 80 #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS 0x33 81 #define ARMV8_PMUV3_PERFCTR_DTLB_WALK 0x34 82 #define ARMV8_PMUV3_PERFCTR_ITLB_WALK 0x35 83 #define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36 84 #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37 85 #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38 86 87 /* Statistical profiling extension microarchitectural events */ 88 #define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000 89 #define ARMV8_SPE_PERFCTR_SAMPLE_FEED 0x4001 90 #define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002 91 #define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003 92 93 /* ARMv8 recommended implementation defined event types */ 94 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x40 95 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x41 96 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD 0x42 97 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x43 98 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER 0x44 99 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER 0x45 100 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM 0x46 101 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN 0x47 102 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL 0x48 103 104 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x4C 105 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x4D 106 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x4E 107 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x4F 108 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD 0x50 109 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR 0x51 110 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD 0x52 111 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR 0x53 112 113 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM 0x56 114 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN 0x57 115 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL 0x58 116 117 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD 0x5C 118 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR 0x5D 119 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD 0x5E 120 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR 0x5F 121 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x60 122 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x61 123 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED 0x62 124 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED 0x63 125 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL 0x64 126 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH 0x65 127 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD 0x66 128 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR 0x67 129 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC 0x68 130 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC 0x69 131 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC 0x6A 132 133 #define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC 0x6C 134 #define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC 0x6D 135 #define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC 0x6E 136 #define ARMV8_IMPDEF_PERFCTR_STREX_SPEC 0x6F 137 #define ARMV8_IMPDEF_PERFCTR_LD_SPEC 0x70 138 #define ARMV8_IMPDEF_PERFCTR_ST_SPEC 0x71 139 #define ARMV8_IMPDEF_PERFCTR_LDST_SPEC 0x72 140 #define ARMV8_IMPDEF_PERFCTR_DP_SPEC 0x73 141 #define ARMV8_IMPDEF_PERFCTR_ASE_SPEC 0x74 142 #define ARMV8_IMPDEF_PERFCTR_VFP_SPEC 0x75 143 #define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC 0x76 144 #define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC 0x77 145 #define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC 0x78 146 #define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC 0x79 147 #define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC 0x7A 148 149 #define ARMV8_IMPDEF_PERFCTR_ISB_SPEC 0x7C 150 #define ARMV8_IMPDEF_PERFCTR_DSB_SPEC 0x7D 151 #define ARMV8_IMPDEF_PERFCTR_DMB_SPEC 0x7E 152 153 #define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF 0x81 154 #define ARMV8_IMPDEF_PERFCTR_EXC_SVC 0x82 155 #define ARMV8_IMPDEF_PERFCTR_EXC_PABORT 0x83 156 #define ARMV8_IMPDEF_PERFCTR_EXC_DABORT 0x84 157 158 #define ARMV8_IMPDEF_PERFCTR_EXC_IRQ 0x86 159 #define ARMV8_IMPDEF_PERFCTR_EXC_FIQ 0x87 160 #define ARMV8_IMPDEF_PERFCTR_EXC_SMC 0x88 161 162 #define ARMV8_IMPDEF_PERFCTR_EXC_HVC 0x8A 163 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT 0x8B 164 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT 0x8C 165 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER 0x8D 166 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ 0x8E 167 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ 0x8F 168 #define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC 0x90 169 #define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC 0x91 170 171 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD 0xA0 172 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR 0xA1 173 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD 0xA2 174 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR 0xA3 175 176 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM 0xA6 177 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN 0xA7 178 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL 0xA8 179 180 /* 181 * Per-CPU PMCR: config reg 182 */ 183 #define ARMV8_PMU_PMCR_E (1 << 0) /* Enable all counters */ 184 #define ARMV8_PMU_PMCR_P (1 << 1) /* Reset all counters */ 185 #define ARMV8_PMU_PMCR_C (1 << 2) /* Cycle counter reset */ 186 #define ARMV8_PMU_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ 187 #define ARMV8_PMU_PMCR_X (1 << 4) /* Export to ETM */ 188 #define ARMV8_PMU_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 189 #define ARMV8_PMU_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */ 190 #define ARMV8_PMU_PMCR_N_SHIFT 11 /* Number of counters supported */ 191 #define ARMV8_PMU_PMCR_N_MASK 0x1f 192 #define ARMV8_PMU_PMCR_MASK 0x7f /* Mask for writable bits */ 193 194 /* 195 * PMOVSR: counters overflow flag status reg 196 */ 197 #define ARMV8_PMU_OVSR_MASK 0xffffffff /* Mask for writable bits */ 198 #define ARMV8_PMU_OVERFLOWED_MASK ARMV8_PMU_OVSR_MASK 199 200 /* 201 * PMXEVTYPER: Event selection reg 202 */ 203 #define ARMV8_PMU_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */ 204 #define ARMV8_PMU_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */ 205 206 /* 207 * Event filters for PMUv3 208 */ 209 #define ARMV8_PMU_EXCLUDE_EL1 (1U << 31) 210 #define ARMV8_PMU_EXCLUDE_EL0 (1U << 30) 211 #define ARMV8_PMU_INCLUDE_EL2 (1U << 27) 212 213 /* 214 * PMUSERENR: user enable reg 215 */ 216 #define ARMV8_PMU_USERENR_MASK 0xf /* Mask for writable bits */ 217 #define ARMV8_PMU_USERENR_EN (1 << 0) /* PMU regs can be accessed at EL0 */ 218 #define ARMV8_PMU_USERENR_SW (1 << 1) /* PMSWINC can be written at EL0 */ 219 #define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */ 220 #define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */ 221 222 #ifdef CONFIG_PERF_EVENTS 223 struct pt_regs; 224 extern unsigned long perf_instruction_pointer(struct pt_regs *regs); 225 extern unsigned long perf_misc_flags(struct pt_regs *regs); 226 #define perf_misc_flags(regs) perf_misc_flags(regs) 227 #define perf_arch_bpf_user_pt_regs(regs) ®s->user_regs 228 #endif 229 230 #define perf_arch_fetch_caller_regs(regs, __ip) { \ 231 (regs)->pc = (__ip); \ 232 (regs)->regs[29] = (unsigned long) __builtin_frame_address(0); \ 233 (regs)->sp = current_stack_pointer; \ 234 (regs)->pstate = PSR_MODE_EL1h; \ 235 } 236 237 #endif 238