1 /*
2  * Copyright (C) 2012 ARM Ltd.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16 
17 #ifndef __ASM_PERF_EVENT_H
18 #define __ASM_PERF_EVENT_H
19 
20 #include <asm/stack_pointer.h>
21 #include <asm/ptrace.h>
22 
23 #define	ARMV8_PMU_MAX_COUNTERS	32
24 #define	ARMV8_PMU_COUNTER_MASK	(ARMV8_PMU_MAX_COUNTERS - 1)
25 
26 /*
27  * Per-CPU PMCR: config reg
28  */
29 #define ARMV8_PMU_PMCR_E	(1 << 0) /* Enable all counters */
30 #define ARMV8_PMU_PMCR_P	(1 << 1) /* Reset all counters */
31 #define ARMV8_PMU_PMCR_C	(1 << 2) /* Cycle counter reset */
32 #define ARMV8_PMU_PMCR_D	(1 << 3) /* CCNT counts every 64th cpu cycle */
33 #define ARMV8_PMU_PMCR_X	(1 << 4) /* Export to ETM */
34 #define ARMV8_PMU_PMCR_DP	(1 << 5) /* Disable CCNT if non-invasive debug*/
35 #define ARMV8_PMU_PMCR_LC	(1 << 6) /* Overflow on 64 bit cycle counter */
36 #define	ARMV8_PMU_PMCR_N_SHIFT	11	 /* Number of counters supported */
37 #define	ARMV8_PMU_PMCR_N_MASK	0x1f
38 #define	ARMV8_PMU_PMCR_MASK	0x7f	 /* Mask for writable bits */
39 
40 /*
41  * PMOVSR: counters overflow flag status reg
42  */
43 #define	ARMV8_PMU_OVSR_MASK		0xffffffff	/* Mask for writable bits */
44 #define	ARMV8_PMU_OVERFLOWED_MASK	ARMV8_PMU_OVSR_MASK
45 
46 /*
47  * PMXEVTYPER: Event selection reg
48  */
49 #define	ARMV8_PMU_EVTYPE_MASK	0xc800ffff	/* Mask for writable bits */
50 #define	ARMV8_PMU_EVTYPE_EVENT	0xffff		/* Mask for EVENT bits */
51 
52 /*
53  * PMUv3 event types: required events
54  */
55 #define ARMV8_PMUV3_PERFCTR_SW_INCR				0x00
56 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL			0x03
57 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE				0x04
58 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED				0x10
59 #define ARMV8_PMUV3_PERFCTR_CPU_CYCLES				0x11
60 #define ARMV8_PMUV3_PERFCTR_BR_PRED				0x12
61 
62 /*
63  * Event filters for PMUv3
64  */
65 #define	ARMV8_PMU_EXCLUDE_EL1	(1 << 31)
66 #define	ARMV8_PMU_EXCLUDE_EL0	(1 << 30)
67 #define	ARMV8_PMU_INCLUDE_EL2	(1 << 27)
68 
69 /*
70  * PMUSERENR: user enable reg
71  */
72 #define ARMV8_PMU_USERENR_MASK	0xf		/* Mask for writable bits */
73 #define ARMV8_PMU_USERENR_EN	(1 << 0) /* PMU regs can be accessed at EL0 */
74 #define ARMV8_PMU_USERENR_SW	(1 << 1) /* PMSWINC can be written at EL0 */
75 #define ARMV8_PMU_USERENR_CR	(1 << 2) /* Cycle counter can be read at EL0 */
76 #define ARMV8_PMU_USERENR_ER	(1 << 3) /* Event counter can be read at EL0 */
77 
78 #ifdef CONFIG_PERF_EVENTS
79 struct pt_regs;
80 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
81 extern unsigned long perf_misc_flags(struct pt_regs *regs);
82 #define perf_misc_flags(regs)	perf_misc_flags(regs)
83 #define perf_arch_bpf_user_pt_regs(regs) &regs->user_regs
84 #endif
85 
86 #define perf_arch_fetch_caller_regs(regs, __ip) { \
87 	(regs)->pc = (__ip);    \
88 	(regs)->regs[29] = (unsigned long) __builtin_frame_address(0); \
89 	(regs)->sp = current_stack_pointer; \
90 	(regs)->pstate = PSR_MODE_EL1h;	\
91 }
92 
93 #endif
94