1 /* 2 * Based on arch/arm/include/asm/mmu_context.h 3 * 4 * Copyright (C) 1996 Russell King. 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASM_MMU_CONTEXT_H 20 #define __ASM_MMU_CONTEXT_H 21 22 #include <linux/compiler.h> 23 #include <linux/sched.h> 24 25 #include <asm/cacheflush.h> 26 #include <asm/proc-fns.h> 27 #include <asm-generic/mm_hooks.h> 28 #include <asm/cputype.h> 29 #include <asm/pgtable.h> 30 31 #define MAX_ASID_BITS 16 32 33 extern unsigned int cpu_last_asid; 34 35 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm); 36 void __new_context(struct mm_struct *mm); 37 38 #ifdef CONFIG_PID_IN_CONTEXTIDR 39 static inline void contextidr_thread_switch(struct task_struct *next) 40 { 41 asm( 42 " msr contextidr_el1, %0\n" 43 " isb" 44 : 45 : "r" (task_pid_nr(next))); 46 } 47 #else 48 static inline void contextidr_thread_switch(struct task_struct *next) 49 { 50 } 51 #endif 52 53 /* 54 * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0. 55 */ 56 static inline void cpu_set_reserved_ttbr0(void) 57 { 58 unsigned long ttbr = page_to_phys(empty_zero_page); 59 60 asm( 61 " msr ttbr0_el1, %0 // set TTBR0\n" 62 " isb" 63 : 64 : "r" (ttbr)); 65 } 66 67 /* 68 * TCR.T0SZ value to use when the ID map is active. Usually equals 69 * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in 70 * physical memory, in which case it will be smaller. 71 */ 72 extern u64 idmap_t0sz; 73 74 static inline bool __cpu_uses_extended_idmap(void) 75 { 76 return (!IS_ENABLED(CONFIG_ARM64_VA_BITS_48) && 77 unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS))); 78 } 79 80 static inline void __cpu_set_tcr_t0sz(u64 t0sz) 81 { 82 unsigned long tcr; 83 84 if (__cpu_uses_extended_idmap()) 85 asm volatile ( 86 " mrs %0, tcr_el1 ;" 87 " bfi %0, %1, %2, %3 ;" 88 " msr tcr_el1, %0 ;" 89 " isb" 90 : "=&r" (tcr) 91 : "r"(t0sz), "I"(TCR_T0SZ_OFFSET), "I"(TCR_TxSZ_WIDTH)); 92 } 93 94 /* 95 * Set TCR.T0SZ to the value appropriate for activating the identity map. 96 */ 97 static inline void cpu_set_idmap_tcr_t0sz(void) 98 { 99 __cpu_set_tcr_t0sz(idmap_t0sz); 100 } 101 102 /* 103 * Set TCR.T0SZ to its default value (based on VA_BITS) 104 */ 105 static inline void cpu_set_default_tcr_t0sz(void) 106 { 107 __cpu_set_tcr_t0sz(TCR_T0SZ(VA_BITS)); 108 } 109 110 static inline void switch_new_context(struct mm_struct *mm) 111 { 112 unsigned long flags; 113 114 __new_context(mm); 115 116 local_irq_save(flags); 117 cpu_switch_mm(mm->pgd, mm); 118 local_irq_restore(flags); 119 } 120 121 static inline void check_and_switch_context(struct mm_struct *mm, 122 struct task_struct *tsk) 123 { 124 /* 125 * Required during context switch to avoid speculative page table 126 * walking with the wrong TTBR. 127 */ 128 cpu_set_reserved_ttbr0(); 129 130 if (!((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS)) 131 /* 132 * The ASID is from the current generation, just switch to the 133 * new pgd. This condition is only true for calls from 134 * context_switch() and interrupts are already disabled. 135 */ 136 cpu_switch_mm(mm->pgd, mm); 137 else if (irqs_disabled()) 138 /* 139 * Defer the new ASID allocation until after the context 140 * switch critical region since __new_context() cannot be 141 * called with interrupts disabled. 142 */ 143 set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM); 144 else 145 /* 146 * That is a direct call to switch_mm() or activate_mm() with 147 * interrupts enabled and a new context. 148 */ 149 switch_new_context(mm); 150 } 151 152 #define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0) 153 #define destroy_context(mm) do { } while(0) 154 155 #define finish_arch_post_lock_switch \ 156 finish_arch_post_lock_switch 157 static inline void finish_arch_post_lock_switch(void) 158 { 159 if (test_and_clear_thread_flag(TIF_SWITCH_MM)) { 160 struct mm_struct *mm = current->mm; 161 unsigned long flags; 162 163 __new_context(mm); 164 165 local_irq_save(flags); 166 cpu_switch_mm(mm->pgd, mm); 167 local_irq_restore(flags); 168 } 169 } 170 171 /* 172 * This is called when "tsk" is about to enter lazy TLB mode. 173 * 174 * mm: describes the currently active mm context 175 * tsk: task which is entering lazy tlb 176 * cpu: cpu number which is entering lazy tlb 177 * 178 * tsk->mm will be NULL 179 */ 180 static inline void 181 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 182 { 183 } 184 185 /* 186 * This is the actual mm switch as far as the scheduler 187 * is concerned. No registers are touched. We avoid 188 * calling the CPU specific function when the mm hasn't 189 * actually changed. 190 */ 191 static inline void 192 switch_mm(struct mm_struct *prev, struct mm_struct *next, 193 struct task_struct *tsk) 194 { 195 unsigned int cpu = smp_processor_id(); 196 197 /* 198 * init_mm.pgd does not contain any user mappings and it is always 199 * active for kernel addresses in TTBR1. Just set the reserved TTBR0. 200 */ 201 if (next == &init_mm) { 202 cpu_set_reserved_ttbr0(); 203 return; 204 } 205 206 if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) 207 check_and_switch_context(next, tsk); 208 } 209 210 #define deactivate_mm(tsk,mm) do { } while (0) 211 #define activate_mm(prev,next) switch_mm(prev, next, NULL) 212 213 #endif 214