1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/mmu_context.h 4 * 5 * Copyright (C) 1996 Russell King. 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASM_MMU_CONTEXT_H 9 #define __ASM_MMU_CONTEXT_H 10 11 #ifndef __ASSEMBLY__ 12 13 #include <linux/compiler.h> 14 #include <linux/sched.h> 15 #include <linux/sched/hotplug.h> 16 #include <linux/mm_types.h> 17 #include <linux/pgtable.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/cpufeature.h> 21 #include <asm/proc-fns.h> 22 #include <asm-generic/mm_hooks.h> 23 #include <asm/cputype.h> 24 #include <asm/sysreg.h> 25 #include <asm/tlbflush.h> 26 27 extern bool rodata_full; 28 29 static inline void contextidr_thread_switch(struct task_struct *next) 30 { 31 if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR)) 32 return; 33 34 write_sysreg(task_pid_nr(next), contextidr_el1); 35 isb(); 36 } 37 38 /* 39 * Set TTBR0 to reserved_pg_dir. No translations will be possible via TTBR0. 40 */ 41 static inline void cpu_set_reserved_ttbr0(void) 42 { 43 unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); 44 45 write_sysreg(ttbr, ttbr0_el1); 46 isb(); 47 } 48 49 void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); 50 51 static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) 52 { 53 BUG_ON(pgd == swapper_pg_dir); 54 cpu_set_reserved_ttbr0(); 55 cpu_do_switch_mm(virt_to_phys(pgd),mm); 56 } 57 58 /* 59 * TCR.T0SZ value to use when the ID map is active. Usually equals 60 * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in 61 * physical memory, in which case it will be smaller. 62 */ 63 extern int idmap_t0sz; 64 65 /* 66 * Ensure TCR.T0SZ is set to the provided value. 67 */ 68 static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) 69 { 70 unsigned long tcr = read_sysreg(tcr_el1); 71 72 if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz) 73 return; 74 75 tcr &= ~TCR_T0SZ_MASK; 76 tcr |= t0sz << TCR_T0SZ_OFFSET; 77 write_sysreg(tcr, tcr_el1); 78 isb(); 79 } 80 81 #define cpu_set_default_tcr_t0sz() __cpu_set_tcr_t0sz(TCR_T0SZ(vabits_actual)) 82 #define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz) 83 84 /* 85 * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm. 86 * 87 * The idmap lives in the same VA range as userspace, but uses global entries 88 * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from 89 * speculative TLB fetches, we must temporarily install the reserved page 90 * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ. 91 * 92 * If current is a not a user task, the mm covers the TTBR1_EL1 page tables, 93 * which should not be installed in TTBR0_EL1. In this case we can leave the 94 * reserved page tables in place. 95 */ 96 static inline void cpu_uninstall_idmap(void) 97 { 98 struct mm_struct *mm = current->active_mm; 99 100 cpu_set_reserved_ttbr0(); 101 local_flush_tlb_all(); 102 cpu_set_default_tcr_t0sz(); 103 104 if (mm != &init_mm && !system_uses_ttbr0_pan()) 105 cpu_switch_mm(mm->pgd, mm); 106 } 107 108 static inline void __cpu_install_idmap(pgd_t *idmap) 109 { 110 cpu_set_reserved_ttbr0(); 111 local_flush_tlb_all(); 112 cpu_set_idmap_tcr_t0sz(); 113 114 cpu_switch_mm(lm_alias(idmap), &init_mm); 115 } 116 117 static inline void cpu_install_idmap(void) 118 { 119 __cpu_install_idmap(idmap_pg_dir); 120 } 121 122 /* 123 * Load our new page tables. A strict BBM approach requires that we ensure that 124 * TLBs are free of any entries that may overlap with the global mappings we are 125 * about to install. 126 * 127 * For a real hibernate/resume/kexec cycle TTBR0 currently points to a zero 128 * page, but TLBs may contain stale ASID-tagged entries (e.g. for EFI runtime 129 * services), while for a userspace-driven test_resume cycle it points to 130 * userspace page tables (and we must point it at a zero page ourselves). 131 * 132 * We change T0SZ as part of installing the idmap. This is undone by 133 * cpu_uninstall_idmap() in __cpu_suspend_exit(). 134 */ 135 static inline void cpu_install_ttbr0(phys_addr_t ttbr0, unsigned long t0sz) 136 { 137 cpu_set_reserved_ttbr0(); 138 local_flush_tlb_all(); 139 __cpu_set_tcr_t0sz(t0sz); 140 141 /* avoid cpu_switch_mm() and its SW-PAN and CNP interactions */ 142 write_sysreg(ttbr0, ttbr0_el1); 143 isb(); 144 } 145 146 /* 147 * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD, 148 * avoiding the possibility of conflicting TLB entries being allocated. 149 */ 150 static inline void cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap) 151 { 152 typedef void (ttbr_replace_func)(phys_addr_t); 153 extern ttbr_replace_func idmap_cpu_replace_ttbr1; 154 ttbr_replace_func *replace_phys; 155 156 /* phys_to_ttbr() zeros lower 2 bits of ttbr with 52-bit PA */ 157 phys_addr_t ttbr1 = phys_to_ttbr(virt_to_phys(pgdp)); 158 159 if (system_supports_cnp() && !WARN_ON(pgdp != lm_alias(swapper_pg_dir))) { 160 /* 161 * cpu_replace_ttbr1() is used when there's a boot CPU 162 * up (i.e. cpufeature framework is not up yet) and 163 * latter only when we enable CNP via cpufeature's 164 * enable() callback. 165 * Also we rely on the cpu_hwcap bit being set before 166 * calling the enable() function. 167 */ 168 ttbr1 |= TTBR_CNP_BIT; 169 } 170 171 replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1); 172 173 __cpu_install_idmap(idmap); 174 replace_phys(ttbr1); 175 cpu_uninstall_idmap(); 176 } 177 178 /* 179 * It would be nice to return ASIDs back to the allocator, but unfortunately 180 * that introduces a race with a generation rollover where we could erroneously 181 * free an ASID allocated in a future generation. We could workaround this by 182 * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap), 183 * but we'd then need to make sure that we didn't dirty any TLBs afterwards. 184 * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you 185 * take CPU migration into account. 186 */ 187 void check_and_switch_context(struct mm_struct *mm); 188 189 #define init_new_context(tsk, mm) init_new_context(tsk, mm) 190 static inline int 191 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 192 { 193 atomic64_set(&mm->context.id, 0); 194 refcount_set(&mm->context.pinned, 0); 195 return 0; 196 } 197 198 #ifdef CONFIG_ARM64_SW_TTBR0_PAN 199 static inline void update_saved_ttbr0(struct task_struct *tsk, 200 struct mm_struct *mm) 201 { 202 u64 ttbr; 203 204 if (!system_uses_ttbr0_pan()) 205 return; 206 207 if (mm == &init_mm) 208 ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); 209 else 210 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; 211 212 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); 213 } 214 #else 215 static inline void update_saved_ttbr0(struct task_struct *tsk, 216 struct mm_struct *mm) 217 { 218 } 219 #endif 220 221 #define enter_lazy_tlb enter_lazy_tlb 222 static inline void 223 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 224 { 225 /* 226 * We don't actually care about the ttbr0 mapping, so point it at the 227 * zero page. 228 */ 229 update_saved_ttbr0(tsk, &init_mm); 230 } 231 232 static inline void __switch_mm(struct mm_struct *next) 233 { 234 /* 235 * init_mm.pgd does not contain any user mappings and it is always 236 * active for kernel addresses in TTBR1. Just set the reserved TTBR0. 237 */ 238 if (next == &init_mm) { 239 cpu_set_reserved_ttbr0(); 240 return; 241 } 242 243 check_and_switch_context(next); 244 } 245 246 static inline void 247 switch_mm(struct mm_struct *prev, struct mm_struct *next, 248 struct task_struct *tsk) 249 { 250 if (prev != next) 251 __switch_mm(next); 252 253 /* 254 * Update the saved TTBR0_EL1 of the scheduled-in task as the previous 255 * value may have not been initialised yet (activate_mm caller) or the 256 * ASID has changed since the last run (following the context switch 257 * of another thread of the same process). 258 */ 259 update_saved_ttbr0(tsk, next); 260 } 261 262 static inline const struct cpumask * 263 task_cpu_possible_mask(struct task_struct *p) 264 { 265 if (!static_branch_unlikely(&arm64_mismatched_32bit_el0)) 266 return cpu_possible_mask; 267 268 if (!is_compat_thread(task_thread_info(p))) 269 return cpu_possible_mask; 270 271 return system_32bit_el0_cpumask(); 272 } 273 #define task_cpu_possible_mask task_cpu_possible_mask 274 275 void verify_cpu_asid_bits(void); 276 void post_ttbr_update_workaround(void); 277 278 unsigned long arm64_mm_context_get(struct mm_struct *mm); 279 void arm64_mm_context_put(struct mm_struct *mm); 280 281 #include <asm-generic/mmu_context.h> 282 283 #endif /* !__ASSEMBLY__ */ 284 285 #endif /* !__ASM_MMU_CONTEXT_H */ 286