1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/mmu_context.h 4 * 5 * Copyright (C) 1996 Russell King. 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASM_MMU_CONTEXT_H 9 #define __ASM_MMU_CONTEXT_H 10 11 #ifndef __ASSEMBLY__ 12 13 #include <linux/compiler.h> 14 #include <linux/sched.h> 15 #include <linux/sched/hotplug.h> 16 #include <linux/mm_types.h> 17 #include <linux/pgtable.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/cpufeature.h> 21 #include <asm/proc-fns.h> 22 #include <asm-generic/mm_hooks.h> 23 #include <asm/cputype.h> 24 #include <asm/sysreg.h> 25 #include <asm/tlbflush.h> 26 27 extern bool rodata_full; 28 29 static inline void contextidr_thread_switch(struct task_struct *next) 30 { 31 if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR)) 32 return; 33 34 write_sysreg(task_pid_nr(next), contextidr_el1); 35 isb(); 36 } 37 38 /* 39 * Set TTBR0 to reserved_pg_dir. No translations will be possible via TTBR0. 40 */ 41 static inline void cpu_set_reserved_ttbr0(void) 42 { 43 unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); 44 45 write_sysreg(ttbr, ttbr0_el1); 46 isb(); 47 } 48 49 void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); 50 51 static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) 52 { 53 BUG_ON(pgd == swapper_pg_dir); 54 cpu_set_reserved_ttbr0(); 55 cpu_do_switch_mm(virt_to_phys(pgd),mm); 56 } 57 58 /* 59 * TCR.T0SZ value to use when the ID map is active. Usually equals 60 * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in 61 * physical memory, in which case it will be smaller. 62 */ 63 extern u64 idmap_t0sz; 64 extern u64 idmap_ptrs_per_pgd; 65 66 static inline bool __cpu_uses_extended_idmap(void) 67 { 68 if (IS_ENABLED(CONFIG_ARM64_VA_BITS_52)) 69 return false; 70 71 return unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS)); 72 } 73 74 /* 75 * True if the extended ID map requires an extra level of translation table 76 * to be configured. 77 */ 78 static inline bool __cpu_uses_extended_idmap_level(void) 79 { 80 return ARM64_HW_PGTABLE_LEVELS(64 - idmap_t0sz) > CONFIG_PGTABLE_LEVELS; 81 } 82 83 /* 84 * Set TCR.T0SZ to its default value (based on VA_BITS) 85 */ 86 static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) 87 { 88 unsigned long tcr; 89 90 if (!__cpu_uses_extended_idmap()) 91 return; 92 93 tcr = read_sysreg(tcr_el1); 94 tcr &= ~TCR_T0SZ_MASK; 95 tcr |= t0sz << TCR_T0SZ_OFFSET; 96 write_sysreg(tcr, tcr_el1); 97 isb(); 98 } 99 100 #define cpu_set_default_tcr_t0sz() __cpu_set_tcr_t0sz(TCR_T0SZ(vabits_actual)) 101 #define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz) 102 103 /* 104 * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm. 105 * 106 * The idmap lives in the same VA range as userspace, but uses global entries 107 * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from 108 * speculative TLB fetches, we must temporarily install the reserved page 109 * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ. 110 * 111 * If current is a not a user task, the mm covers the TTBR1_EL1 page tables, 112 * which should not be installed in TTBR0_EL1. In this case we can leave the 113 * reserved page tables in place. 114 */ 115 static inline void cpu_uninstall_idmap(void) 116 { 117 struct mm_struct *mm = current->active_mm; 118 119 cpu_set_reserved_ttbr0(); 120 local_flush_tlb_all(); 121 cpu_set_default_tcr_t0sz(); 122 123 if (mm != &init_mm && !system_uses_ttbr0_pan()) 124 cpu_switch_mm(mm->pgd, mm); 125 } 126 127 static inline void cpu_install_idmap(void) 128 { 129 cpu_set_reserved_ttbr0(); 130 local_flush_tlb_all(); 131 cpu_set_idmap_tcr_t0sz(); 132 133 cpu_switch_mm(lm_alias(idmap_pg_dir), &init_mm); 134 } 135 136 /* 137 * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD, 138 * avoiding the possibility of conflicting TLB entries being allocated. 139 */ 140 static inline void cpu_replace_ttbr1(pgd_t *pgdp) 141 { 142 typedef void (ttbr_replace_func)(phys_addr_t); 143 extern ttbr_replace_func idmap_cpu_replace_ttbr1; 144 ttbr_replace_func *replace_phys; 145 146 /* phys_to_ttbr() zeros lower 2 bits of ttbr with 52-bit PA */ 147 phys_addr_t ttbr1 = phys_to_ttbr(virt_to_phys(pgdp)); 148 149 if (system_supports_cnp() && !WARN_ON(pgdp != lm_alias(swapper_pg_dir))) { 150 /* 151 * cpu_replace_ttbr1() is used when there's a boot CPU 152 * up (i.e. cpufeature framework is not up yet) and 153 * latter only when we enable CNP via cpufeature's 154 * enable() callback. 155 * Also we rely on the cpu_hwcap bit being set before 156 * calling the enable() function. 157 */ 158 ttbr1 |= TTBR_CNP_BIT; 159 } 160 161 replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1); 162 163 cpu_install_idmap(); 164 replace_phys(ttbr1); 165 cpu_uninstall_idmap(); 166 } 167 168 /* 169 * It would be nice to return ASIDs back to the allocator, but unfortunately 170 * that introduces a race with a generation rollover where we could erroneously 171 * free an ASID allocated in a future generation. We could workaround this by 172 * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap), 173 * but we'd then need to make sure that we didn't dirty any TLBs afterwards. 174 * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you 175 * take CPU migration into account. 176 */ 177 void check_and_switch_context(struct mm_struct *mm); 178 179 #define init_new_context(tsk, mm) init_new_context(tsk, mm) 180 static inline int 181 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 182 { 183 atomic64_set(&mm->context.id, 0); 184 refcount_set(&mm->context.pinned, 0); 185 return 0; 186 } 187 188 #ifdef CONFIG_ARM64_SW_TTBR0_PAN 189 static inline void update_saved_ttbr0(struct task_struct *tsk, 190 struct mm_struct *mm) 191 { 192 u64 ttbr; 193 194 if (!system_uses_ttbr0_pan()) 195 return; 196 197 if (mm == &init_mm) 198 ttbr = __pa_symbol(reserved_pg_dir); 199 else 200 ttbr = virt_to_phys(mm->pgd) | ASID(mm) << 48; 201 202 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); 203 } 204 #else 205 static inline void update_saved_ttbr0(struct task_struct *tsk, 206 struct mm_struct *mm) 207 { 208 } 209 #endif 210 211 #define enter_lazy_tlb enter_lazy_tlb 212 static inline void 213 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 214 { 215 /* 216 * We don't actually care about the ttbr0 mapping, so point it at the 217 * zero page. 218 */ 219 update_saved_ttbr0(tsk, &init_mm); 220 } 221 222 static inline void __switch_mm(struct mm_struct *next) 223 { 224 /* 225 * init_mm.pgd does not contain any user mappings and it is always 226 * active for kernel addresses in TTBR1. Just set the reserved TTBR0. 227 */ 228 if (next == &init_mm) { 229 cpu_set_reserved_ttbr0(); 230 return; 231 } 232 233 check_and_switch_context(next); 234 } 235 236 static inline void 237 switch_mm(struct mm_struct *prev, struct mm_struct *next, 238 struct task_struct *tsk) 239 { 240 if (prev != next) 241 __switch_mm(next); 242 243 /* 244 * Update the saved TTBR0_EL1 of the scheduled-in task as the previous 245 * value may have not been initialised yet (activate_mm caller) or the 246 * ASID has changed since the last run (following the context switch 247 * of another thread of the same process). 248 */ 249 update_saved_ttbr0(tsk, next); 250 } 251 252 void verify_cpu_asid_bits(void); 253 void post_ttbr_update_workaround(void); 254 255 unsigned long arm64_mm_context_get(struct mm_struct *mm); 256 void arm64_mm_context_put(struct mm_struct *mm); 257 258 #include <asm-generic/mmu_context.h> 259 260 #endif /* !__ASSEMBLY__ */ 261 262 #endif /* !__ASM_MMU_CONTEXT_H */ 263