1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM64_KVM_MMU_H__ 8 #define __ARM64_KVM_MMU_H__ 9 10 #include <asm/page.h> 11 #include <asm/memory.h> 12 #include <asm/mmu.h> 13 #include <asm/cpufeature.h> 14 15 /* 16 * As ARMv8.0 only has the TTBR0_EL2 register, we cannot express 17 * "negative" addresses. This makes it impossible to directly share 18 * mappings with the kernel. 19 * 20 * Instead, give the HYP mode its own VA region at a fixed offset from 21 * the kernel by just masking the top bits (which are all ones for a 22 * kernel address). We need to find out how many bits to mask. 23 * 24 * We want to build a set of page tables that cover both parts of the 25 * idmap (the trampoline page used to initialize EL2), and our normal 26 * runtime VA space, at the same time. 27 * 28 * Given that the kernel uses VA_BITS for its entire address space, 29 * and that half of that space (VA_BITS - 1) is used for the linear 30 * mapping, we can also limit the EL2 space to (VA_BITS - 1). 31 * 32 * The main question is "Within the VA_BITS space, does EL2 use the 33 * top or the bottom half of that space to shadow the kernel's linear 34 * mapping?". As we need to idmap the trampoline page, this is 35 * determined by the range in which this page lives. 36 * 37 * If the page is in the bottom half, we have to use the top half. If 38 * the page is in the top half, we have to use the bottom half: 39 * 40 * T = __pa_symbol(__hyp_idmap_text_start) 41 * if (T & BIT(VA_BITS - 1)) 42 * HYP_VA_MIN = 0 //idmap in upper half 43 * else 44 * HYP_VA_MIN = 1 << (VA_BITS - 1) 45 * HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1 46 * 47 * When using VHE, there are no separate hyp mappings and all KVM 48 * functionality is already mapped as part of the main kernel 49 * mappings, and none of this applies in that case. 50 */ 51 52 #ifdef __ASSEMBLY__ 53 54 #include <asm/alternative.h> 55 56 /* 57 * Convert a kernel VA into a HYP VA. 58 * reg: VA to be converted. 59 * 60 * The actual code generation takes place in kvm_update_va_mask, and 61 * the instructions below are only there to reserve the space and 62 * perform the register allocation (kvm_update_va_mask uses the 63 * specific registers encoded in the instructions). 64 */ 65 .macro kern_hyp_va reg 66 alternative_cb kvm_update_va_mask 67 and \reg, \reg, #1 /* mask with va_mask */ 68 ror \reg, \reg, #1 /* rotate to the first tag bit */ 69 add \reg, \reg, #0 /* insert the low 12 bits of the tag */ 70 add \reg, \reg, #0, lsl 12 /* insert the top 12 bits of the tag */ 71 ror \reg, \reg, #63 /* rotate back */ 72 alternative_cb_end 73 .endm 74 75 /* 76 * Convert a hypervisor VA to a PA 77 * reg: hypervisor address to be converted in place 78 * tmp: temporary register 79 */ 80 .macro hyp_pa reg, tmp 81 ldr_l \tmp, hyp_physvirt_offset 82 add \reg, \reg, \tmp 83 .endm 84 85 /* 86 * Convert a hypervisor VA to a kernel image address 87 * reg: hypervisor address to be converted in place 88 * tmp: temporary register 89 * 90 * The actual code generation takes place in kvm_get_kimage_voffset, and 91 * the instructions below are only there to reserve the space and 92 * perform the register allocation (kvm_get_kimage_voffset uses the 93 * specific registers encoded in the instructions). 94 */ 95 .macro hyp_kimg_va reg, tmp 96 /* Convert hyp VA -> PA. */ 97 hyp_pa \reg, \tmp 98 99 /* Load kimage_voffset. */ 100 alternative_cb kvm_get_kimage_voffset 101 movz \tmp, #0 102 movk \tmp, #0, lsl #16 103 movk \tmp, #0, lsl #32 104 movk \tmp, #0, lsl #48 105 alternative_cb_end 106 107 /* Convert PA -> kimg VA. */ 108 add \reg, \reg, \tmp 109 .endm 110 111 #else 112 113 #include <linux/pgtable.h> 114 #include <asm/pgalloc.h> 115 #include <asm/cache.h> 116 #include <asm/cacheflush.h> 117 #include <asm/mmu_context.h> 118 119 void kvm_update_va_mask(struct alt_instr *alt, 120 __le32 *origptr, __le32 *updptr, int nr_inst); 121 void kvm_compute_layout(void); 122 void kvm_apply_hyp_relocations(void); 123 124 #define __hyp_pa(x) (((phys_addr_t)(x)) + hyp_physvirt_offset) 125 126 static __always_inline unsigned long __kern_hyp_va(unsigned long v) 127 { 128 asm volatile(ALTERNATIVE_CB("and %0, %0, #1\n" 129 "ror %0, %0, #1\n" 130 "add %0, %0, #0\n" 131 "add %0, %0, #0, lsl 12\n" 132 "ror %0, %0, #63\n", 133 kvm_update_va_mask) 134 : "+r" (v)); 135 return v; 136 } 137 138 #define kern_hyp_va(v) ((typeof(v))(__kern_hyp_va((unsigned long)(v)))) 139 140 /* 141 * We currently support using a VM-specified IPA size. For backward 142 * compatibility, the default IPA size is fixed to 40bits. 143 */ 144 #define KVM_PHYS_SHIFT (40) 145 146 #define kvm_phys_shift(kvm) VTCR_EL2_IPA(kvm->arch.vtcr) 147 #define kvm_phys_size(kvm) (_AC(1, ULL) << kvm_phys_shift(kvm)) 148 #define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL)) 149 150 #include <asm/kvm_pgtable.h> 151 #include <asm/stage2_pgtable.h> 152 153 int kvm_share_hyp(void *from, void *to); 154 void kvm_unshare_hyp(void *from, void *to); 155 int create_hyp_mappings(void *from, void *to, enum kvm_pgtable_prot prot); 156 int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size, 157 void __iomem **kaddr, 158 void __iomem **haddr); 159 int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size, 160 void **haddr); 161 void free_hyp_pgds(void); 162 163 void stage2_unmap_vm(struct kvm *kvm); 164 int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu); 165 void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu); 166 int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa, 167 phys_addr_t pa, unsigned long size, bool writable); 168 169 int kvm_handle_guest_abort(struct kvm_vcpu *vcpu); 170 171 phys_addr_t kvm_mmu_get_httbr(void); 172 phys_addr_t kvm_get_idmap_vector(void); 173 int kvm_mmu_init(u32 *hyp_va_bits); 174 175 static inline void *__kvm_vector_slot2addr(void *base, 176 enum arm64_hyp_spectre_vector slot) 177 { 178 int idx = slot - (slot != HYP_VECTOR_DIRECT); 179 180 return base + (idx * SZ_2K); 181 } 182 183 struct kvm; 184 185 #define kvm_flush_dcache_to_poc(a,l) \ 186 dcache_clean_inval_poc((unsigned long)(a), (unsigned long)(a)+(l)) 187 188 static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) 189 { 190 return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101; 191 } 192 193 static inline void __clean_dcache_guest_page(void *va, size_t size) 194 { 195 /* 196 * With FWB, we ensure that the guest always accesses memory using 197 * cacheable attributes, and we don't have to clean to PoC when 198 * faulting in pages. Furthermore, FWB implies IDC, so cleaning to 199 * PoU is not required either in this case. 200 */ 201 if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 202 return; 203 204 kvm_flush_dcache_to_poc(va, size); 205 } 206 207 static inline void __invalidate_icache_guest_page(void *va, size_t size) 208 { 209 if (icache_is_aliasing()) { 210 /* any kind of VIPT cache */ 211 icache_inval_all_pou(); 212 } else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) { 213 /* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */ 214 icache_inval_pou((unsigned long)va, (unsigned long)va + size); 215 } 216 } 217 218 void kvm_set_way_flush(struct kvm_vcpu *vcpu); 219 void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled); 220 221 static inline unsigned int kvm_get_vmid_bits(void) 222 { 223 int reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 224 225 return get_vmid_bits(reg); 226 } 227 228 /* 229 * We are not in the kvm->srcu critical section most of the time, so we take 230 * the SRCU read lock here. Since we copy the data from the user page, we 231 * can immediately drop the lock again. 232 */ 233 static inline int kvm_read_guest_lock(struct kvm *kvm, 234 gpa_t gpa, void *data, unsigned long len) 235 { 236 int srcu_idx = srcu_read_lock(&kvm->srcu); 237 int ret = kvm_read_guest(kvm, gpa, data, len); 238 239 srcu_read_unlock(&kvm->srcu, srcu_idx); 240 241 return ret; 242 } 243 244 static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa, 245 const void *data, unsigned long len) 246 { 247 int srcu_idx = srcu_read_lock(&kvm->srcu); 248 int ret = kvm_write_guest(kvm, gpa, data, len); 249 250 srcu_read_unlock(&kvm->srcu, srcu_idx); 251 252 return ret; 253 } 254 255 #define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr) 256 257 /* 258 * When this is (directly or indirectly) used on the TLB invalidation 259 * path, we rely on a previously issued DSB so that page table updates 260 * and VMID reads are correctly ordered. 261 */ 262 static __always_inline u64 kvm_get_vttbr(struct kvm_s2_mmu *mmu) 263 { 264 struct kvm_vmid *vmid = &mmu->vmid; 265 u64 vmid_field, baddr; 266 u64 cnp = system_supports_cnp() ? VTTBR_CNP_BIT : 0; 267 268 baddr = mmu->pgd_phys; 269 vmid_field = (u64)READ_ONCE(vmid->vmid) << VTTBR_VMID_SHIFT; 270 return kvm_phys_to_vttbr(baddr) | vmid_field | cnp; 271 } 272 273 /* 274 * Must be called from hyp code running at EL2 with an updated VTTBR 275 * and interrupts disabled. 276 */ 277 static __always_inline void __load_stage2(struct kvm_s2_mmu *mmu, 278 struct kvm_arch *arch) 279 { 280 write_sysreg(arch->vtcr, vtcr_el2); 281 write_sysreg(kvm_get_vttbr(mmu), vttbr_el2); 282 283 /* 284 * ARM errata 1165522 and 1530923 require the actual execution of the 285 * above before we can switch to the EL1/EL0 translation regime used by 286 * the guest. 287 */ 288 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); 289 } 290 291 static inline struct kvm *kvm_s2_mmu_to_kvm(struct kvm_s2_mmu *mmu) 292 { 293 return container_of(mmu->arch, struct kvm, arch); 294 } 295 #endif /* __ASSEMBLY__ */ 296 #endif /* __ARM64_KVM_MMU_H__ */ 297