1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM64_KVM_HYP_H__ 8 #define __ARM64_KVM_HYP_H__ 9 10 #include <linux/compiler.h> 11 #include <linux/kvm_host.h> 12 #include <asm/alternative.h> 13 #include <asm/kvm_mmu.h> 14 #include <asm/sysreg.h> 15 16 #define __hyp_text __section(.hyp.text) notrace 17 18 #define read_sysreg_elx(r,nvh,vh) \ 19 ({ \ 20 u64 reg; \ 21 asm volatile(ALTERNATIVE("mrs %0, " __stringify(r##nvh),\ 22 __mrs_s("%0", r##vh), \ 23 ARM64_HAS_VIRT_HOST_EXTN) \ 24 : "=r" (reg)); \ 25 reg; \ 26 }) 27 28 #define write_sysreg_elx(v,r,nvh,vh) \ 29 do { \ 30 u64 __val = (u64)(v); \ 31 asm volatile(ALTERNATIVE("msr " __stringify(r##nvh) ", %x0",\ 32 __msr_s(r##vh, "%x0"), \ 33 ARM64_HAS_VIRT_HOST_EXTN) \ 34 : : "rZ" (__val)); \ 35 } while (0) 36 37 /* 38 * Unified accessors for registers that have a different encoding 39 * between VHE and non-VHE. They must be specified without their "ELx" 40 * encoding. 41 */ 42 #define read_sysreg_el2(r) \ 43 ({ \ 44 u64 reg; \ 45 asm volatile(ALTERNATIVE("mrs %0, " __stringify(r##_EL2),\ 46 "mrs %0, " __stringify(r##_EL1),\ 47 ARM64_HAS_VIRT_HOST_EXTN) \ 48 : "=r" (reg)); \ 49 reg; \ 50 }) 51 52 #define write_sysreg_el2(v,r) \ 53 do { \ 54 u64 __val = (u64)(v); \ 55 asm volatile(ALTERNATIVE("msr " __stringify(r##_EL2) ", %x0",\ 56 "msr " __stringify(r##_EL1) ", %x0",\ 57 ARM64_HAS_VIRT_HOST_EXTN) \ 58 : : "rZ" (__val)); \ 59 } while (0) 60 61 #define read_sysreg_el0(r) read_sysreg_elx(r, _EL0, _EL02) 62 #define write_sysreg_el0(v,r) write_sysreg_elx(v, r, _EL0, _EL02) 63 #define read_sysreg_el1(r) read_sysreg_elx(r, _EL1, _EL12) 64 #define write_sysreg_el1(v,r) write_sysreg_elx(v, r, _EL1, _EL12) 65 66 /* The VHE specific system registers and their encoding */ 67 #define sctlr_EL12 sys_reg(3, 5, 1, 0, 0) 68 #define cpacr_EL12 sys_reg(3, 5, 1, 0, 2) 69 #define ttbr0_EL12 sys_reg(3, 5, 2, 0, 0) 70 #define ttbr1_EL12 sys_reg(3, 5, 2, 0, 1) 71 #define tcr_EL12 sys_reg(3, 5, 2, 0, 2) 72 #define afsr0_EL12 sys_reg(3, 5, 5, 1, 0) 73 #define afsr1_EL12 sys_reg(3, 5, 5, 1, 1) 74 #define esr_EL12 sys_reg(3, 5, 5, 2, 0) 75 #define far_EL12 sys_reg(3, 5, 6, 0, 0) 76 #define mair_EL12 sys_reg(3, 5, 10, 2, 0) 77 #define amair_EL12 sys_reg(3, 5, 10, 3, 0) 78 #define vbar_EL12 sys_reg(3, 5, 12, 0, 0) 79 #define contextidr_EL12 sys_reg(3, 5, 13, 0, 1) 80 #define cntkctl_EL12 sys_reg(3, 5, 14, 1, 0) 81 #define cntp_tval_EL02 sys_reg(3, 5, 14, 2, 0) 82 #define cntp_ctl_EL02 sys_reg(3, 5, 14, 2, 1) 83 #define cntp_cval_EL02 sys_reg(3, 5, 14, 2, 2) 84 #define cntv_tval_EL02 sys_reg(3, 5, 14, 3, 0) 85 #define cntv_ctl_EL02 sys_reg(3, 5, 14, 3, 1) 86 #define cntv_cval_EL02 sys_reg(3, 5, 14, 3, 2) 87 #define spsr_EL12 sys_reg(3, 5, 4, 0, 0) 88 #define elr_EL12 sys_reg(3, 5, 4, 0, 1) 89 90 /** 91 * hyp_alternate_select - Generates patchable code sequences that are 92 * used to switch between two implementations of a function, depending 93 * on the availability of a feature. 94 * 95 * @fname: a symbol name that will be defined as a function returning a 96 * function pointer whose type will match @orig and @alt 97 * @orig: A pointer to the default function, as returned by @fname when 98 * @cond doesn't hold 99 * @alt: A pointer to the alternate function, as returned by @fname 100 * when @cond holds 101 * @cond: a CPU feature (as described in asm/cpufeature.h) 102 */ 103 #define hyp_alternate_select(fname, orig, alt, cond) \ 104 typeof(orig) * __hyp_text fname(void) \ 105 { \ 106 typeof(alt) *val = orig; \ 107 asm volatile(ALTERNATIVE("nop \n", \ 108 "mov %0, %1 \n", \ 109 cond) \ 110 : "+r" (val) : "r" (alt)); \ 111 return val; \ 112 } 113 114 int __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu); 115 116 void __vgic_v3_save_state(struct kvm_vcpu *vcpu); 117 void __vgic_v3_restore_state(struct kvm_vcpu *vcpu); 118 void __vgic_v3_activate_traps(struct kvm_vcpu *vcpu); 119 void __vgic_v3_deactivate_traps(struct kvm_vcpu *vcpu); 120 void __vgic_v3_save_aprs(struct kvm_vcpu *vcpu); 121 void __vgic_v3_restore_aprs(struct kvm_vcpu *vcpu); 122 int __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu); 123 124 void __timer_enable_traps(struct kvm_vcpu *vcpu); 125 void __timer_disable_traps(struct kvm_vcpu *vcpu); 126 127 void __sysreg_save_state_nvhe(struct kvm_cpu_context *ctxt); 128 void __sysreg_restore_state_nvhe(struct kvm_cpu_context *ctxt); 129 void sysreg_save_host_state_vhe(struct kvm_cpu_context *ctxt); 130 void sysreg_restore_host_state_vhe(struct kvm_cpu_context *ctxt); 131 void sysreg_save_guest_state_vhe(struct kvm_cpu_context *ctxt); 132 void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt); 133 void __sysreg32_save_state(struct kvm_vcpu *vcpu); 134 void __sysreg32_restore_state(struct kvm_vcpu *vcpu); 135 136 void __debug_switch_to_guest(struct kvm_vcpu *vcpu); 137 void __debug_switch_to_host(struct kvm_vcpu *vcpu); 138 139 void __fpsimd_save_state(struct user_fpsimd_state *fp_regs); 140 void __fpsimd_restore_state(struct user_fpsimd_state *fp_regs); 141 142 void activate_traps_vhe_load(struct kvm_vcpu *vcpu); 143 void deactivate_traps_vhe_put(void); 144 145 u64 __guest_enter(struct kvm_vcpu *vcpu, struct kvm_cpu_context *host_ctxt); 146 void __noreturn __hyp_do_panic(unsigned long, ...); 147 148 /* 149 * Must be called from hyp code running at EL2 with an updated VTTBR 150 * and interrupts disabled. 151 */ 152 static __always_inline void __hyp_text __load_guest_stage2(struct kvm *kvm) 153 { 154 write_sysreg(kvm->arch.vtcr, vtcr_el2); 155 write_sysreg(kvm_get_vttbr(kvm), vttbr_el2); 156 157 /* 158 * ARM erratum 1165522 requires the actual execution of the above 159 * before we can switch to the EL1/EL0 translation regime used by 160 * the guest. 161 */ 162 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_1165522)); 163 } 164 165 #endif /* __ARM64_KVM_HYP_H__ */ 166 167