1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/bitmap.h> 15 #include <linux/types.h> 16 #include <linux/jump_label.h> 17 #include <linux/kvm_types.h> 18 #include <linux/percpu.h> 19 #include <asm/arch_gicv3.h> 20 #include <asm/barrier.h> 21 #include <asm/cpufeature.h> 22 #include <asm/cputype.h> 23 #include <asm/daifflags.h> 24 #include <asm/fpsimd.h> 25 #include <asm/kvm.h> 26 #include <asm/kvm_asm.h> 27 #include <asm/thread_info.h> 28 29 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 30 31 #define KVM_USER_MEM_SLOTS 512 32 #define KVM_HALT_POLL_NS_DEFAULT 500000 33 34 #include <kvm/arm_vgic.h> 35 #include <kvm/arm_arch_timer.h> 36 #include <kvm/arm_pmu.h> 37 38 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 39 40 #define KVM_VCPU_MAX_FEATURES 7 41 42 #define KVM_REQ_SLEEP \ 43 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 44 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 45 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 46 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 47 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 48 49 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 50 KVM_DIRTY_LOG_INITIALLY_SET) 51 52 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 53 54 extern unsigned int kvm_sve_max_vl; 55 int kvm_arm_init_sve(void); 56 57 int __attribute_const__ kvm_target_cpu(void); 58 int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 59 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 60 int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext); 61 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start); 62 63 struct kvm_vmid { 64 /* The VMID generation used for the virt. memory system */ 65 u64 vmid_gen; 66 u32 vmid; 67 }; 68 69 struct kvm_arch { 70 struct kvm_vmid vmid; 71 72 /* stage2 entry level table */ 73 pgd_t *pgd; 74 phys_addr_t pgd_phys; 75 76 /* VTCR_EL2 value for this VM */ 77 u64 vtcr; 78 79 /* The last vcpu id that ran on each physical CPU */ 80 int __percpu *last_vcpu_ran; 81 82 /* The maximum number of vCPUs depends on the used GIC model */ 83 int max_vcpus; 84 85 /* Interrupt controller */ 86 struct vgic_dist vgic; 87 88 /* Mandated version of PSCI */ 89 u32 psci_version; 90 91 /* 92 * If we encounter a data abort without valid instruction syndrome 93 * information, report this to user space. User space can (and 94 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 95 * supported. 96 */ 97 bool return_nisv_io_abort_to_user; 98 }; 99 100 struct kvm_vcpu_fault_info { 101 u32 esr_el2; /* Hyp Syndrom Register */ 102 u64 far_el2; /* Hyp Fault Address Register */ 103 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 104 u64 disr_el1; /* Deferred [SError] Status Register */ 105 }; 106 107 enum vcpu_sysreg { 108 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 109 MPIDR_EL1, /* MultiProcessor Affinity Register */ 110 CSSELR_EL1, /* Cache Size Selection Register */ 111 SCTLR_EL1, /* System Control Register */ 112 ACTLR_EL1, /* Auxiliary Control Register */ 113 CPACR_EL1, /* Coprocessor Access Control */ 114 ZCR_EL1, /* SVE Control */ 115 TTBR0_EL1, /* Translation Table Base Register 0 */ 116 TTBR1_EL1, /* Translation Table Base Register 1 */ 117 TCR_EL1, /* Translation Control Register */ 118 ESR_EL1, /* Exception Syndrome Register */ 119 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ 120 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ 121 FAR_EL1, /* Fault Address Register */ 122 MAIR_EL1, /* Memory Attribute Indirection Register */ 123 VBAR_EL1, /* Vector Base Address Register */ 124 CONTEXTIDR_EL1, /* Context ID Register */ 125 TPIDR_EL0, /* Thread ID, User R/W */ 126 TPIDRRO_EL0, /* Thread ID, User R/O */ 127 TPIDR_EL1, /* Thread ID, Privileged */ 128 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ 129 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 130 PAR_EL1, /* Physical Address Register */ 131 MDSCR_EL1, /* Monitor Debug System Control Register */ 132 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 133 DISR_EL1, /* Deferred Interrupt Status Register */ 134 135 /* Performance Monitors Registers */ 136 PMCR_EL0, /* Control Register */ 137 PMSELR_EL0, /* Event Counter Selection Register */ 138 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 139 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 140 PMCCNTR_EL0, /* Cycle Counter Register */ 141 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 142 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 143 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 144 PMCNTENSET_EL0, /* Count Enable Set Register */ 145 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 146 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 147 PMSWINC_EL0, /* Software Increment Register */ 148 PMUSERENR_EL0, /* User Enable Register */ 149 150 /* Pointer Authentication Registers in a strict increasing order. */ 151 APIAKEYLO_EL1, 152 APIAKEYHI_EL1, 153 APIBKEYLO_EL1, 154 APIBKEYHI_EL1, 155 APDAKEYLO_EL1, 156 APDAKEYHI_EL1, 157 APDBKEYLO_EL1, 158 APDBKEYHI_EL1, 159 APGAKEYLO_EL1, 160 APGAKEYHI_EL1, 161 162 /* 32bit specific registers. Keep them at the end of the range */ 163 DACR32_EL2, /* Domain Access Control Register */ 164 IFSR32_EL2, /* Instruction Fault Status Register */ 165 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 166 DBGVCR32_EL2, /* Debug Vector Catch Register */ 167 168 NR_SYS_REGS /* Nothing after this line! */ 169 }; 170 171 /* 32bit mapping */ 172 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ 173 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ 174 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ 175 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ 176 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ 177 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ 178 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ 179 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ 180 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ 181 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ 182 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ 183 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ 184 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ 185 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ 186 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ 187 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ 188 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ 189 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ 190 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ 191 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ 192 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ 193 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ 194 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ 195 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ 196 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ 197 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ 198 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ 199 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ 200 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ 201 202 #define cp14_DBGDSCRext (MDSCR_EL1 * 2) 203 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) 204 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) 205 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) 206 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) 207 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) 208 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2) 209 210 #define NR_COPRO_REGS (NR_SYS_REGS * 2) 211 212 struct kvm_cpu_context { 213 struct kvm_regs gp_regs; 214 union { 215 u64 sys_regs[NR_SYS_REGS]; 216 u32 copro[NR_COPRO_REGS]; 217 }; 218 219 struct kvm_vcpu *__hyp_running_vcpu; 220 }; 221 222 struct kvm_pmu_events { 223 u32 events_host; 224 u32 events_guest; 225 }; 226 227 struct kvm_host_data { 228 struct kvm_cpu_context host_ctxt; 229 struct kvm_pmu_events pmu_events; 230 }; 231 232 typedef struct kvm_host_data kvm_host_data_t; 233 234 struct vcpu_reset_state { 235 unsigned long pc; 236 unsigned long r0; 237 bool be; 238 bool reset; 239 }; 240 241 struct kvm_vcpu_arch { 242 struct kvm_cpu_context ctxt; 243 void *sve_state; 244 unsigned int sve_max_vl; 245 246 /* HYP configuration */ 247 u64 hcr_el2; 248 u32 mdcr_el2; 249 250 /* Exception Information */ 251 struct kvm_vcpu_fault_info fault; 252 253 /* State of various workarounds, see kvm_asm.h for bit assignment */ 254 u64 workaround_flags; 255 256 /* Miscellaneous vcpu state flags */ 257 u64 flags; 258 259 /* 260 * We maintain more than a single set of debug registers to support 261 * debugging the guest from the host and to maintain separate host and 262 * guest state during world switches. vcpu_debug_state are the debug 263 * registers of the vcpu as the guest sees them. host_debug_state are 264 * the host registers which are saved and restored during 265 * world switches. external_debug_state contains the debug 266 * values we want to debug the guest. This is set via the 267 * KVM_SET_GUEST_DEBUG ioctl. 268 * 269 * debug_ptr points to the set of debug registers that should be loaded 270 * onto the hardware when running the guest. 271 */ 272 struct kvm_guest_debug_arch *debug_ptr; 273 struct kvm_guest_debug_arch vcpu_debug_state; 274 struct kvm_guest_debug_arch external_debug_state; 275 276 struct thread_info *host_thread_info; /* hyp VA */ 277 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ 278 279 struct { 280 /* {Break,watch}point registers */ 281 struct kvm_guest_debug_arch regs; 282 /* Statistical profiling extension */ 283 u64 pmscr_el1; 284 } host_debug_state; 285 286 /* VGIC state */ 287 struct vgic_cpu vgic_cpu; 288 struct arch_timer_cpu timer_cpu; 289 struct kvm_pmu pmu; 290 291 /* 292 * Anything that is not used directly from assembly code goes 293 * here. 294 */ 295 296 /* 297 * Guest registers we preserve during guest debugging. 298 * 299 * These shadow registers are updated by the kvm_handle_sys_reg 300 * trap handler if the guest accesses or updates them while we 301 * are using guest debug. 302 */ 303 struct { 304 u32 mdscr_el1; 305 } guest_debug_preserved; 306 307 /* vcpu power-off state */ 308 bool power_off; 309 310 /* Don't run the guest (internal implementation need) */ 311 bool pause; 312 313 /* Cache some mmu pages needed inside spinlock regions */ 314 struct kvm_mmu_memory_cache mmu_page_cache; 315 316 /* Target CPU and feature flags */ 317 int target; 318 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); 319 320 /* Detect first run of a vcpu */ 321 bool has_run_once; 322 323 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 324 u64 vsesr_el2; 325 326 /* Additional reset state */ 327 struct vcpu_reset_state reset_state; 328 329 /* True when deferrable sysregs are loaded on the physical CPU, 330 * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */ 331 bool sysregs_loaded_on_cpu; 332 333 /* Guest PV state */ 334 struct { 335 u64 steal; 336 u64 last_steal; 337 gpa_t base; 338 } steal; 339 }; 340 341 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 342 #define vcpu_sve_pffr(vcpu) ((void *)((char *)((vcpu)->arch.sve_state) + \ 343 sve_ffr_offset((vcpu)->arch.sve_max_vl))) 344 345 #define vcpu_sve_state_size(vcpu) ({ \ 346 size_t __size_ret; \ 347 unsigned int __vcpu_vq; \ 348 \ 349 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ 350 __size_ret = 0; \ 351 } else { \ 352 __vcpu_vq = sve_vq_from_vl((vcpu)->arch.sve_max_vl); \ 353 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ 354 } \ 355 \ 356 __size_ret; \ 357 }) 358 359 /* vcpu_arch flags field values: */ 360 #define KVM_ARM64_DEBUG_DIRTY (1 << 0) 361 #define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */ 362 #define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */ 363 #define KVM_ARM64_HOST_SVE_IN_USE (1 << 3) /* backup for host TIF_SVE */ 364 #define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */ 365 #define KVM_ARM64_GUEST_HAS_SVE (1 << 5) /* SVE exposed to guest */ 366 #define KVM_ARM64_VCPU_SVE_FINALIZED (1 << 6) /* SVE config completed */ 367 #define KVM_ARM64_GUEST_HAS_PTRAUTH (1 << 7) /* PTRAUTH exposed to guest */ 368 369 #define vcpu_has_sve(vcpu) (system_supports_sve() && \ 370 ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_SVE)) 371 372 #ifdef CONFIG_ARM64_PTR_AUTH 373 #define vcpu_has_ptrauth(vcpu) \ 374 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 375 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 376 (vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_PTRAUTH) 377 #else 378 #define vcpu_has_ptrauth(vcpu) false 379 #endif 380 381 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs) 382 383 /* 384 * Only use __vcpu_sys_reg if you know you want the memory backed version of a 385 * register, and not the one most recently accessed by a running VCPU. For 386 * example, for userspace access or for system registers that are never context 387 * switched, but only emulated. 388 */ 389 #define __vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) 390 391 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 392 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 393 394 /* 395 * CP14 and CP15 live in the same array, as they are backed by the 396 * same system registers. 397 */ 398 #define CPx_BIAS IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) 399 400 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r) ^ CPx_BIAS]) 401 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r) ^ CPx_BIAS]) 402 403 struct kvm_vm_stat { 404 ulong remote_tlb_flush; 405 }; 406 407 struct kvm_vcpu_stat { 408 u64 halt_successful_poll; 409 u64 halt_attempted_poll; 410 u64 halt_poll_success_ns; 411 u64 halt_poll_fail_ns; 412 u64 halt_poll_invalid; 413 u64 halt_wakeup; 414 u64 hvc_exit_stat; 415 u64 wfe_exit_stat; 416 u64 wfi_exit_stat; 417 u64 mmio_exit_user; 418 u64 mmio_exit_kernel; 419 u64 exits; 420 }; 421 422 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 423 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 424 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 425 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 426 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 427 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 428 struct kvm_vcpu_events *events); 429 430 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 431 struct kvm_vcpu_events *events); 432 433 #define KVM_ARCH_WANT_MMU_NOTIFIER 434 int kvm_unmap_hva_range(struct kvm *kvm, 435 unsigned long start, unsigned long end); 436 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 437 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 438 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 439 440 void kvm_arm_halt_guest(struct kvm *kvm); 441 void kvm_arm_resume_guest(struct kvm *kvm); 442 443 u64 __kvm_call_hyp(void *hypfn, ...); 444 445 /* 446 * The couple of isb() below are there to guarantee the same behaviour 447 * on VHE as on !VHE, where the eret to EL1 acts as a context 448 * synchronization event. 449 */ 450 #define kvm_call_hyp(f, ...) \ 451 do { \ 452 if (has_vhe()) { \ 453 f(__VA_ARGS__); \ 454 isb(); \ 455 } else { \ 456 __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__); \ 457 } \ 458 } while(0) 459 460 #define kvm_call_hyp_ret(f, ...) \ 461 ({ \ 462 typeof(f(__VA_ARGS__)) ret; \ 463 \ 464 if (has_vhe()) { \ 465 ret = f(__VA_ARGS__); \ 466 isb(); \ 467 } else { \ 468 ret = __kvm_call_hyp(kvm_ksym_ref(f), \ 469 ##__VA_ARGS__); \ 470 } \ 471 \ 472 ret; \ 473 }) 474 475 void force_vm_exit(const cpumask_t *mask); 476 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); 477 478 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 479 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 480 481 /* MMIO helpers */ 482 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 483 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 484 485 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 486 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 487 488 int kvm_perf_init(void); 489 int kvm_perf_teardown(void); 490 491 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 492 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 493 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 494 495 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 496 struct kvm_device_attr *attr); 497 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 498 struct kvm_device_attr *attr); 499 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 500 struct kvm_device_attr *attr); 501 502 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 503 { 504 vcpu_arch->steal.base = GPA_INVALID; 505 } 506 507 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 508 { 509 return (vcpu_arch->steal.base != GPA_INVALID); 510 } 511 512 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); 513 514 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 515 516 DECLARE_PER_CPU(kvm_host_data_t, kvm_host_data); 517 518 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 519 { 520 /* The host's MPIDR is immutable, so let's set it up at boot time */ 521 cpu_ctxt->sys_regs[MPIDR_EL1] = read_cpuid_mpidr(); 522 } 523 524 static inline bool kvm_arch_requires_vhe(void) 525 { 526 /* 527 * The Arm architecture specifies that implementation of SVE 528 * requires VHE also to be implemented. The KVM code for arm64 529 * relies on this when SVE is present: 530 */ 531 if (system_supports_sve()) 532 return true; 533 534 return false; 535 } 536 537 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu); 538 539 static inline void kvm_arch_hardware_unsetup(void) {} 540 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 541 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 542 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 543 544 void kvm_arm_init_debug(void); 545 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 546 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 547 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 548 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 549 struct kvm_device_attr *attr); 550 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 551 struct kvm_device_attr *attr); 552 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 553 struct kvm_device_attr *attr); 554 555 /* Guest/host FPSIMD coordination helpers */ 556 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); 557 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 558 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 559 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 560 561 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 562 { 563 return (!has_vhe() && attr->exclude_host); 564 } 565 566 #ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */ 567 static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) 568 { 569 return kvm_arch_vcpu_run_map_fp(vcpu); 570 } 571 572 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); 573 void kvm_clr_pmu_events(u32 clr); 574 575 void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu); 576 void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); 577 #else 578 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} 579 static inline void kvm_clr_pmu_events(u32 clr) {} 580 #endif 581 582 #define KVM_BP_HARDEN_UNKNOWN -1 583 #define KVM_BP_HARDEN_WA_NEEDED 0 584 #define KVM_BP_HARDEN_NOT_REQUIRED 1 585 586 static inline int kvm_arm_harden_branch_predictor(void) 587 { 588 switch (get_spectre_v2_workaround_state()) { 589 case ARM64_BP_HARDEN_WA_NEEDED: 590 return KVM_BP_HARDEN_WA_NEEDED; 591 case ARM64_BP_HARDEN_NOT_REQUIRED: 592 return KVM_BP_HARDEN_NOT_REQUIRED; 593 case ARM64_BP_HARDEN_UNKNOWN: 594 default: 595 return KVM_BP_HARDEN_UNKNOWN; 596 } 597 } 598 599 #define KVM_SSBD_UNKNOWN -1 600 #define KVM_SSBD_FORCE_DISABLE 0 601 #define KVM_SSBD_KERNEL 1 602 #define KVM_SSBD_FORCE_ENABLE 2 603 #define KVM_SSBD_MITIGATED 3 604 605 static inline int kvm_arm_have_ssbd(void) 606 { 607 switch (arm64_get_ssbd_state()) { 608 case ARM64_SSBD_FORCE_DISABLE: 609 return KVM_SSBD_FORCE_DISABLE; 610 case ARM64_SSBD_KERNEL: 611 return KVM_SSBD_KERNEL; 612 case ARM64_SSBD_FORCE_ENABLE: 613 return KVM_SSBD_FORCE_ENABLE; 614 case ARM64_SSBD_MITIGATED: 615 return KVM_SSBD_MITIGATED; 616 case ARM64_SSBD_UNKNOWN: 617 default: 618 return KVM_SSBD_UNKNOWN; 619 } 620 } 621 622 void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu); 623 void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu); 624 625 int kvm_set_ipa_limit(void); 626 627 #define __KVM_HAVE_ARCH_VM_ALLOC 628 struct kvm *kvm_arch_alloc_vm(void); 629 void kvm_arch_free_vm(struct kvm *kvm); 630 631 int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type); 632 633 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 634 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 635 636 #define kvm_arm_vcpu_sve_finalized(vcpu) \ 637 ((vcpu)->arch.flags & KVM_ARM64_VCPU_SVE_FINALIZED) 638 639 #endif /* __ARM64_KVM_HOST_H__ */ 640