1 /* 2 * Copyright (C) 2012,2013 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * Derived from arch/arm/include/asm/kvm_host.h: 6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 7 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef __ARM64_KVM_HOST_H__ 23 #define __ARM64_KVM_HOST_H__ 24 25 #include <linux/types.h> 26 #include <linux/kvm_types.h> 27 #include <asm/kvm.h> 28 #include <asm/kvm_mmio.h> 29 30 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 31 32 #define KVM_USER_MEM_SLOTS 32 33 #define KVM_PRIVATE_MEM_SLOTS 4 34 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 35 #define KVM_HALT_POLL_NS_DEFAULT 500000 36 37 #include <kvm/arm_vgic.h> 38 #include <kvm/arm_arch_timer.h> 39 40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 41 42 #define KVM_VCPU_MAX_FEATURES 3 43 44 int __attribute_const__ kvm_target_cpu(void); 45 int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 46 int kvm_arch_dev_ioctl_check_extension(long ext); 47 48 struct kvm_arch { 49 /* The VMID generation used for the virt. memory system */ 50 u64 vmid_gen; 51 u32 vmid; 52 53 /* 1-level 2nd stage table and lock */ 54 spinlock_t pgd_lock; 55 pgd_t *pgd; 56 57 /* VTTBR value associated with above pgd and vmid */ 58 u64 vttbr; 59 60 /* The maximum number of vCPUs depends on the used GIC model */ 61 int max_vcpus; 62 63 /* Interrupt controller */ 64 struct vgic_dist vgic; 65 66 /* Timer */ 67 struct arch_timer_kvm timer; 68 }; 69 70 #define KVM_NR_MEM_OBJS 40 71 72 /* 73 * We don't want allocation failures within the mmu code, so we preallocate 74 * enough memory for a single page fault in a cache. 75 */ 76 struct kvm_mmu_memory_cache { 77 int nobjs; 78 void *objects[KVM_NR_MEM_OBJS]; 79 }; 80 81 struct kvm_vcpu_fault_info { 82 u32 esr_el2; /* Hyp Syndrom Register */ 83 u64 far_el2; /* Hyp Fault Address Register */ 84 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 85 }; 86 87 /* 88 * 0 is reserved as an invalid value. 89 * Order should be kept in sync with the save/restore code. 90 */ 91 enum vcpu_sysreg { 92 __INVALID_SYSREG__, 93 MPIDR_EL1, /* MultiProcessor Affinity Register */ 94 CSSELR_EL1, /* Cache Size Selection Register */ 95 SCTLR_EL1, /* System Control Register */ 96 ACTLR_EL1, /* Auxiliary Control Register */ 97 CPACR_EL1, /* Coprocessor Access Control */ 98 TTBR0_EL1, /* Translation Table Base Register 0 */ 99 TTBR1_EL1, /* Translation Table Base Register 1 */ 100 TCR_EL1, /* Translation Control Register */ 101 ESR_EL1, /* Exception Syndrome Register */ 102 AFSR0_EL1, /* Auxilary Fault Status Register 0 */ 103 AFSR1_EL1, /* Auxilary Fault Status Register 1 */ 104 FAR_EL1, /* Fault Address Register */ 105 MAIR_EL1, /* Memory Attribute Indirection Register */ 106 VBAR_EL1, /* Vector Base Address Register */ 107 CONTEXTIDR_EL1, /* Context ID Register */ 108 TPIDR_EL0, /* Thread ID, User R/W */ 109 TPIDRRO_EL0, /* Thread ID, User R/O */ 110 TPIDR_EL1, /* Thread ID, Privileged */ 111 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ 112 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 113 PAR_EL1, /* Physical Address Register */ 114 MDSCR_EL1, /* Monitor Debug System Control Register */ 115 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 116 117 /* 32bit specific registers. Keep them at the end of the range */ 118 DACR32_EL2, /* Domain Access Control Register */ 119 IFSR32_EL2, /* Instruction Fault Status Register */ 120 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 121 DBGVCR32_EL2, /* Debug Vector Catch Register */ 122 123 NR_SYS_REGS /* Nothing after this line! */ 124 }; 125 126 /* 32bit mapping */ 127 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ 128 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ 129 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ 130 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ 131 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ 132 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ 133 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ 134 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ 135 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ 136 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ 137 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ 138 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ 139 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ 140 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ 141 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ 142 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ 143 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ 144 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ 145 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ 146 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ 147 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ 148 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ 149 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ 150 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ 151 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ 152 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ 153 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ 154 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ 155 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ 156 157 #define cp14_DBGDSCRext (MDSCR_EL1 * 2) 158 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) 159 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) 160 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) 161 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) 162 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) 163 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2) 164 165 #define NR_COPRO_REGS (NR_SYS_REGS * 2) 166 167 struct kvm_cpu_context { 168 struct kvm_regs gp_regs; 169 union { 170 u64 sys_regs[NR_SYS_REGS]; 171 u32 copro[NR_COPRO_REGS]; 172 }; 173 }; 174 175 typedef struct kvm_cpu_context kvm_cpu_context_t; 176 177 struct kvm_vcpu_arch { 178 struct kvm_cpu_context ctxt; 179 180 /* HYP configuration */ 181 u64 hcr_el2; 182 u32 mdcr_el2; 183 184 /* Exception Information */ 185 struct kvm_vcpu_fault_info fault; 186 187 /* Guest debug state */ 188 u64 debug_flags; 189 190 /* 191 * We maintain more than a single set of debug registers to support 192 * debugging the guest from the host and to maintain separate host and 193 * guest state during world switches. vcpu_debug_state are the debug 194 * registers of the vcpu as the guest sees them. host_debug_state are 195 * the host registers which are saved and restored during 196 * world switches. external_debug_state contains the debug 197 * values we want to debug the guest. This is set via the 198 * KVM_SET_GUEST_DEBUG ioctl. 199 * 200 * debug_ptr points to the set of debug registers that should be loaded 201 * onto the hardware when running the guest. 202 */ 203 struct kvm_guest_debug_arch *debug_ptr; 204 struct kvm_guest_debug_arch vcpu_debug_state; 205 struct kvm_guest_debug_arch external_debug_state; 206 207 /* Pointer to host CPU context */ 208 kvm_cpu_context_t *host_cpu_context; 209 struct kvm_guest_debug_arch host_debug_state; 210 211 /* VGIC state */ 212 struct vgic_cpu vgic_cpu; 213 struct arch_timer_cpu timer_cpu; 214 215 /* 216 * Anything that is not used directly from assembly code goes 217 * here. 218 */ 219 220 /* 221 * Guest registers we preserve during guest debugging. 222 * 223 * These shadow registers are updated by the kvm_handle_sys_reg 224 * trap handler if the guest accesses or updates them while we 225 * are using guest debug. 226 */ 227 struct { 228 u32 mdscr_el1; 229 } guest_debug_preserved; 230 231 /* vcpu power-off state */ 232 bool power_off; 233 234 /* Don't run the guest (internal implementation need) */ 235 bool pause; 236 237 /* IO related fields */ 238 struct kvm_decode mmio_decode; 239 240 /* Interrupt related fields */ 241 u64 irq_lines; /* IRQ and FIQ levels */ 242 243 /* Cache some mmu pages needed inside spinlock regions */ 244 struct kvm_mmu_memory_cache mmu_page_cache; 245 246 /* Target CPU and feature flags */ 247 int target; 248 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); 249 250 /* Detect first run of a vcpu */ 251 bool has_run_once; 252 }; 253 254 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs) 255 #define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) 256 /* 257 * CP14 and CP15 live in the same array, as they are backed by the 258 * same system registers. 259 */ 260 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)]) 261 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)]) 262 263 #ifdef CONFIG_CPU_BIG_ENDIAN 264 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r)) 265 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r) + 1) 266 #else 267 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r) + 1) 268 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r)) 269 #endif 270 271 struct kvm_vm_stat { 272 u32 remote_tlb_flush; 273 }; 274 275 struct kvm_vcpu_stat { 276 u32 halt_successful_poll; 277 u32 halt_attempted_poll; 278 u32 halt_wakeup; 279 u32 hvc_exit_stat; 280 u64 wfe_exit_stat; 281 u64 wfi_exit_stat; 282 u64 mmio_exit_user; 283 u64 mmio_exit_kernel; 284 u64 exits; 285 }; 286 287 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 288 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 289 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 290 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 291 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 292 293 #define KVM_ARCH_WANT_MMU_NOTIFIER 294 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); 295 int kvm_unmap_hva_range(struct kvm *kvm, 296 unsigned long start, unsigned long end); 297 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 298 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 299 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 300 301 /* We do not have shadow page tables, hence the empty hooks */ 302 static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 303 unsigned long address) 304 { 305 } 306 307 struct kvm_vcpu *kvm_arm_get_running_vcpu(void); 308 struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void); 309 310 u64 kvm_call_hyp(void *hypfn, ...); 311 void force_vm_exit(const cpumask_t *mask); 312 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); 313 314 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, 315 int exception_index); 316 317 int kvm_perf_init(void); 318 int kvm_perf_teardown(void); 319 320 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 321 322 static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr, 323 phys_addr_t pgd_ptr, 324 unsigned long hyp_stack_ptr, 325 unsigned long vector_ptr) 326 { 327 /* 328 * Call initialization code, and switch to the full blown 329 * HYP code. 330 */ 331 kvm_call_hyp((void *)boot_pgd_ptr, pgd_ptr, 332 hyp_stack_ptr, vector_ptr); 333 } 334 335 static inline void kvm_arch_hardware_disable(void) {} 336 static inline void kvm_arch_hardware_unsetup(void) {} 337 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 338 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} 339 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 340 341 void kvm_arm_init_debug(void); 342 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 343 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 344 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 345 346 #endif /* __ARM64_KVM_HOST_H__ */ 347