1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/bitmap.h> 15 #include <linux/types.h> 16 #include <linux/jump_label.h> 17 #include <linux/kvm_types.h> 18 #include <linux/percpu.h> 19 #include <asm/arch_gicv3.h> 20 #include <asm/barrier.h> 21 #include <asm/cpufeature.h> 22 #include <asm/cputype.h> 23 #include <asm/daifflags.h> 24 #include <asm/fpsimd.h> 25 #include <asm/kvm.h> 26 #include <asm/kvm_asm.h> 27 #include <asm/thread_info.h> 28 29 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 30 31 #define KVM_USER_MEM_SLOTS 512 32 #define KVM_HALT_POLL_NS_DEFAULT 500000 33 34 #include <kvm/arm_vgic.h> 35 #include <kvm/arm_arch_timer.h> 36 #include <kvm/arm_pmu.h> 37 38 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 39 40 #define KVM_VCPU_MAX_FEATURES 7 41 42 #define KVM_REQ_SLEEP \ 43 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 44 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 45 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 46 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 47 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 48 49 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 50 KVM_DIRTY_LOG_INITIALLY_SET) 51 52 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 53 54 extern unsigned int kvm_sve_max_vl; 55 int kvm_arm_init_sve(void); 56 57 int __attribute_const__ kvm_target_cpu(void); 58 int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 59 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 60 int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext); 61 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start); 62 63 struct kvm_vmid { 64 /* The VMID generation used for the virt. memory system */ 65 u64 vmid_gen; 66 u32 vmid; 67 }; 68 69 struct kvm_s2_mmu { 70 struct kvm_vmid vmid; 71 72 /* 73 * stage2 entry level table 74 * 75 * Two kvm_s2_mmu structures in the same VM can point to the same 76 * pgd here. This happens when running a guest using a 77 * translation regime that isn't affected by its own stage-2 78 * translation, such as a non-VHE hypervisor running at vEL2, or 79 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 80 * canonical stage-2 page tables. 81 */ 82 pgd_t *pgd; 83 phys_addr_t pgd_phys; 84 85 /* The last vcpu id that ran on each physical CPU */ 86 int __percpu *last_vcpu_ran; 87 88 struct kvm *kvm; 89 }; 90 91 struct kvm_arch { 92 struct kvm_s2_mmu mmu; 93 94 /* VTCR_EL2 value for this VM */ 95 u64 vtcr; 96 97 /* The maximum number of vCPUs depends on the used GIC model */ 98 int max_vcpus; 99 100 /* Interrupt controller */ 101 struct vgic_dist vgic; 102 103 /* Mandated version of PSCI */ 104 u32 psci_version; 105 106 /* 107 * If we encounter a data abort without valid instruction syndrome 108 * information, report this to user space. User space can (and 109 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 110 * supported. 111 */ 112 bool return_nisv_io_abort_to_user; 113 }; 114 115 struct kvm_vcpu_fault_info { 116 u32 esr_el2; /* Hyp Syndrom Register */ 117 u64 far_el2; /* Hyp Fault Address Register */ 118 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 119 u64 disr_el1; /* Deferred [SError] Status Register */ 120 }; 121 122 enum vcpu_sysreg { 123 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 124 MPIDR_EL1, /* MultiProcessor Affinity Register */ 125 CSSELR_EL1, /* Cache Size Selection Register */ 126 SCTLR_EL1, /* System Control Register */ 127 ACTLR_EL1, /* Auxiliary Control Register */ 128 CPACR_EL1, /* Coprocessor Access Control */ 129 ZCR_EL1, /* SVE Control */ 130 TTBR0_EL1, /* Translation Table Base Register 0 */ 131 TTBR1_EL1, /* Translation Table Base Register 1 */ 132 TCR_EL1, /* Translation Control Register */ 133 ESR_EL1, /* Exception Syndrome Register */ 134 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ 135 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ 136 FAR_EL1, /* Fault Address Register */ 137 MAIR_EL1, /* Memory Attribute Indirection Register */ 138 VBAR_EL1, /* Vector Base Address Register */ 139 CONTEXTIDR_EL1, /* Context ID Register */ 140 TPIDR_EL0, /* Thread ID, User R/W */ 141 TPIDRRO_EL0, /* Thread ID, User R/O */ 142 TPIDR_EL1, /* Thread ID, Privileged */ 143 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ 144 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 145 PAR_EL1, /* Physical Address Register */ 146 MDSCR_EL1, /* Monitor Debug System Control Register */ 147 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 148 DISR_EL1, /* Deferred Interrupt Status Register */ 149 150 /* Performance Monitors Registers */ 151 PMCR_EL0, /* Control Register */ 152 PMSELR_EL0, /* Event Counter Selection Register */ 153 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 154 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 155 PMCCNTR_EL0, /* Cycle Counter Register */ 156 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 157 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 158 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 159 PMCNTENSET_EL0, /* Count Enable Set Register */ 160 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 161 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 162 PMSWINC_EL0, /* Software Increment Register */ 163 PMUSERENR_EL0, /* User Enable Register */ 164 165 /* Pointer Authentication Registers in a strict increasing order. */ 166 APIAKEYLO_EL1, 167 APIAKEYHI_EL1, 168 APIBKEYLO_EL1, 169 APIBKEYHI_EL1, 170 APDAKEYLO_EL1, 171 APDAKEYHI_EL1, 172 APDBKEYLO_EL1, 173 APDBKEYHI_EL1, 174 APGAKEYLO_EL1, 175 APGAKEYHI_EL1, 176 177 ELR_EL1, 178 SP_EL1, 179 SPSR_EL1, 180 181 CNTVOFF_EL2, 182 CNTV_CVAL_EL0, 183 CNTV_CTL_EL0, 184 CNTP_CVAL_EL0, 185 CNTP_CTL_EL0, 186 187 /* 32bit specific registers. Keep them at the end of the range */ 188 DACR32_EL2, /* Domain Access Control Register */ 189 IFSR32_EL2, /* Instruction Fault Status Register */ 190 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 191 DBGVCR32_EL2, /* Debug Vector Catch Register */ 192 193 NR_SYS_REGS /* Nothing after this line! */ 194 }; 195 196 /* 32bit mapping */ 197 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ 198 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ 199 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ 200 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ 201 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ 202 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ 203 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ 204 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ 205 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ 206 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ 207 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ 208 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ 209 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ 210 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ 211 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ 212 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ 213 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ 214 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ 215 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ 216 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ 217 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ 218 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ 219 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ 220 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ 221 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ 222 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ 223 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ 224 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ 225 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ 226 227 #define cp14_DBGDSCRext (MDSCR_EL1 * 2) 228 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) 229 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) 230 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) 231 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) 232 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) 233 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2) 234 235 #define NR_COPRO_REGS (NR_SYS_REGS * 2) 236 237 struct kvm_cpu_context { 238 struct user_pt_regs regs; /* sp = sp_el0 */ 239 240 u64 spsr_abt; 241 u64 spsr_und; 242 u64 spsr_irq; 243 u64 spsr_fiq; 244 245 struct user_fpsimd_state fp_regs; 246 247 union { 248 u64 sys_regs[NR_SYS_REGS]; 249 u32 copro[NR_COPRO_REGS]; 250 }; 251 252 struct kvm_vcpu *__hyp_running_vcpu; 253 }; 254 255 struct kvm_pmu_events { 256 u32 events_host; 257 u32 events_guest; 258 }; 259 260 struct kvm_host_data { 261 struct kvm_cpu_context host_ctxt; 262 struct kvm_pmu_events pmu_events; 263 }; 264 265 typedef struct kvm_host_data kvm_host_data_t; 266 267 struct vcpu_reset_state { 268 unsigned long pc; 269 unsigned long r0; 270 bool be; 271 bool reset; 272 }; 273 274 struct kvm_vcpu_arch { 275 struct kvm_cpu_context ctxt; 276 void *sve_state; 277 unsigned int sve_max_vl; 278 279 /* Stage 2 paging state used by the hardware on next switch */ 280 struct kvm_s2_mmu *hw_mmu; 281 282 /* HYP configuration */ 283 u64 hcr_el2; 284 u32 mdcr_el2; 285 286 /* Exception Information */ 287 struct kvm_vcpu_fault_info fault; 288 289 /* State of various workarounds, see kvm_asm.h for bit assignment */ 290 u64 workaround_flags; 291 292 /* Miscellaneous vcpu state flags */ 293 u64 flags; 294 295 /* 296 * We maintain more than a single set of debug registers to support 297 * debugging the guest from the host and to maintain separate host and 298 * guest state during world switches. vcpu_debug_state are the debug 299 * registers of the vcpu as the guest sees them. host_debug_state are 300 * the host registers which are saved and restored during 301 * world switches. external_debug_state contains the debug 302 * values we want to debug the guest. This is set via the 303 * KVM_SET_GUEST_DEBUG ioctl. 304 * 305 * debug_ptr points to the set of debug registers that should be loaded 306 * onto the hardware when running the guest. 307 */ 308 struct kvm_guest_debug_arch *debug_ptr; 309 struct kvm_guest_debug_arch vcpu_debug_state; 310 struct kvm_guest_debug_arch external_debug_state; 311 312 struct thread_info *host_thread_info; /* hyp VA */ 313 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ 314 315 struct { 316 /* {Break,watch}point registers */ 317 struct kvm_guest_debug_arch regs; 318 /* Statistical profiling extension */ 319 u64 pmscr_el1; 320 } host_debug_state; 321 322 /* VGIC state */ 323 struct vgic_cpu vgic_cpu; 324 struct arch_timer_cpu timer_cpu; 325 struct kvm_pmu pmu; 326 327 /* 328 * Anything that is not used directly from assembly code goes 329 * here. 330 */ 331 332 /* 333 * Guest registers we preserve during guest debugging. 334 * 335 * These shadow registers are updated by the kvm_handle_sys_reg 336 * trap handler if the guest accesses or updates them while we 337 * are using guest debug. 338 */ 339 struct { 340 u32 mdscr_el1; 341 } guest_debug_preserved; 342 343 /* vcpu power-off state */ 344 bool power_off; 345 346 /* Don't run the guest (internal implementation need) */ 347 bool pause; 348 349 /* Cache some mmu pages needed inside spinlock regions */ 350 struct kvm_mmu_memory_cache mmu_page_cache; 351 352 /* Target CPU and feature flags */ 353 int target; 354 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); 355 356 /* Detect first run of a vcpu */ 357 bool has_run_once; 358 359 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 360 u64 vsesr_el2; 361 362 /* Additional reset state */ 363 struct vcpu_reset_state reset_state; 364 365 /* True when deferrable sysregs are loaded on the physical CPU, 366 * see kvm_vcpu_load_sysregs_vhe and kvm_vcpu_put_sysregs_vhe. */ 367 bool sysregs_loaded_on_cpu; 368 369 /* Guest PV state */ 370 struct { 371 u64 steal; 372 u64 last_steal; 373 gpa_t base; 374 } steal; 375 }; 376 377 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 378 #define vcpu_sve_pffr(vcpu) ((void *)((char *)((vcpu)->arch.sve_state) + \ 379 sve_ffr_offset((vcpu)->arch.sve_max_vl))) 380 381 #define vcpu_sve_state_size(vcpu) ({ \ 382 size_t __size_ret; \ 383 unsigned int __vcpu_vq; \ 384 \ 385 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ 386 __size_ret = 0; \ 387 } else { \ 388 __vcpu_vq = sve_vq_from_vl((vcpu)->arch.sve_max_vl); \ 389 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ 390 } \ 391 \ 392 __size_ret; \ 393 }) 394 395 /* vcpu_arch flags field values: */ 396 #define KVM_ARM64_DEBUG_DIRTY (1 << 0) 397 #define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */ 398 #define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */ 399 #define KVM_ARM64_HOST_SVE_IN_USE (1 << 3) /* backup for host TIF_SVE */ 400 #define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */ 401 #define KVM_ARM64_GUEST_HAS_SVE (1 << 5) /* SVE exposed to guest */ 402 #define KVM_ARM64_VCPU_SVE_FINALIZED (1 << 6) /* SVE config completed */ 403 #define KVM_ARM64_GUEST_HAS_PTRAUTH (1 << 7) /* PTRAUTH exposed to guest */ 404 405 #define vcpu_has_sve(vcpu) (system_supports_sve() && \ 406 ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_SVE)) 407 408 #ifdef CONFIG_ARM64_PTR_AUTH 409 #define vcpu_has_ptrauth(vcpu) \ 410 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 411 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 412 (vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_PTRAUTH) 413 #else 414 #define vcpu_has_ptrauth(vcpu) false 415 #endif 416 417 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 418 419 /* 420 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 421 * memory backed version of a register, and not the one most recently 422 * accessed by a running VCPU. For example, for userspace access or 423 * for system registers that are never context switched, but only 424 * emulated. 425 */ 426 #define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)]) 427 428 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 429 430 #define __vcpu_sys_reg(v,r) (ctxt_sys_reg(&(v)->arch.ctxt, (r))) 431 432 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 433 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 434 435 /* 436 * CP14 and CP15 live in the same array, as they are backed by the 437 * same system registers. 438 */ 439 #define CPx_BIAS IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) 440 441 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r) ^ CPx_BIAS]) 442 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r) ^ CPx_BIAS]) 443 444 struct kvm_vm_stat { 445 ulong remote_tlb_flush; 446 }; 447 448 struct kvm_vcpu_stat { 449 u64 halt_successful_poll; 450 u64 halt_attempted_poll; 451 u64 halt_poll_success_ns; 452 u64 halt_poll_fail_ns; 453 u64 halt_poll_invalid; 454 u64 halt_wakeup; 455 u64 hvc_exit_stat; 456 u64 wfe_exit_stat; 457 u64 wfi_exit_stat; 458 u64 mmio_exit_user; 459 u64 mmio_exit_kernel; 460 u64 exits; 461 }; 462 463 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 464 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 465 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 466 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 467 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 468 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 469 struct kvm_vcpu_events *events); 470 471 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 472 struct kvm_vcpu_events *events); 473 474 #define KVM_ARCH_WANT_MMU_NOTIFIER 475 int kvm_unmap_hva_range(struct kvm *kvm, 476 unsigned long start, unsigned long end); 477 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 478 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 479 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 480 481 void kvm_arm_halt_guest(struct kvm *kvm); 482 void kvm_arm_resume_guest(struct kvm *kvm); 483 484 u64 __kvm_call_hyp(void *hypfn, ...); 485 486 #define kvm_call_hyp_nvhe(f, ...) \ 487 do { \ 488 DECLARE_KVM_NVHE_SYM(f); \ 489 __kvm_call_hyp(kvm_ksym_ref_nvhe(f), ##__VA_ARGS__); \ 490 } while(0) 491 492 #define kvm_call_hyp_nvhe_ret(f, ...) \ 493 ({ \ 494 DECLARE_KVM_NVHE_SYM(f); \ 495 __kvm_call_hyp(kvm_ksym_ref_nvhe(f), ##__VA_ARGS__); \ 496 }) 497 498 /* 499 * The couple of isb() below are there to guarantee the same behaviour 500 * on VHE as on !VHE, where the eret to EL1 acts as a context 501 * synchronization event. 502 */ 503 #define kvm_call_hyp(f, ...) \ 504 do { \ 505 if (has_vhe()) { \ 506 f(__VA_ARGS__); \ 507 isb(); \ 508 } else { \ 509 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 510 } \ 511 } while(0) 512 513 #define kvm_call_hyp_ret(f, ...) \ 514 ({ \ 515 typeof(f(__VA_ARGS__)) ret; \ 516 \ 517 if (has_vhe()) { \ 518 ret = f(__VA_ARGS__); \ 519 isb(); \ 520 } else { \ 521 ret = kvm_call_hyp_nvhe_ret(f, ##__VA_ARGS__); \ 522 } \ 523 \ 524 ret; \ 525 }) 526 527 void force_vm_exit(const cpumask_t *mask); 528 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); 529 530 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 531 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 532 533 /* MMIO helpers */ 534 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 535 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 536 537 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 538 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 539 540 int kvm_perf_init(void); 541 int kvm_perf_teardown(void); 542 543 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 544 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 545 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 546 547 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 548 struct kvm_device_attr *attr); 549 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 550 struct kvm_device_attr *attr); 551 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 552 struct kvm_device_attr *attr); 553 554 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 555 { 556 vcpu_arch->steal.base = GPA_INVALID; 557 } 558 559 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 560 { 561 return (vcpu_arch->steal.base != GPA_INVALID); 562 } 563 564 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); 565 566 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 567 568 DECLARE_PER_CPU(kvm_host_data_t, kvm_host_data); 569 570 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 571 { 572 /* The host's MPIDR is immutable, so let's set it up at boot time */ 573 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 574 } 575 576 static inline bool kvm_arch_requires_vhe(void) 577 { 578 /* 579 * The Arm architecture specifies that implementation of SVE 580 * requires VHE also to be implemented. The KVM code for arm64 581 * relies on this when SVE is present: 582 */ 583 if (system_supports_sve()) 584 return true; 585 586 return false; 587 } 588 589 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu); 590 591 static inline void kvm_arch_hardware_unsetup(void) {} 592 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 593 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 594 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 595 596 void kvm_arm_init_debug(void); 597 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 598 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 599 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 600 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 601 struct kvm_device_attr *attr); 602 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 603 struct kvm_device_attr *attr); 604 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 605 struct kvm_device_attr *attr); 606 607 /* Guest/host FPSIMD coordination helpers */ 608 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); 609 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 610 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 611 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 612 613 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 614 { 615 return (!has_vhe() && attr->exclude_host); 616 } 617 618 #ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */ 619 static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) 620 { 621 return kvm_arch_vcpu_run_map_fp(vcpu); 622 } 623 624 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); 625 void kvm_clr_pmu_events(u32 clr); 626 627 void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu); 628 void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); 629 #else 630 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} 631 static inline void kvm_clr_pmu_events(u32 clr) {} 632 #endif 633 634 #define KVM_BP_HARDEN_UNKNOWN -1 635 #define KVM_BP_HARDEN_WA_NEEDED 0 636 #define KVM_BP_HARDEN_NOT_REQUIRED 1 637 638 static inline int kvm_arm_harden_branch_predictor(void) 639 { 640 switch (get_spectre_v2_workaround_state()) { 641 case ARM64_BP_HARDEN_WA_NEEDED: 642 return KVM_BP_HARDEN_WA_NEEDED; 643 case ARM64_BP_HARDEN_NOT_REQUIRED: 644 return KVM_BP_HARDEN_NOT_REQUIRED; 645 case ARM64_BP_HARDEN_UNKNOWN: 646 default: 647 return KVM_BP_HARDEN_UNKNOWN; 648 } 649 } 650 651 #define KVM_SSBD_UNKNOWN -1 652 #define KVM_SSBD_FORCE_DISABLE 0 653 #define KVM_SSBD_KERNEL 1 654 #define KVM_SSBD_FORCE_ENABLE 2 655 #define KVM_SSBD_MITIGATED 3 656 657 static inline int kvm_arm_have_ssbd(void) 658 { 659 switch (arm64_get_ssbd_state()) { 660 case ARM64_SSBD_FORCE_DISABLE: 661 return KVM_SSBD_FORCE_DISABLE; 662 case ARM64_SSBD_KERNEL: 663 return KVM_SSBD_KERNEL; 664 case ARM64_SSBD_FORCE_ENABLE: 665 return KVM_SSBD_FORCE_ENABLE; 666 case ARM64_SSBD_MITIGATED: 667 return KVM_SSBD_MITIGATED; 668 case ARM64_SSBD_UNKNOWN: 669 default: 670 return KVM_SSBD_UNKNOWN; 671 } 672 } 673 674 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu); 675 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu); 676 677 int kvm_set_ipa_limit(void); 678 679 #define __KVM_HAVE_ARCH_VM_ALLOC 680 struct kvm *kvm_arch_alloc_vm(void); 681 void kvm_arch_free_vm(struct kvm *kvm); 682 683 int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type); 684 685 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 686 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 687 688 #define kvm_arm_vcpu_sve_finalized(vcpu) \ 689 ((vcpu)->arch.flags & KVM_ARM64_VCPU_SVE_FINALIZED) 690 691 #endif /* __ARM64_KVM_HOST_H__ */ 692