1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/percpu.h> 20 #include <linux/psci.h> 21 #include <asm/arch_gicv3.h> 22 #include <asm/barrier.h> 23 #include <asm/cpufeature.h> 24 #include <asm/cputype.h> 25 #include <asm/daifflags.h> 26 #include <asm/fpsimd.h> 27 #include <asm/kvm.h> 28 #include <asm/kvm_asm.h> 29 30 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 31 32 #define KVM_HALT_POLL_NS_DEFAULT 500000 33 34 #include <kvm/arm_vgic.h> 35 #include <kvm/arm_arch_timer.h> 36 #include <kvm/arm_pmu.h> 37 38 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 39 40 #define KVM_VCPU_MAX_FEATURES 7 41 42 #define KVM_REQ_SLEEP \ 43 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 44 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 45 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 46 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 47 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 48 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 49 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 50 51 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 52 KVM_DIRTY_LOG_INITIALLY_SET) 53 54 #define KVM_HAVE_MMU_RWLOCK 55 56 /* 57 * Mode of operation configurable with kvm-arm.mode early param. 58 * See Documentation/admin-guide/kernel-parameters.txt for more information. 59 */ 60 enum kvm_mode { 61 KVM_MODE_DEFAULT, 62 KVM_MODE_PROTECTED, 63 KVM_MODE_NONE, 64 }; 65 enum kvm_mode kvm_get_mode(void); 66 67 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 68 69 extern unsigned int kvm_sve_max_vl; 70 int kvm_arm_init_sve(void); 71 72 u32 __attribute_const__ kvm_target_cpu(void); 73 int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 74 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 75 76 struct kvm_vmid { 77 atomic64_t id; 78 }; 79 80 struct kvm_s2_mmu { 81 struct kvm_vmid vmid; 82 83 /* 84 * stage2 entry level table 85 * 86 * Two kvm_s2_mmu structures in the same VM can point to the same 87 * pgd here. This happens when running a guest using a 88 * translation regime that isn't affected by its own stage-2 89 * translation, such as a non-VHE hypervisor running at vEL2, or 90 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 91 * canonical stage-2 page tables. 92 */ 93 phys_addr_t pgd_phys; 94 struct kvm_pgtable *pgt; 95 96 /* The last vcpu id that ran on each physical CPU */ 97 int __percpu *last_vcpu_ran; 98 99 struct kvm_arch *arch; 100 }; 101 102 struct kvm_arch_memory_slot { 103 }; 104 105 /** 106 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 107 * 108 * @std_bmap: Bitmap of standard secure service calls 109 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 110 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 111 */ 112 struct kvm_smccc_features { 113 unsigned long std_bmap; 114 unsigned long std_hyp_bmap; 115 unsigned long vendor_hyp_bmap; 116 }; 117 118 struct kvm_arch { 119 struct kvm_s2_mmu mmu; 120 121 /* VTCR_EL2 value for this VM */ 122 u64 vtcr; 123 124 /* Interrupt controller */ 125 struct vgic_dist vgic; 126 127 /* Mandated version of PSCI */ 128 u32 psci_version; 129 130 /* 131 * If we encounter a data abort without valid instruction syndrome 132 * information, report this to user space. User space can (and 133 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 134 * supported. 135 */ 136 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 137 /* Memory Tagging Extension enabled for the guest */ 138 #define KVM_ARCH_FLAG_MTE_ENABLED 1 139 /* At least one vCPU has ran in the VM */ 140 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 141 /* 142 * The following two bits are used to indicate the guest's EL1 143 * register width configuration. A value of KVM_ARCH_FLAG_EL1_32BIT 144 * bit is valid only when KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED is set. 145 * Otherwise, the guest's EL1 register width has not yet been 146 * determined yet. 147 */ 148 #define KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED 3 149 #define KVM_ARCH_FLAG_EL1_32BIT 4 150 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 151 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 5 152 153 unsigned long flags; 154 155 /* 156 * VM-wide PMU filter, implemented as a bitmap and big enough for 157 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 158 */ 159 unsigned long *pmu_filter; 160 struct arm_pmu *arm_pmu; 161 162 cpumask_var_t supported_cpus; 163 164 u8 pfr0_csv2; 165 u8 pfr0_csv3; 166 167 /* Hypercall features firmware registers' descriptor */ 168 struct kvm_smccc_features smccc_feat; 169 }; 170 171 struct kvm_vcpu_fault_info { 172 u64 esr_el2; /* Hyp Syndrom Register */ 173 u64 far_el2; /* Hyp Fault Address Register */ 174 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 175 u64 disr_el1; /* Deferred [SError] Status Register */ 176 }; 177 178 enum vcpu_sysreg { 179 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 180 MPIDR_EL1, /* MultiProcessor Affinity Register */ 181 CSSELR_EL1, /* Cache Size Selection Register */ 182 SCTLR_EL1, /* System Control Register */ 183 ACTLR_EL1, /* Auxiliary Control Register */ 184 CPACR_EL1, /* Coprocessor Access Control */ 185 ZCR_EL1, /* SVE Control */ 186 TTBR0_EL1, /* Translation Table Base Register 0 */ 187 TTBR1_EL1, /* Translation Table Base Register 1 */ 188 TCR_EL1, /* Translation Control Register */ 189 ESR_EL1, /* Exception Syndrome Register */ 190 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ 191 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ 192 FAR_EL1, /* Fault Address Register */ 193 MAIR_EL1, /* Memory Attribute Indirection Register */ 194 VBAR_EL1, /* Vector Base Address Register */ 195 CONTEXTIDR_EL1, /* Context ID Register */ 196 TPIDR_EL0, /* Thread ID, User R/W */ 197 TPIDRRO_EL0, /* Thread ID, User R/O */ 198 TPIDR_EL1, /* Thread ID, Privileged */ 199 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ 200 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 201 PAR_EL1, /* Physical Address Register */ 202 MDSCR_EL1, /* Monitor Debug System Control Register */ 203 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 204 OSLSR_EL1, /* OS Lock Status Register */ 205 DISR_EL1, /* Deferred Interrupt Status Register */ 206 207 /* Performance Monitors Registers */ 208 PMCR_EL0, /* Control Register */ 209 PMSELR_EL0, /* Event Counter Selection Register */ 210 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 211 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 212 PMCCNTR_EL0, /* Cycle Counter Register */ 213 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 214 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 215 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 216 PMCNTENSET_EL0, /* Count Enable Set Register */ 217 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 218 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 219 PMUSERENR_EL0, /* User Enable Register */ 220 221 /* Pointer Authentication Registers in a strict increasing order. */ 222 APIAKEYLO_EL1, 223 APIAKEYHI_EL1, 224 APIBKEYLO_EL1, 225 APIBKEYHI_EL1, 226 APDAKEYLO_EL1, 227 APDAKEYHI_EL1, 228 APDBKEYLO_EL1, 229 APDBKEYHI_EL1, 230 APGAKEYLO_EL1, 231 APGAKEYHI_EL1, 232 233 ELR_EL1, 234 SP_EL1, 235 SPSR_EL1, 236 237 CNTVOFF_EL2, 238 CNTV_CVAL_EL0, 239 CNTV_CTL_EL0, 240 CNTP_CVAL_EL0, 241 CNTP_CTL_EL0, 242 243 /* Memory Tagging Extension registers */ 244 RGSR_EL1, /* Random Allocation Tag Seed Register */ 245 GCR_EL1, /* Tag Control Register */ 246 TFSR_EL1, /* Tag Fault Status Register (EL1) */ 247 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 248 249 /* 32bit specific registers. Keep them at the end of the range */ 250 DACR32_EL2, /* Domain Access Control Register */ 251 IFSR32_EL2, /* Instruction Fault Status Register */ 252 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 253 DBGVCR32_EL2, /* Debug Vector Catch Register */ 254 255 NR_SYS_REGS /* Nothing after this line! */ 256 }; 257 258 struct kvm_cpu_context { 259 struct user_pt_regs regs; /* sp = sp_el0 */ 260 261 u64 spsr_abt; 262 u64 spsr_und; 263 u64 spsr_irq; 264 u64 spsr_fiq; 265 266 struct user_fpsimd_state fp_regs; 267 268 u64 sys_regs[NR_SYS_REGS]; 269 270 struct kvm_vcpu *__hyp_running_vcpu; 271 }; 272 273 struct kvm_host_data { 274 struct kvm_cpu_context host_ctxt; 275 }; 276 277 struct kvm_host_psci_config { 278 /* PSCI version used by host. */ 279 u32 version; 280 281 /* Function IDs used by host if version is v0.1. */ 282 struct psci_0_1_function_ids function_ids_0_1; 283 284 bool psci_0_1_cpu_suspend_implemented; 285 bool psci_0_1_cpu_on_implemented; 286 bool psci_0_1_cpu_off_implemented; 287 bool psci_0_1_migrate_implemented; 288 }; 289 290 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 291 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 292 293 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 294 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 295 296 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 297 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 298 299 struct vcpu_reset_state { 300 unsigned long pc; 301 unsigned long r0; 302 bool be; 303 bool reset; 304 }; 305 306 struct kvm_vcpu_arch { 307 struct kvm_cpu_context ctxt; 308 309 /* Guest floating point state */ 310 void *sve_state; 311 unsigned int sve_max_vl; 312 u64 svcr; 313 314 /* Stage 2 paging state used by the hardware on next switch */ 315 struct kvm_s2_mmu *hw_mmu; 316 317 /* Values of trap registers for the guest. */ 318 u64 hcr_el2; 319 u64 mdcr_el2; 320 u64 cptr_el2; 321 322 /* Values of trap registers for the host before guest entry. */ 323 u64 mdcr_el2_host; 324 325 /* Exception Information */ 326 struct kvm_vcpu_fault_info fault; 327 328 /* Ownership of the FP regs */ 329 enum { 330 FP_STATE_FREE, 331 FP_STATE_HOST_OWNED, 332 FP_STATE_GUEST_OWNED, 333 } fp_state; 334 335 /* Configuration flags, set once and for all before the vcpu can run */ 336 u8 cflags; 337 338 /* Input flags to the hypervisor code, potentially cleared after use */ 339 u8 iflags; 340 341 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 342 u8 sflags; 343 344 /* 345 * Don't run the guest (internal implementation need). 346 * 347 * Contrary to the flags above, this is set/cleared outside of 348 * a vcpu context, and thus cannot be mixed with the flags 349 * themselves (or the flag accesses need to be made atomic). 350 */ 351 bool pause; 352 353 /* 354 * We maintain more than a single set of debug registers to support 355 * debugging the guest from the host and to maintain separate host and 356 * guest state during world switches. vcpu_debug_state are the debug 357 * registers of the vcpu as the guest sees them. host_debug_state are 358 * the host registers which are saved and restored during 359 * world switches. external_debug_state contains the debug 360 * values we want to debug the guest. This is set via the 361 * KVM_SET_GUEST_DEBUG ioctl. 362 * 363 * debug_ptr points to the set of debug registers that should be loaded 364 * onto the hardware when running the guest. 365 */ 366 struct kvm_guest_debug_arch *debug_ptr; 367 struct kvm_guest_debug_arch vcpu_debug_state; 368 struct kvm_guest_debug_arch external_debug_state; 369 370 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ 371 struct task_struct *parent_task; 372 373 struct { 374 /* {Break,watch}point registers */ 375 struct kvm_guest_debug_arch regs; 376 /* Statistical profiling extension */ 377 u64 pmscr_el1; 378 /* Self-hosted trace */ 379 u64 trfcr_el1; 380 } host_debug_state; 381 382 /* VGIC state */ 383 struct vgic_cpu vgic_cpu; 384 struct arch_timer_cpu timer_cpu; 385 struct kvm_pmu pmu; 386 387 /* 388 * Guest registers we preserve during guest debugging. 389 * 390 * These shadow registers are updated by the kvm_handle_sys_reg 391 * trap handler if the guest accesses or updates them while we 392 * are using guest debug. 393 */ 394 struct { 395 u32 mdscr_el1; 396 bool pstate_ss; 397 } guest_debug_preserved; 398 399 /* vcpu power state */ 400 struct kvm_mp_state mp_state; 401 402 /* Cache some mmu pages needed inside spinlock regions */ 403 struct kvm_mmu_memory_cache mmu_page_cache; 404 405 /* Target CPU and feature flags */ 406 int target; 407 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); 408 409 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 410 u64 vsesr_el2; 411 412 /* Additional reset state */ 413 struct vcpu_reset_state reset_state; 414 415 /* Guest PV state */ 416 struct { 417 u64 last_steal; 418 gpa_t base; 419 } steal; 420 }; 421 422 /* 423 * Each 'flag' is composed of a comma-separated triplet: 424 * 425 * - the flag-set it belongs to in the vcpu->arch structure 426 * - the value for that flag 427 * - the mask for that flag 428 * 429 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 430 * unpack_vcpu_flag() extract the flag value from the triplet for 431 * direct use outside of the flag accessors. 432 */ 433 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 434 435 #define __unpack_flag(_set, _f, _m) _f 436 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 437 438 #define __build_check_flag(v, flagset, f, m) \ 439 do { \ 440 typeof(v->arch.flagset) *_fset; \ 441 \ 442 /* Check that the flags fit in the mask */ \ 443 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 444 /* Check that the flags fit in the type */ \ 445 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 446 } while (0) 447 448 #define __vcpu_get_flag(v, flagset, f, m) \ 449 ({ \ 450 __build_check_flag(v, flagset, f, m); \ 451 \ 452 v->arch.flagset & (m); \ 453 }) 454 455 #define __vcpu_set_flag(v, flagset, f, m) \ 456 do { \ 457 typeof(v->arch.flagset) *fset; \ 458 \ 459 __build_check_flag(v, flagset, f, m); \ 460 \ 461 fset = &v->arch.flagset; \ 462 if (HWEIGHT(m) > 1) \ 463 *fset &= ~(m); \ 464 *fset |= (f); \ 465 } while (0) 466 467 #define __vcpu_clear_flag(v, flagset, f, m) \ 468 do { \ 469 typeof(v->arch.flagset) *fset; \ 470 \ 471 __build_check_flag(v, flagset, f, m); \ 472 \ 473 fset = &v->arch.flagset; \ 474 *fset &= ~(m); \ 475 } while (0) 476 477 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 478 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 479 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 480 481 /* SVE exposed to guest */ 482 #define GUEST_HAS_SVE __vcpu_single_flag(cflags, BIT(0)) 483 /* SVE config completed */ 484 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 485 /* PTRAUTH exposed to guest */ 486 #define GUEST_HAS_PTRAUTH __vcpu_single_flag(cflags, BIT(2)) 487 488 /* Exception pending */ 489 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 490 /* 491 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 492 * be set together with an exception... 493 */ 494 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 495 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 496 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 497 498 /* Helpers to encode exceptions with minimum fuss */ 499 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 500 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 501 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 502 503 /* 504 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 505 * values: 506 * 507 * For AArch32 EL1: 508 */ 509 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 510 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 511 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 512 /* For AArch64: */ 513 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 514 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 515 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 516 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 517 /* For AArch64 with NV (one day): */ 518 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 519 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 520 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 521 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 522 /* Guest debug is live */ 523 #define DEBUG_DIRTY __vcpu_single_flag(iflags, BIT(4)) 524 /* Save SPE context if active */ 525 #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5)) 526 /* Save TRBE context if active */ 527 #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) 528 529 /* SVE enabled for host EL0 */ 530 #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) 531 /* SME enabled for EL0 */ 532 #define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1)) 533 /* Physical CPU not in supported_cpus */ 534 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2)) 535 /* WFIT instruction trapped */ 536 #define IN_WFIT __vcpu_single_flag(sflags, BIT(3)) 537 /* vcpu system registers loaded on physical CPU */ 538 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(4)) 539 /* Software step state is Active-pending */ 540 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5)) 541 542 543 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 544 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 545 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 546 547 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 548 549 #define vcpu_sve_state_size(vcpu) ({ \ 550 size_t __size_ret; \ 551 unsigned int __vcpu_vq; \ 552 \ 553 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ 554 __size_ret = 0; \ 555 } else { \ 556 __vcpu_vq = vcpu_sve_max_vq(vcpu); \ 557 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ 558 } \ 559 \ 560 __size_ret; \ 561 }) 562 563 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 564 KVM_GUESTDBG_USE_SW_BP | \ 565 KVM_GUESTDBG_USE_HW | \ 566 KVM_GUESTDBG_SINGLESTEP) 567 568 #define vcpu_has_sve(vcpu) (system_supports_sve() && \ 569 vcpu_get_flag(vcpu, GUEST_HAS_SVE)) 570 571 #ifdef CONFIG_ARM64_PTR_AUTH 572 #define vcpu_has_ptrauth(vcpu) \ 573 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 574 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 575 vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH)) 576 #else 577 #define vcpu_has_ptrauth(vcpu) false 578 #endif 579 580 #define vcpu_on_unsupported_cpu(vcpu) \ 581 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 582 583 #define vcpu_set_on_unsupported_cpu(vcpu) \ 584 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 585 586 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 587 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 588 589 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 590 591 /* 592 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 593 * memory backed version of a register, and not the one most recently 594 * accessed by a running VCPU. For example, for userspace access or 595 * for system registers that are never context switched, but only 596 * emulated. 597 */ 598 #define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)]) 599 600 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 601 602 #define __vcpu_sys_reg(v,r) (ctxt_sys_reg(&(v)->arch.ctxt, (r))) 603 604 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 605 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 606 607 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 608 { 609 /* 610 * *** VHE ONLY *** 611 * 612 * System registers listed in the switch are not saved on every 613 * exit from the guest but are only saved on vcpu_put. 614 * 615 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 616 * should never be listed below, because the guest cannot modify its 617 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 618 * thread when emulating cross-VCPU communication. 619 */ 620 if (!has_vhe()) 621 return false; 622 623 switch (reg) { 624 case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break; 625 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; 626 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; 627 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; 628 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; 629 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; 630 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; 631 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; 632 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; 633 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; 634 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; 635 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; 636 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 637 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; 638 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 639 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; 640 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; 641 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 642 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; 643 case PAR_EL1: *val = read_sysreg_par(); break; 644 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; 645 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; 646 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 647 default: return false; 648 } 649 650 return true; 651 } 652 653 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 654 { 655 /* 656 * *** VHE ONLY *** 657 * 658 * System registers listed in the switch are not restored on every 659 * entry to the guest but are only restored on vcpu_load. 660 * 661 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 662 * should never be listed below, because the MPIDR should only be set 663 * once, before running the VCPU, and never changed later. 664 */ 665 if (!has_vhe()) 666 return false; 667 668 switch (reg) { 669 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break; 670 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 671 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 672 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 673 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 674 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 675 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 676 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 677 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 678 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 679 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 680 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 681 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 682 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 683 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 684 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 685 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 686 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 687 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 688 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 689 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 690 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 691 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 692 default: return false; 693 } 694 695 return true; 696 } 697 698 struct kvm_vm_stat { 699 struct kvm_vm_stat_generic generic; 700 }; 701 702 struct kvm_vcpu_stat { 703 struct kvm_vcpu_stat_generic generic; 704 u64 hvc_exit_stat; 705 u64 wfe_exit_stat; 706 u64 wfi_exit_stat; 707 u64 mmio_exit_user; 708 u64 mmio_exit_kernel; 709 u64 signal_exits; 710 u64 exits; 711 }; 712 713 void kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 714 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 715 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 716 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 717 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 718 719 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 720 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 721 722 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 723 struct kvm_vcpu_events *events); 724 725 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 726 struct kvm_vcpu_events *events); 727 728 #define KVM_ARCH_WANT_MMU_NOTIFIER 729 730 void kvm_arm_halt_guest(struct kvm *kvm); 731 void kvm_arm_resume_guest(struct kvm *kvm); 732 733 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid) 734 735 #ifndef __KVM_NVHE_HYPERVISOR__ 736 #define kvm_call_hyp_nvhe(f, ...) \ 737 ({ \ 738 struct arm_smccc_res res; \ 739 \ 740 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 741 ##__VA_ARGS__, &res); \ 742 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 743 \ 744 res.a1; \ 745 }) 746 747 /* 748 * The couple of isb() below are there to guarantee the same behaviour 749 * on VHE as on !VHE, where the eret to EL1 acts as a context 750 * synchronization event. 751 */ 752 #define kvm_call_hyp(f, ...) \ 753 do { \ 754 if (has_vhe()) { \ 755 f(__VA_ARGS__); \ 756 isb(); \ 757 } else { \ 758 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 759 } \ 760 } while(0) 761 762 #define kvm_call_hyp_ret(f, ...) \ 763 ({ \ 764 typeof(f(__VA_ARGS__)) ret; \ 765 \ 766 if (has_vhe()) { \ 767 ret = f(__VA_ARGS__); \ 768 isb(); \ 769 } else { \ 770 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 771 } \ 772 \ 773 ret; \ 774 }) 775 #else /* __KVM_NVHE_HYPERVISOR__ */ 776 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 777 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 778 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 779 #endif /* __KVM_NVHE_HYPERVISOR__ */ 780 781 void force_vm_exit(const cpumask_t *mask); 782 783 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 784 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 785 786 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 787 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 788 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 789 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 790 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 791 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 792 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 793 794 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 795 796 int kvm_sys_reg_table_init(void); 797 798 /* MMIO helpers */ 799 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 800 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 801 802 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 803 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 804 805 /* 806 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 807 * arrived in guest context. For arm64, any event that arrives while a vCPU is 808 * loaded is considered to be "in guest". 809 */ 810 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 811 { 812 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 813 } 814 815 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 816 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 817 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 818 819 bool kvm_arm_pvtime_supported(void); 820 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 821 struct kvm_device_attr *attr); 822 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 823 struct kvm_device_attr *attr); 824 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 825 struct kvm_device_attr *attr); 826 827 extern unsigned int kvm_arm_vmid_bits; 828 int kvm_arm_vmid_alloc_init(void); 829 void kvm_arm_vmid_alloc_free(void); 830 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 831 void kvm_arm_vmid_clear_active(void); 832 833 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 834 { 835 vcpu_arch->steal.base = GPA_INVALID; 836 } 837 838 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 839 { 840 return (vcpu_arch->steal.base != GPA_INVALID); 841 } 842 843 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); 844 845 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 846 847 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 848 849 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 850 { 851 /* The host's MPIDR is immutable, so let's set it up at boot time */ 852 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 853 } 854 855 static inline bool kvm_system_needs_idmapped_vectors(void) 856 { 857 return cpus_have_const_cap(ARM64_SPECTRE_V3A); 858 } 859 860 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu); 861 862 static inline void kvm_arch_hardware_unsetup(void) {} 863 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 864 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 865 866 void kvm_arm_init_debug(void); 867 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu); 868 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 869 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 870 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 871 872 #define kvm_vcpu_os_lock_enabled(vcpu) \ 873 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & SYS_OSLSR_OSLK)) 874 875 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 876 struct kvm_device_attr *attr); 877 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 878 struct kvm_device_attr *attr); 879 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 880 struct kvm_device_attr *attr); 881 882 long kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 883 struct kvm_arm_copy_mte_tags *copy_tags); 884 885 /* Guest/host FPSIMD coordination helpers */ 886 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); 887 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 888 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 889 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 890 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 891 void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu); 892 893 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 894 { 895 return (!has_vhe() && attr->exclude_host); 896 } 897 898 /* Flags for host debug state */ 899 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu); 900 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu); 901 902 #ifdef CONFIG_KVM 903 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); 904 void kvm_clr_pmu_events(u32 clr); 905 #else 906 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} 907 static inline void kvm_clr_pmu_events(u32 clr) {} 908 #endif 909 910 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu); 911 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu); 912 913 int kvm_set_ipa_limit(void); 914 915 #define __KVM_HAVE_ARCH_VM_ALLOC 916 struct kvm *kvm_arch_alloc_vm(void); 917 918 int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type); 919 920 static inline bool kvm_vm_is_protected(struct kvm *kvm) 921 { 922 return false; 923 } 924 925 void kvm_init_protected_traps(struct kvm_vcpu *vcpu); 926 927 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 928 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 929 930 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 931 932 #define kvm_has_mte(kvm) \ 933 (system_supports_mte() && \ 934 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 935 936 #define kvm_supports_32bit_el0() \ 937 (system_supports_32bit_el0() && \ 938 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 939 940 int kvm_trng_call(struct kvm_vcpu *vcpu); 941 #ifdef CONFIG_KVM 942 extern phys_addr_t hyp_mem_base; 943 extern phys_addr_t hyp_mem_size; 944 void __init kvm_hyp_reserve(void); 945 #else 946 static inline void kvm_hyp_reserve(void) { } 947 #endif 948 949 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 950 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 951 952 #endif /* __ARM64_KVM_HOST_H__ */ 953