1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/percpu.h> 20 #include <linux/psci.h> 21 #include <asm/arch_gicv3.h> 22 #include <asm/barrier.h> 23 #include <asm/cpufeature.h> 24 #include <asm/cputype.h> 25 #include <asm/daifflags.h> 26 #include <asm/fpsimd.h> 27 #include <asm/kvm.h> 28 #include <asm/kvm_asm.h> 29 30 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 31 32 #define KVM_HALT_POLL_NS_DEFAULT 500000 33 34 #include <kvm/arm_vgic.h> 35 #include <kvm/arm_arch_timer.h> 36 #include <kvm/arm_pmu.h> 37 38 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 39 40 #define KVM_VCPU_MAX_FEATURES 7 41 42 #define KVM_REQ_SLEEP \ 43 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 44 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 45 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 46 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 47 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 48 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 49 50 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 51 KVM_DIRTY_LOG_INITIALLY_SET) 52 53 /* 54 * Mode of operation configurable with kvm-arm.mode early param. 55 * See Documentation/admin-guide/kernel-parameters.txt for more information. 56 */ 57 enum kvm_mode { 58 KVM_MODE_DEFAULT, 59 KVM_MODE_PROTECTED, 60 KVM_MODE_NONE, 61 }; 62 enum kvm_mode kvm_get_mode(void); 63 64 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 65 66 extern unsigned int kvm_sve_max_vl; 67 int kvm_arm_init_sve(void); 68 69 u32 __attribute_const__ kvm_target_cpu(void); 70 int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 71 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 72 73 struct kvm_vmid { 74 /* The VMID generation used for the virt. memory system */ 75 u64 vmid_gen; 76 u32 vmid; 77 }; 78 79 struct kvm_s2_mmu { 80 struct kvm_vmid vmid; 81 82 /* 83 * stage2 entry level table 84 * 85 * Two kvm_s2_mmu structures in the same VM can point to the same 86 * pgd here. This happens when running a guest using a 87 * translation regime that isn't affected by its own stage-2 88 * translation, such as a non-VHE hypervisor running at vEL2, or 89 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 90 * canonical stage-2 page tables. 91 */ 92 phys_addr_t pgd_phys; 93 struct kvm_pgtable *pgt; 94 95 /* The last vcpu id that ran on each physical CPU */ 96 int __percpu *last_vcpu_ran; 97 98 struct kvm_arch *arch; 99 }; 100 101 struct kvm_arch_memory_slot { 102 }; 103 104 struct kvm_arch { 105 struct kvm_s2_mmu mmu; 106 107 /* VTCR_EL2 value for this VM */ 108 u64 vtcr; 109 110 /* The maximum number of vCPUs depends on the used GIC model */ 111 int max_vcpus; 112 113 /* Interrupt controller */ 114 struct vgic_dist vgic; 115 116 /* Mandated version of PSCI */ 117 u32 psci_version; 118 119 /* 120 * If we encounter a data abort without valid instruction syndrome 121 * information, report this to user space. User space can (and 122 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 123 * supported. 124 */ 125 bool return_nisv_io_abort_to_user; 126 127 /* 128 * VM-wide PMU filter, implemented as a bitmap and big enough for 129 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 130 */ 131 unsigned long *pmu_filter; 132 struct arm_pmu *arm_pmu; 133 134 u8 pfr0_csv2; 135 u8 pfr0_csv3; 136 137 /* Memory Tagging Extension enabled for the guest */ 138 bool mte_enabled; 139 bool ran_once; 140 }; 141 142 struct kvm_vcpu_fault_info { 143 u32 esr_el2; /* Hyp Syndrom Register */ 144 u64 far_el2; /* Hyp Fault Address Register */ 145 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 146 u64 disr_el1; /* Deferred [SError] Status Register */ 147 }; 148 149 enum vcpu_sysreg { 150 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 151 MPIDR_EL1, /* MultiProcessor Affinity Register */ 152 CSSELR_EL1, /* Cache Size Selection Register */ 153 SCTLR_EL1, /* System Control Register */ 154 ACTLR_EL1, /* Auxiliary Control Register */ 155 CPACR_EL1, /* Coprocessor Access Control */ 156 ZCR_EL1, /* SVE Control */ 157 TTBR0_EL1, /* Translation Table Base Register 0 */ 158 TTBR1_EL1, /* Translation Table Base Register 1 */ 159 TCR_EL1, /* Translation Control Register */ 160 ESR_EL1, /* Exception Syndrome Register */ 161 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ 162 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ 163 FAR_EL1, /* Fault Address Register */ 164 MAIR_EL1, /* Memory Attribute Indirection Register */ 165 VBAR_EL1, /* Vector Base Address Register */ 166 CONTEXTIDR_EL1, /* Context ID Register */ 167 TPIDR_EL0, /* Thread ID, User R/W */ 168 TPIDRRO_EL0, /* Thread ID, User R/O */ 169 TPIDR_EL1, /* Thread ID, Privileged */ 170 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ 171 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 172 PAR_EL1, /* Physical Address Register */ 173 MDSCR_EL1, /* Monitor Debug System Control Register */ 174 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 175 DISR_EL1, /* Deferred Interrupt Status Register */ 176 177 /* Performance Monitors Registers */ 178 PMCR_EL0, /* Control Register */ 179 PMSELR_EL0, /* Event Counter Selection Register */ 180 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 181 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 182 PMCCNTR_EL0, /* Cycle Counter Register */ 183 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 184 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 185 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 186 PMCNTENSET_EL0, /* Count Enable Set Register */ 187 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 188 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 189 PMUSERENR_EL0, /* User Enable Register */ 190 191 /* Pointer Authentication Registers in a strict increasing order. */ 192 APIAKEYLO_EL1, 193 APIAKEYHI_EL1, 194 APIBKEYLO_EL1, 195 APIBKEYHI_EL1, 196 APDAKEYLO_EL1, 197 APDAKEYHI_EL1, 198 APDBKEYLO_EL1, 199 APDBKEYHI_EL1, 200 APGAKEYLO_EL1, 201 APGAKEYHI_EL1, 202 203 ELR_EL1, 204 SP_EL1, 205 SPSR_EL1, 206 207 CNTVOFF_EL2, 208 CNTV_CVAL_EL0, 209 CNTV_CTL_EL0, 210 CNTP_CVAL_EL0, 211 CNTP_CTL_EL0, 212 213 /* Memory Tagging Extension registers */ 214 RGSR_EL1, /* Random Allocation Tag Seed Register */ 215 GCR_EL1, /* Tag Control Register */ 216 TFSR_EL1, /* Tag Fault Status Register (EL1) */ 217 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 218 219 /* 32bit specific registers. Keep them at the end of the range */ 220 DACR32_EL2, /* Domain Access Control Register */ 221 IFSR32_EL2, /* Instruction Fault Status Register */ 222 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 223 DBGVCR32_EL2, /* Debug Vector Catch Register */ 224 225 NR_SYS_REGS /* Nothing after this line! */ 226 }; 227 228 struct kvm_cpu_context { 229 struct user_pt_regs regs; /* sp = sp_el0 */ 230 231 u64 spsr_abt; 232 u64 spsr_und; 233 u64 spsr_irq; 234 u64 spsr_fiq; 235 236 struct user_fpsimd_state fp_regs; 237 238 u64 sys_regs[NR_SYS_REGS]; 239 240 struct kvm_vcpu *__hyp_running_vcpu; 241 }; 242 243 struct kvm_pmu_events { 244 u32 events_host; 245 u32 events_guest; 246 }; 247 248 struct kvm_host_data { 249 struct kvm_cpu_context host_ctxt; 250 struct kvm_pmu_events pmu_events; 251 }; 252 253 struct kvm_host_psci_config { 254 /* PSCI version used by host. */ 255 u32 version; 256 257 /* Function IDs used by host if version is v0.1. */ 258 struct psci_0_1_function_ids function_ids_0_1; 259 260 bool psci_0_1_cpu_suspend_implemented; 261 bool psci_0_1_cpu_on_implemented; 262 bool psci_0_1_cpu_off_implemented; 263 bool psci_0_1_migrate_implemented; 264 }; 265 266 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 267 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 268 269 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 270 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 271 272 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 273 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 274 275 struct vcpu_reset_state { 276 unsigned long pc; 277 unsigned long r0; 278 bool be; 279 bool reset; 280 }; 281 282 struct kvm_vcpu_arch { 283 struct kvm_cpu_context ctxt; 284 void *sve_state; 285 unsigned int sve_max_vl; 286 287 /* Stage 2 paging state used by the hardware on next switch */ 288 struct kvm_s2_mmu *hw_mmu; 289 290 /* Values of trap registers for the guest. */ 291 u64 hcr_el2; 292 u64 mdcr_el2; 293 u64 cptr_el2; 294 295 /* Values of trap registers for the host before guest entry. */ 296 u64 mdcr_el2_host; 297 298 /* Exception Information */ 299 struct kvm_vcpu_fault_info fault; 300 301 /* Miscellaneous vcpu state flags */ 302 u64 flags; 303 304 /* 305 * We maintain more than a single set of debug registers to support 306 * debugging the guest from the host and to maintain separate host and 307 * guest state during world switches. vcpu_debug_state are the debug 308 * registers of the vcpu as the guest sees them. host_debug_state are 309 * the host registers which are saved and restored during 310 * world switches. external_debug_state contains the debug 311 * values we want to debug the guest. This is set via the 312 * KVM_SET_GUEST_DEBUG ioctl. 313 * 314 * debug_ptr points to the set of debug registers that should be loaded 315 * onto the hardware when running the guest. 316 */ 317 struct kvm_guest_debug_arch *debug_ptr; 318 struct kvm_guest_debug_arch vcpu_debug_state; 319 struct kvm_guest_debug_arch external_debug_state; 320 321 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ 322 struct task_struct *parent_task; 323 324 struct { 325 /* {Break,watch}point registers */ 326 struct kvm_guest_debug_arch regs; 327 /* Statistical profiling extension */ 328 u64 pmscr_el1; 329 /* Self-hosted trace */ 330 u64 trfcr_el1; 331 } host_debug_state; 332 333 /* VGIC state */ 334 struct vgic_cpu vgic_cpu; 335 struct arch_timer_cpu timer_cpu; 336 struct kvm_pmu pmu; 337 338 /* 339 * Anything that is not used directly from assembly code goes 340 * here. 341 */ 342 343 /* 344 * Guest registers we preserve during guest debugging. 345 * 346 * These shadow registers are updated by the kvm_handle_sys_reg 347 * trap handler if the guest accesses or updates them while we 348 * are using guest debug. 349 */ 350 struct { 351 u32 mdscr_el1; 352 } guest_debug_preserved; 353 354 /* vcpu power-off state */ 355 bool power_off; 356 357 /* Don't run the guest (internal implementation need) */ 358 bool pause; 359 360 /* Cache some mmu pages needed inside spinlock regions */ 361 struct kvm_mmu_memory_cache mmu_page_cache; 362 363 /* Target CPU and feature flags */ 364 int target; 365 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); 366 367 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 368 u64 vsesr_el2; 369 370 /* Additional reset state */ 371 struct vcpu_reset_state reset_state; 372 373 /* True when deferrable sysregs are loaded on the physical CPU, 374 * see kvm_vcpu_load_sysregs_vhe and kvm_vcpu_put_sysregs_vhe. */ 375 bool sysregs_loaded_on_cpu; 376 377 /* Guest PV state */ 378 struct { 379 u64 last_steal; 380 gpa_t base; 381 } steal; 382 }; 383 384 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 385 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 386 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 387 388 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 389 390 #define vcpu_sve_state_size(vcpu) ({ \ 391 size_t __size_ret; \ 392 unsigned int __vcpu_vq; \ 393 \ 394 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ 395 __size_ret = 0; \ 396 } else { \ 397 __vcpu_vq = vcpu_sve_max_vq(vcpu); \ 398 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ 399 } \ 400 \ 401 __size_ret; \ 402 }) 403 404 /* vcpu_arch flags field values: */ 405 #define KVM_ARM64_DEBUG_DIRTY (1 << 0) 406 #define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */ 407 #define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */ 408 #define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */ 409 #define KVM_ARM64_GUEST_HAS_SVE (1 << 5) /* SVE exposed to guest */ 410 #define KVM_ARM64_VCPU_SVE_FINALIZED (1 << 6) /* SVE config completed */ 411 #define KVM_ARM64_GUEST_HAS_PTRAUTH (1 << 7) /* PTRAUTH exposed to guest */ 412 #define KVM_ARM64_PENDING_EXCEPTION (1 << 8) /* Exception pending */ 413 /* 414 * Overlaps with KVM_ARM64_EXCEPT_MASK on purpose so that it can't be 415 * set together with an exception... 416 */ 417 #define KVM_ARM64_INCREMENT_PC (1 << 9) /* Increment PC */ 418 #define KVM_ARM64_EXCEPT_MASK (7 << 9) /* Target EL/MODE */ 419 /* 420 * When KVM_ARM64_PENDING_EXCEPTION is set, KVM_ARM64_EXCEPT_MASK can 421 * take the following values: 422 * 423 * For AArch32 EL1: 424 */ 425 #define KVM_ARM64_EXCEPT_AA32_UND (0 << 9) 426 #define KVM_ARM64_EXCEPT_AA32_IABT (1 << 9) 427 #define KVM_ARM64_EXCEPT_AA32_DABT (2 << 9) 428 /* For AArch64: */ 429 #define KVM_ARM64_EXCEPT_AA64_ELx_SYNC (0 << 9) 430 #define KVM_ARM64_EXCEPT_AA64_ELx_IRQ (1 << 9) 431 #define KVM_ARM64_EXCEPT_AA64_ELx_FIQ (2 << 9) 432 #define KVM_ARM64_EXCEPT_AA64_ELx_SERR (3 << 9) 433 #define KVM_ARM64_EXCEPT_AA64_EL1 (0 << 11) 434 #define KVM_ARM64_EXCEPT_AA64_EL2 (1 << 11) 435 436 #define KVM_ARM64_DEBUG_STATE_SAVE_SPE (1 << 12) /* Save SPE context if active */ 437 #define KVM_ARM64_DEBUG_STATE_SAVE_TRBE (1 << 13) /* Save TRBE context if active */ 438 #define KVM_ARM64_FP_FOREIGN_FPSTATE (1 << 14) 439 440 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 441 KVM_GUESTDBG_USE_SW_BP | \ 442 KVM_GUESTDBG_USE_HW | \ 443 KVM_GUESTDBG_SINGLESTEP) 444 445 #define vcpu_has_sve(vcpu) (system_supports_sve() && \ 446 ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_SVE)) 447 448 #ifdef CONFIG_ARM64_PTR_AUTH 449 #define vcpu_has_ptrauth(vcpu) \ 450 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 451 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 452 (vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_PTRAUTH) 453 #else 454 #define vcpu_has_ptrauth(vcpu) false 455 #endif 456 457 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 458 459 /* 460 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 461 * memory backed version of a register, and not the one most recently 462 * accessed by a running VCPU. For example, for userspace access or 463 * for system registers that are never context switched, but only 464 * emulated. 465 */ 466 #define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)]) 467 468 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 469 470 #define __vcpu_sys_reg(v,r) (ctxt_sys_reg(&(v)->arch.ctxt, (r))) 471 472 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 473 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 474 475 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 476 { 477 /* 478 * *** VHE ONLY *** 479 * 480 * System registers listed in the switch are not saved on every 481 * exit from the guest but are only saved on vcpu_put. 482 * 483 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 484 * should never be listed below, because the guest cannot modify its 485 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 486 * thread when emulating cross-VCPU communication. 487 */ 488 if (!has_vhe()) 489 return false; 490 491 switch (reg) { 492 case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break; 493 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; 494 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; 495 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; 496 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; 497 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; 498 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; 499 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; 500 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; 501 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; 502 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; 503 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; 504 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 505 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; 506 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 507 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; 508 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; 509 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 510 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; 511 case PAR_EL1: *val = read_sysreg_par(); break; 512 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; 513 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; 514 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 515 default: return false; 516 } 517 518 return true; 519 } 520 521 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 522 { 523 /* 524 * *** VHE ONLY *** 525 * 526 * System registers listed in the switch are not restored on every 527 * entry to the guest but are only restored on vcpu_load. 528 * 529 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 530 * should never be listed below, because the MPIDR should only be set 531 * once, before running the VCPU, and never changed later. 532 */ 533 if (!has_vhe()) 534 return false; 535 536 switch (reg) { 537 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break; 538 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 539 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 540 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 541 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 542 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 543 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 544 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 545 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 546 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 547 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 548 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 549 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 550 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 551 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 552 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 553 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 554 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 555 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 556 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 557 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 558 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 559 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 560 default: return false; 561 } 562 563 return true; 564 } 565 566 struct kvm_vm_stat { 567 struct kvm_vm_stat_generic generic; 568 }; 569 570 struct kvm_vcpu_stat { 571 struct kvm_vcpu_stat_generic generic; 572 u64 hvc_exit_stat; 573 u64 wfe_exit_stat; 574 u64 wfi_exit_stat; 575 u64 mmio_exit_user; 576 u64 mmio_exit_kernel; 577 u64 signal_exits; 578 u64 exits; 579 }; 580 581 void kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 582 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 583 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 584 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 585 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 586 587 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 588 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 589 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *); 590 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *); 591 592 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 593 struct kvm_vcpu_events *events); 594 595 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 596 struct kvm_vcpu_events *events); 597 598 #define KVM_ARCH_WANT_MMU_NOTIFIER 599 600 void kvm_arm_halt_guest(struct kvm *kvm); 601 void kvm_arm_resume_guest(struct kvm *kvm); 602 603 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid) 604 605 #ifndef __KVM_NVHE_HYPERVISOR__ 606 #define kvm_call_hyp_nvhe(f, ...) \ 607 ({ \ 608 struct arm_smccc_res res; \ 609 \ 610 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 611 ##__VA_ARGS__, &res); \ 612 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 613 \ 614 res.a1; \ 615 }) 616 617 /* 618 * The couple of isb() below are there to guarantee the same behaviour 619 * on VHE as on !VHE, where the eret to EL1 acts as a context 620 * synchronization event. 621 */ 622 #define kvm_call_hyp(f, ...) \ 623 do { \ 624 if (has_vhe()) { \ 625 f(__VA_ARGS__); \ 626 isb(); \ 627 } else { \ 628 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 629 } \ 630 } while(0) 631 632 #define kvm_call_hyp_ret(f, ...) \ 633 ({ \ 634 typeof(f(__VA_ARGS__)) ret; \ 635 \ 636 if (has_vhe()) { \ 637 ret = f(__VA_ARGS__); \ 638 isb(); \ 639 } else { \ 640 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 641 } \ 642 \ 643 ret; \ 644 }) 645 #else /* __KVM_NVHE_HYPERVISOR__ */ 646 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 647 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 648 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 649 #endif /* __KVM_NVHE_HYPERVISOR__ */ 650 651 void force_vm_exit(const cpumask_t *mask); 652 653 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 654 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 655 656 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 657 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 658 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 659 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 660 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 661 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 662 663 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 664 665 void kvm_sys_reg_table_init(void); 666 667 /* MMIO helpers */ 668 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 669 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 670 671 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 672 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 673 674 /* 675 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 676 * arrived in guest context. For arm64, any event that arrives while a vCPU is 677 * loaded is considered to be "in guest". 678 */ 679 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 680 { 681 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 682 } 683 684 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 685 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 686 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 687 688 bool kvm_arm_pvtime_supported(void); 689 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 690 struct kvm_device_attr *attr); 691 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 692 struct kvm_device_attr *attr); 693 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 694 struct kvm_device_attr *attr); 695 696 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 697 { 698 vcpu_arch->steal.base = GPA_INVALID; 699 } 700 701 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 702 { 703 return (vcpu_arch->steal.base != GPA_INVALID); 704 } 705 706 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); 707 708 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 709 710 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 711 712 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 713 { 714 /* The host's MPIDR is immutable, so let's set it up at boot time */ 715 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 716 } 717 718 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu); 719 720 static inline void kvm_arch_hardware_unsetup(void) {} 721 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 722 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 723 724 void kvm_arm_init_debug(void); 725 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu); 726 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 727 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 728 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 729 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 730 struct kvm_device_attr *attr); 731 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 732 struct kvm_device_attr *attr); 733 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 734 struct kvm_device_attr *attr); 735 736 long kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 737 struct kvm_arm_copy_mte_tags *copy_tags); 738 739 /* Guest/host FPSIMD coordination helpers */ 740 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); 741 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 742 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 743 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 744 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 745 void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu); 746 747 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 748 { 749 return (!has_vhe() && attr->exclude_host); 750 } 751 752 /* Flags for host debug state */ 753 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu); 754 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu); 755 756 #ifdef CONFIG_KVM 757 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); 758 void kvm_clr_pmu_events(u32 clr); 759 760 void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu); 761 void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); 762 #else 763 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} 764 static inline void kvm_clr_pmu_events(u32 clr) {} 765 #endif 766 767 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu); 768 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu); 769 770 int kvm_set_ipa_limit(void); 771 772 #define __KVM_HAVE_ARCH_VM_ALLOC 773 struct kvm *kvm_arch_alloc_vm(void); 774 775 int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type); 776 777 static inline bool kvm_vm_is_protected(struct kvm *kvm) 778 { 779 return false; 780 } 781 782 void kvm_init_protected_traps(struct kvm_vcpu *vcpu); 783 784 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 785 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 786 787 #define kvm_arm_vcpu_sve_finalized(vcpu) \ 788 ((vcpu)->arch.flags & KVM_ARM64_VCPU_SVE_FINALIZED) 789 790 #define kvm_has_mte(kvm) (system_supports_mte() && (kvm)->arch.mte_enabled) 791 #define kvm_vcpu_has_pmu(vcpu) \ 792 (test_bit(KVM_ARM_VCPU_PMU_V3, (vcpu)->arch.features)) 793 794 int kvm_trng_call(struct kvm_vcpu *vcpu); 795 #ifdef CONFIG_KVM 796 extern phys_addr_t hyp_mem_base; 797 extern phys_addr_t hyp_mem_size; 798 void __init kvm_hyp_reserve(void); 799 #else 800 static inline void kvm_hyp_reserve(void) { } 801 #endif 802 803 #endif /* __ARM64_KVM_HOST_H__ */ 804