1 /* 2 * Copyright (C) 2012,2013 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * Derived from arch/arm/include/asm/kvm_host.h: 6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 7 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef __ARM64_KVM_HOST_H__ 23 #define __ARM64_KVM_HOST_H__ 24 25 #include <linux/types.h> 26 #include <linux/kvm_types.h> 27 #include <asm/kvm.h> 28 #include <asm/kvm_asm.h> 29 #include <asm/kvm_mmio.h> 30 31 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 32 33 #define KVM_USER_MEM_SLOTS 512 34 #define KVM_HALT_POLL_NS_DEFAULT 500000 35 36 #include <kvm/arm_vgic.h> 37 #include <kvm/arm_arch_timer.h> 38 #include <kvm/arm_pmu.h> 39 40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 41 42 #define KVM_VCPU_MAX_FEATURES 4 43 44 #define KVM_REQ_VCPU_EXIT (8 | KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 45 46 int __attribute_const__ kvm_target_cpu(void); 47 int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 48 int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext); 49 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start); 50 51 struct kvm_arch { 52 /* The VMID generation used for the virt. memory system */ 53 u64 vmid_gen; 54 u32 vmid; 55 56 /* 1-level 2nd stage table and lock */ 57 spinlock_t pgd_lock; 58 pgd_t *pgd; 59 60 /* VTTBR value associated with above pgd and vmid */ 61 u64 vttbr; 62 63 /* The last vcpu id that ran on each physical CPU */ 64 int __percpu *last_vcpu_ran; 65 66 /* The maximum number of vCPUs depends on the used GIC model */ 67 int max_vcpus; 68 69 /* Interrupt controller */ 70 struct vgic_dist vgic; 71 }; 72 73 #define KVM_NR_MEM_OBJS 40 74 75 /* 76 * We don't want allocation failures within the mmu code, so we preallocate 77 * enough memory for a single page fault in a cache. 78 */ 79 struct kvm_mmu_memory_cache { 80 int nobjs; 81 void *objects[KVM_NR_MEM_OBJS]; 82 }; 83 84 struct kvm_vcpu_fault_info { 85 u32 esr_el2; /* Hyp Syndrom Register */ 86 u64 far_el2; /* Hyp Fault Address Register */ 87 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 88 }; 89 90 /* 91 * 0 is reserved as an invalid value. 92 * Order should be kept in sync with the save/restore code. 93 */ 94 enum vcpu_sysreg { 95 __INVALID_SYSREG__, 96 MPIDR_EL1, /* MultiProcessor Affinity Register */ 97 CSSELR_EL1, /* Cache Size Selection Register */ 98 SCTLR_EL1, /* System Control Register */ 99 ACTLR_EL1, /* Auxiliary Control Register */ 100 CPACR_EL1, /* Coprocessor Access Control */ 101 TTBR0_EL1, /* Translation Table Base Register 0 */ 102 TTBR1_EL1, /* Translation Table Base Register 1 */ 103 TCR_EL1, /* Translation Control Register */ 104 ESR_EL1, /* Exception Syndrome Register */ 105 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ 106 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ 107 FAR_EL1, /* Fault Address Register */ 108 MAIR_EL1, /* Memory Attribute Indirection Register */ 109 VBAR_EL1, /* Vector Base Address Register */ 110 CONTEXTIDR_EL1, /* Context ID Register */ 111 TPIDR_EL0, /* Thread ID, User R/W */ 112 TPIDRRO_EL0, /* Thread ID, User R/O */ 113 TPIDR_EL1, /* Thread ID, Privileged */ 114 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ 115 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 116 PAR_EL1, /* Physical Address Register */ 117 MDSCR_EL1, /* Monitor Debug System Control Register */ 118 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 119 120 /* Performance Monitors Registers */ 121 PMCR_EL0, /* Control Register */ 122 PMSELR_EL0, /* Event Counter Selection Register */ 123 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 124 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 125 PMCCNTR_EL0, /* Cycle Counter Register */ 126 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 127 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 128 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 129 PMCNTENSET_EL0, /* Count Enable Set Register */ 130 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 131 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 132 PMSWINC_EL0, /* Software Increment Register */ 133 PMUSERENR_EL0, /* User Enable Register */ 134 135 /* 32bit specific registers. Keep them at the end of the range */ 136 DACR32_EL2, /* Domain Access Control Register */ 137 IFSR32_EL2, /* Instruction Fault Status Register */ 138 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 139 DBGVCR32_EL2, /* Debug Vector Catch Register */ 140 141 NR_SYS_REGS /* Nothing after this line! */ 142 }; 143 144 /* 32bit mapping */ 145 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ 146 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ 147 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ 148 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ 149 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ 150 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ 151 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ 152 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ 153 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ 154 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ 155 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ 156 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ 157 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ 158 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ 159 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ 160 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ 161 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ 162 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ 163 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ 164 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ 165 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ 166 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ 167 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ 168 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ 169 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ 170 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ 171 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ 172 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ 173 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ 174 175 #define cp14_DBGDSCRext (MDSCR_EL1 * 2) 176 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) 177 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) 178 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) 179 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) 180 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) 181 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2) 182 183 #define NR_COPRO_REGS (NR_SYS_REGS * 2) 184 185 struct kvm_cpu_context { 186 struct kvm_regs gp_regs; 187 union { 188 u64 sys_regs[NR_SYS_REGS]; 189 u32 copro[NR_COPRO_REGS]; 190 }; 191 }; 192 193 typedef struct kvm_cpu_context kvm_cpu_context_t; 194 195 struct kvm_vcpu_arch { 196 struct kvm_cpu_context ctxt; 197 198 /* HYP configuration */ 199 u64 hcr_el2; 200 u32 mdcr_el2; 201 202 /* Exception Information */ 203 struct kvm_vcpu_fault_info fault; 204 205 /* Guest debug state */ 206 u64 debug_flags; 207 208 /* 209 * We maintain more than a single set of debug registers to support 210 * debugging the guest from the host and to maintain separate host and 211 * guest state during world switches. vcpu_debug_state are the debug 212 * registers of the vcpu as the guest sees them. host_debug_state are 213 * the host registers which are saved and restored during 214 * world switches. external_debug_state contains the debug 215 * values we want to debug the guest. This is set via the 216 * KVM_SET_GUEST_DEBUG ioctl. 217 * 218 * debug_ptr points to the set of debug registers that should be loaded 219 * onto the hardware when running the guest. 220 */ 221 struct kvm_guest_debug_arch *debug_ptr; 222 struct kvm_guest_debug_arch vcpu_debug_state; 223 struct kvm_guest_debug_arch external_debug_state; 224 225 /* Pointer to host CPU context */ 226 kvm_cpu_context_t *host_cpu_context; 227 struct { 228 /* {Break,watch}point registers */ 229 struct kvm_guest_debug_arch regs; 230 /* Statistical profiling extension */ 231 u64 pmscr_el1; 232 } host_debug_state; 233 234 /* VGIC state */ 235 struct vgic_cpu vgic_cpu; 236 struct arch_timer_cpu timer_cpu; 237 struct kvm_pmu pmu; 238 239 /* 240 * Anything that is not used directly from assembly code goes 241 * here. 242 */ 243 244 /* 245 * Guest registers we preserve during guest debugging. 246 * 247 * These shadow registers are updated by the kvm_handle_sys_reg 248 * trap handler if the guest accesses or updates them while we 249 * are using guest debug. 250 */ 251 struct { 252 u32 mdscr_el1; 253 } guest_debug_preserved; 254 255 /* vcpu power-off state */ 256 bool power_off; 257 258 /* Don't run the guest (internal implementation need) */ 259 bool pause; 260 261 /* IO related fields */ 262 struct kvm_decode mmio_decode; 263 264 /* Interrupt related fields */ 265 u64 irq_lines; /* IRQ and FIQ levels */ 266 267 /* Cache some mmu pages needed inside spinlock regions */ 268 struct kvm_mmu_memory_cache mmu_page_cache; 269 270 /* Target CPU and feature flags */ 271 int target; 272 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); 273 274 /* Detect first run of a vcpu */ 275 bool has_run_once; 276 }; 277 278 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs) 279 #define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) 280 /* 281 * CP14 and CP15 live in the same array, as they are backed by the 282 * same system registers. 283 */ 284 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)]) 285 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)]) 286 287 #ifdef CONFIG_CPU_BIG_ENDIAN 288 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r)) 289 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r) + 1) 290 #else 291 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r) + 1) 292 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r)) 293 #endif 294 295 struct kvm_vm_stat { 296 ulong remote_tlb_flush; 297 }; 298 299 struct kvm_vcpu_stat { 300 u64 halt_successful_poll; 301 u64 halt_attempted_poll; 302 u64 halt_poll_invalid; 303 u64 halt_wakeup; 304 u64 hvc_exit_stat; 305 u64 wfe_exit_stat; 306 u64 wfi_exit_stat; 307 u64 mmio_exit_user; 308 u64 mmio_exit_kernel; 309 u64 exits; 310 }; 311 312 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 313 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 314 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 315 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 316 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 317 318 #define KVM_ARCH_WANT_MMU_NOTIFIER 319 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); 320 int kvm_unmap_hva_range(struct kvm *kvm, 321 unsigned long start, unsigned long end); 322 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 323 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 324 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 325 326 /* We do not have shadow page tables, hence the empty hooks */ 327 static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 328 unsigned long address) 329 { 330 } 331 332 struct kvm_vcpu *kvm_arm_get_running_vcpu(void); 333 struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void); 334 void kvm_arm_halt_guest(struct kvm *kvm); 335 void kvm_arm_resume_guest(struct kvm *kvm); 336 void kvm_arm_halt_vcpu(struct kvm_vcpu *vcpu); 337 void kvm_arm_resume_vcpu(struct kvm_vcpu *vcpu); 338 339 u64 __kvm_call_hyp(void *hypfn, ...); 340 #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__) 341 342 void force_vm_exit(const cpumask_t *mask); 343 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); 344 345 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, 346 int exception_index); 347 348 int kvm_perf_init(void); 349 int kvm_perf_teardown(void); 350 351 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 352 353 static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr, 354 unsigned long hyp_stack_ptr, 355 unsigned long vector_ptr) 356 { 357 /* 358 * Call initialization code, and switch to the full blown 359 * HYP code. 360 */ 361 __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr); 362 } 363 364 static inline void kvm_arch_hardware_unsetup(void) {} 365 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 366 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} 367 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 368 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 369 370 void kvm_arm_init_debug(void); 371 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 372 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 373 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 374 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 375 struct kvm_device_attr *attr); 376 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 377 struct kvm_device_attr *attr); 378 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 379 struct kvm_device_attr *attr); 380 381 static inline void __cpu_init_stage2(void) 382 { 383 u32 parange = kvm_call_hyp(__init_stage2_translation); 384 385 WARN_ONCE(parange < 40, 386 "PARange is %d bits, unsupported configuration!", parange); 387 } 388 389 #endif /* __ARM64_KVM_HOST_H__ */ 390