1 /* 2 * Copyright (C) 2012,2013 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * Derived from arch/arm/include/asm/kvm_host.h: 6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 7 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef __ARM64_KVM_HOST_H__ 23 #define __ARM64_KVM_HOST_H__ 24 25 #include <linux/types.h> 26 #include <linux/kvm_types.h> 27 #include <asm/kvm.h> 28 #include <asm/kvm_asm.h> 29 #include <asm/kvm_mmio.h> 30 31 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 32 33 #define KVM_USER_MEM_SLOTS 32 34 #define KVM_PRIVATE_MEM_SLOTS 4 35 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 36 #define KVM_HALT_POLL_NS_DEFAULT 500000 37 38 #include <kvm/arm_vgic.h> 39 #include <kvm/arm_arch_timer.h> 40 #include <kvm/arm_pmu.h> 41 42 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 43 44 #define KVM_VCPU_MAX_FEATURES 4 45 46 #define KVM_REQ_VCPU_EXIT 8 47 48 int __attribute_const__ kvm_target_cpu(void); 49 int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 50 int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext); 51 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start); 52 53 struct kvm_arch { 54 /* The VMID generation used for the virt. memory system */ 55 u64 vmid_gen; 56 u32 vmid; 57 58 /* 1-level 2nd stage table and lock */ 59 spinlock_t pgd_lock; 60 pgd_t *pgd; 61 62 /* VTTBR value associated with above pgd and vmid */ 63 u64 vttbr; 64 65 /* The maximum number of vCPUs depends on the used GIC model */ 66 int max_vcpus; 67 68 /* Interrupt controller */ 69 struct vgic_dist vgic; 70 71 /* Timer */ 72 struct arch_timer_kvm timer; 73 }; 74 75 #define KVM_NR_MEM_OBJS 40 76 77 /* 78 * We don't want allocation failures within the mmu code, so we preallocate 79 * enough memory for a single page fault in a cache. 80 */ 81 struct kvm_mmu_memory_cache { 82 int nobjs; 83 void *objects[KVM_NR_MEM_OBJS]; 84 }; 85 86 struct kvm_vcpu_fault_info { 87 u32 esr_el2; /* Hyp Syndrom Register */ 88 u64 far_el2; /* Hyp Fault Address Register */ 89 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 90 }; 91 92 /* 93 * 0 is reserved as an invalid value. 94 * Order should be kept in sync with the save/restore code. 95 */ 96 enum vcpu_sysreg { 97 __INVALID_SYSREG__, 98 MPIDR_EL1, /* MultiProcessor Affinity Register */ 99 CSSELR_EL1, /* Cache Size Selection Register */ 100 SCTLR_EL1, /* System Control Register */ 101 ACTLR_EL1, /* Auxiliary Control Register */ 102 CPACR_EL1, /* Coprocessor Access Control */ 103 TTBR0_EL1, /* Translation Table Base Register 0 */ 104 TTBR1_EL1, /* Translation Table Base Register 1 */ 105 TCR_EL1, /* Translation Control Register */ 106 ESR_EL1, /* Exception Syndrome Register */ 107 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ 108 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ 109 FAR_EL1, /* Fault Address Register */ 110 MAIR_EL1, /* Memory Attribute Indirection Register */ 111 VBAR_EL1, /* Vector Base Address Register */ 112 CONTEXTIDR_EL1, /* Context ID Register */ 113 TPIDR_EL0, /* Thread ID, User R/W */ 114 TPIDRRO_EL0, /* Thread ID, User R/O */ 115 TPIDR_EL1, /* Thread ID, Privileged */ 116 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ 117 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 118 PAR_EL1, /* Physical Address Register */ 119 MDSCR_EL1, /* Monitor Debug System Control Register */ 120 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 121 122 /* Performance Monitors Registers */ 123 PMCR_EL0, /* Control Register */ 124 PMSELR_EL0, /* Event Counter Selection Register */ 125 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 126 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 127 PMCCNTR_EL0, /* Cycle Counter Register */ 128 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 129 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 130 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 131 PMCNTENSET_EL0, /* Count Enable Set Register */ 132 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 133 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 134 PMSWINC_EL0, /* Software Increment Register */ 135 PMUSERENR_EL0, /* User Enable Register */ 136 137 /* 32bit specific registers. Keep them at the end of the range */ 138 DACR32_EL2, /* Domain Access Control Register */ 139 IFSR32_EL2, /* Instruction Fault Status Register */ 140 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 141 DBGVCR32_EL2, /* Debug Vector Catch Register */ 142 143 NR_SYS_REGS /* Nothing after this line! */ 144 }; 145 146 /* 32bit mapping */ 147 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ 148 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ 149 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ 150 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ 151 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ 152 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ 153 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ 154 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ 155 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ 156 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ 157 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ 158 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ 159 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ 160 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ 161 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ 162 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ 163 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ 164 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ 165 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ 166 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ 167 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ 168 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ 169 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ 170 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ 171 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ 172 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ 173 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ 174 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ 175 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ 176 177 #define cp14_DBGDSCRext (MDSCR_EL1 * 2) 178 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) 179 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) 180 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) 181 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) 182 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) 183 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2) 184 185 #define NR_COPRO_REGS (NR_SYS_REGS * 2) 186 187 struct kvm_cpu_context { 188 struct kvm_regs gp_regs; 189 union { 190 u64 sys_regs[NR_SYS_REGS]; 191 u32 copro[NR_COPRO_REGS]; 192 }; 193 }; 194 195 typedef struct kvm_cpu_context kvm_cpu_context_t; 196 197 struct kvm_vcpu_arch { 198 struct kvm_cpu_context ctxt; 199 200 /* HYP configuration */ 201 u64 hcr_el2; 202 u32 mdcr_el2; 203 204 /* Exception Information */ 205 struct kvm_vcpu_fault_info fault; 206 207 /* Guest debug state */ 208 u64 debug_flags; 209 210 /* 211 * We maintain more than a single set of debug registers to support 212 * debugging the guest from the host and to maintain separate host and 213 * guest state during world switches. vcpu_debug_state are the debug 214 * registers of the vcpu as the guest sees them. host_debug_state are 215 * the host registers which are saved and restored during 216 * world switches. external_debug_state contains the debug 217 * values we want to debug the guest. This is set via the 218 * KVM_SET_GUEST_DEBUG ioctl. 219 * 220 * debug_ptr points to the set of debug registers that should be loaded 221 * onto the hardware when running the guest. 222 */ 223 struct kvm_guest_debug_arch *debug_ptr; 224 struct kvm_guest_debug_arch vcpu_debug_state; 225 struct kvm_guest_debug_arch external_debug_state; 226 227 /* Pointer to host CPU context */ 228 kvm_cpu_context_t *host_cpu_context; 229 struct kvm_guest_debug_arch host_debug_state; 230 231 /* VGIC state */ 232 struct vgic_cpu vgic_cpu; 233 struct arch_timer_cpu timer_cpu; 234 struct kvm_pmu pmu; 235 236 /* 237 * Anything that is not used directly from assembly code goes 238 * here. 239 */ 240 241 /* 242 * Guest registers we preserve during guest debugging. 243 * 244 * These shadow registers are updated by the kvm_handle_sys_reg 245 * trap handler if the guest accesses or updates them while we 246 * are using guest debug. 247 */ 248 struct { 249 u32 mdscr_el1; 250 } guest_debug_preserved; 251 252 /* vcpu power-off state */ 253 bool power_off; 254 255 /* Don't run the guest (internal implementation need) */ 256 bool pause; 257 258 /* IO related fields */ 259 struct kvm_decode mmio_decode; 260 261 /* Interrupt related fields */ 262 u64 irq_lines; /* IRQ and FIQ levels */ 263 264 /* Cache some mmu pages needed inside spinlock regions */ 265 struct kvm_mmu_memory_cache mmu_page_cache; 266 267 /* Target CPU and feature flags */ 268 int target; 269 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); 270 271 /* Detect first run of a vcpu */ 272 bool has_run_once; 273 }; 274 275 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs) 276 #define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) 277 /* 278 * CP14 and CP15 live in the same array, as they are backed by the 279 * same system registers. 280 */ 281 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)]) 282 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)]) 283 284 #ifdef CONFIG_CPU_BIG_ENDIAN 285 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r)) 286 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r) + 1) 287 #else 288 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r) + 1) 289 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r)) 290 #endif 291 292 struct kvm_vm_stat { 293 u32 remote_tlb_flush; 294 }; 295 296 struct kvm_vcpu_stat { 297 u32 halt_successful_poll; 298 u32 halt_attempted_poll; 299 u32 halt_poll_invalid; 300 u32 halt_wakeup; 301 u32 hvc_exit_stat; 302 u64 wfe_exit_stat; 303 u64 wfi_exit_stat; 304 u64 mmio_exit_user; 305 u64 mmio_exit_kernel; 306 u64 exits; 307 }; 308 309 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 310 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 311 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 312 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 313 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 314 315 #define KVM_ARCH_WANT_MMU_NOTIFIER 316 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); 317 int kvm_unmap_hva_range(struct kvm *kvm, 318 unsigned long start, unsigned long end); 319 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 320 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 321 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 322 323 /* We do not have shadow page tables, hence the empty hooks */ 324 static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 325 unsigned long address) 326 { 327 } 328 329 struct kvm_vcpu *kvm_arm_get_running_vcpu(void); 330 struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void); 331 void kvm_arm_halt_guest(struct kvm *kvm); 332 void kvm_arm_resume_guest(struct kvm *kvm); 333 void kvm_arm_halt_vcpu(struct kvm_vcpu *vcpu); 334 void kvm_arm_resume_vcpu(struct kvm_vcpu *vcpu); 335 336 u64 __kvm_call_hyp(void *hypfn, ...); 337 #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__) 338 339 void force_vm_exit(const cpumask_t *mask); 340 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); 341 342 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, 343 int exception_index); 344 345 int kvm_perf_init(void); 346 int kvm_perf_teardown(void); 347 348 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 349 350 static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr, 351 unsigned long hyp_stack_ptr, 352 unsigned long vector_ptr) 353 { 354 /* 355 * Call initialization code, and switch to the full blown 356 * HYP code. 357 */ 358 __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr); 359 } 360 361 void __kvm_hyp_teardown(void); 362 static inline void __cpu_reset_hyp_mode(unsigned long vector_ptr, 363 phys_addr_t phys_idmap_start) 364 { 365 kvm_call_hyp(__kvm_hyp_teardown, phys_idmap_start); 366 } 367 368 static inline void kvm_arch_hardware_unsetup(void) {} 369 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 370 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} 371 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 372 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 373 374 void kvm_arm_init_debug(void); 375 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 376 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 377 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 378 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 379 struct kvm_device_attr *attr); 380 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 381 struct kvm_device_attr *attr); 382 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 383 struct kvm_device_attr *attr); 384 385 static inline void __cpu_init_stage2(void) 386 { 387 u32 parange = kvm_call_hyp(__init_stage2_translation); 388 389 WARN_ONCE(parange < 40, 390 "PARange is %d bits, unsupported configuration!", parange); 391 } 392 393 #endif /* __ARM64_KVM_HOST_H__ */ 394