1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/maple_tree.h> 20 #include <linux/percpu.h> 21 #include <linux/psci.h> 22 #include <asm/arch_gicv3.h> 23 #include <asm/barrier.h> 24 #include <asm/cpufeature.h> 25 #include <asm/cputype.h> 26 #include <asm/daifflags.h> 27 #include <asm/fpsimd.h> 28 #include <asm/kvm.h> 29 #include <asm/kvm_asm.h> 30 31 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 32 33 #define KVM_HALT_POLL_NS_DEFAULT 500000 34 35 #include <kvm/arm_vgic.h> 36 #include <kvm/arm_arch_timer.h> 37 #include <kvm/arm_pmu.h> 38 39 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 40 41 #define KVM_VCPU_MAX_FEATURES 7 42 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) 43 44 #define KVM_REQ_SLEEP \ 45 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 46 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 47 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 48 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 49 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 50 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 51 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 52 53 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 54 KVM_DIRTY_LOG_INITIALLY_SET) 55 56 #define KVM_HAVE_MMU_RWLOCK 57 58 /* 59 * Mode of operation configurable with kvm-arm.mode early param. 60 * See Documentation/admin-guide/kernel-parameters.txt for more information. 61 */ 62 enum kvm_mode { 63 KVM_MODE_DEFAULT, 64 KVM_MODE_PROTECTED, 65 KVM_MODE_NV, 66 KVM_MODE_NONE, 67 }; 68 #ifdef CONFIG_KVM 69 enum kvm_mode kvm_get_mode(void); 70 #else 71 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; 72 #endif 73 74 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 75 76 extern unsigned int __ro_after_init kvm_sve_max_vl; 77 int __init kvm_arm_init_sve(void); 78 79 u32 __attribute_const__ kvm_target_cpu(void); 80 int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 81 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 82 83 struct kvm_hyp_memcache { 84 phys_addr_t head; 85 unsigned long nr_pages; 86 }; 87 88 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc, 89 phys_addr_t *p, 90 phys_addr_t (*to_pa)(void *virt)) 91 { 92 *p = mc->head; 93 mc->head = to_pa(p); 94 mc->nr_pages++; 95 } 96 97 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc, 98 void *(*to_va)(phys_addr_t phys)) 99 { 100 phys_addr_t *p = to_va(mc->head); 101 102 if (!mc->nr_pages) 103 return NULL; 104 105 mc->head = *p; 106 mc->nr_pages--; 107 108 return p; 109 } 110 111 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc, 112 unsigned long min_pages, 113 void *(*alloc_fn)(void *arg), 114 phys_addr_t (*to_pa)(void *virt), 115 void *arg) 116 { 117 while (mc->nr_pages < min_pages) { 118 phys_addr_t *p = alloc_fn(arg); 119 120 if (!p) 121 return -ENOMEM; 122 push_hyp_memcache(mc, p, to_pa); 123 } 124 125 return 0; 126 } 127 128 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc, 129 void (*free_fn)(void *virt, void *arg), 130 void *(*to_va)(phys_addr_t phys), 131 void *arg) 132 { 133 while (mc->nr_pages) 134 free_fn(pop_hyp_memcache(mc, to_va), arg); 135 } 136 137 void free_hyp_memcache(struct kvm_hyp_memcache *mc); 138 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages); 139 140 struct kvm_vmid { 141 atomic64_t id; 142 }; 143 144 struct kvm_s2_mmu { 145 struct kvm_vmid vmid; 146 147 /* 148 * stage2 entry level table 149 * 150 * Two kvm_s2_mmu structures in the same VM can point to the same 151 * pgd here. This happens when running a guest using a 152 * translation regime that isn't affected by its own stage-2 153 * translation, such as a non-VHE hypervisor running at vEL2, or 154 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 155 * canonical stage-2 page tables. 156 */ 157 phys_addr_t pgd_phys; 158 struct kvm_pgtable *pgt; 159 160 /* The last vcpu id that ran on each physical CPU */ 161 int __percpu *last_vcpu_ran; 162 163 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0 164 /* 165 * Memory cache used to split 166 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It 167 * is used to allocate stage2 page tables while splitting huge 168 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 169 * influences both the capacity of the split page cache, and 170 * how often KVM reschedules. Be wary of raising CHUNK_SIZE 171 * too high. 172 * 173 * Protected by kvm->slots_lock. 174 */ 175 struct kvm_mmu_memory_cache split_page_cache; 176 uint64_t split_page_chunk_size; 177 178 struct kvm_arch *arch; 179 }; 180 181 struct kvm_arch_memory_slot { 182 }; 183 184 /** 185 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 186 * 187 * @std_bmap: Bitmap of standard secure service calls 188 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 189 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 190 */ 191 struct kvm_smccc_features { 192 unsigned long std_bmap; 193 unsigned long std_hyp_bmap; 194 unsigned long vendor_hyp_bmap; 195 }; 196 197 typedef unsigned int pkvm_handle_t; 198 199 struct kvm_protected_vm { 200 pkvm_handle_t handle; 201 struct kvm_hyp_memcache teardown_mc; 202 }; 203 204 struct kvm_arch { 205 struct kvm_s2_mmu mmu; 206 207 /* VTCR_EL2 value for this VM */ 208 u64 vtcr; 209 210 /* Interrupt controller */ 211 struct vgic_dist vgic; 212 213 /* Timers */ 214 struct arch_timer_vm_data timer_data; 215 216 /* Mandated version of PSCI */ 217 u32 psci_version; 218 219 /* Protects VM-scoped configuration data */ 220 struct mutex config_lock; 221 222 /* 223 * If we encounter a data abort without valid instruction syndrome 224 * information, report this to user space. User space can (and 225 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 226 * supported. 227 */ 228 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 229 /* Memory Tagging Extension enabled for the guest */ 230 #define KVM_ARCH_FLAG_MTE_ENABLED 1 231 /* At least one vCPU has ran in the VM */ 232 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 233 /* The vCPU feature set for the VM is configured */ 234 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3 235 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 236 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 237 /* VM counter offset */ 238 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 239 /* Timer PPIs made immutable */ 240 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 241 /* SMCCC filter initialized for the VM */ 242 #define KVM_ARCH_FLAG_SMCCC_FILTER_CONFIGURED 7 243 /* Initial ID reg values loaded */ 244 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 8 245 unsigned long flags; 246 247 /* VM-wide vCPU feature set */ 248 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); 249 250 /* 251 * VM-wide PMU filter, implemented as a bitmap and big enough for 252 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 253 */ 254 unsigned long *pmu_filter; 255 struct arm_pmu *arm_pmu; 256 257 cpumask_var_t supported_cpus; 258 259 /* Hypercall features firmware registers' descriptor */ 260 struct kvm_smccc_features smccc_feat; 261 struct maple_tree smccc_filter; 262 263 /* 264 * Emulated CPU ID registers per VM 265 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it 266 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 267 * 268 * These emulated idregs are VM-wide, but accessed from the context of a vCPU. 269 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. 270 */ 271 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) 272 #define IDREG(kvm, id) ((kvm)->arch.id_regs[IDREG_IDX(id)]) 273 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) 274 u64 id_regs[KVM_ARM_ID_REG_NUM]; 275 276 /* 277 * For an untrusted host VM, 'pkvm.handle' is used to lookup 278 * the associated pKVM instance in the hypervisor. 279 */ 280 struct kvm_protected_vm pkvm; 281 }; 282 283 struct kvm_vcpu_fault_info { 284 u64 esr_el2; /* Hyp Syndrom Register */ 285 u64 far_el2; /* Hyp Fault Address Register */ 286 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 287 u64 disr_el1; /* Deferred [SError] Status Register */ 288 }; 289 290 enum vcpu_sysreg { 291 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 292 MPIDR_EL1, /* MultiProcessor Affinity Register */ 293 CLIDR_EL1, /* Cache Level ID Register */ 294 CSSELR_EL1, /* Cache Size Selection Register */ 295 SCTLR_EL1, /* System Control Register */ 296 ACTLR_EL1, /* Auxiliary Control Register */ 297 CPACR_EL1, /* Coprocessor Access Control */ 298 ZCR_EL1, /* SVE Control */ 299 TTBR0_EL1, /* Translation Table Base Register 0 */ 300 TTBR1_EL1, /* Translation Table Base Register 1 */ 301 TCR_EL1, /* Translation Control Register */ 302 TCR2_EL1, /* Extended Translation Control Register */ 303 ESR_EL1, /* Exception Syndrome Register */ 304 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ 305 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ 306 FAR_EL1, /* Fault Address Register */ 307 MAIR_EL1, /* Memory Attribute Indirection Register */ 308 VBAR_EL1, /* Vector Base Address Register */ 309 CONTEXTIDR_EL1, /* Context ID Register */ 310 TPIDR_EL0, /* Thread ID, User R/W */ 311 TPIDRRO_EL0, /* Thread ID, User R/O */ 312 TPIDR_EL1, /* Thread ID, Privileged */ 313 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ 314 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 315 PAR_EL1, /* Physical Address Register */ 316 MDSCR_EL1, /* Monitor Debug System Control Register */ 317 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 318 OSLSR_EL1, /* OS Lock Status Register */ 319 DISR_EL1, /* Deferred Interrupt Status Register */ 320 321 /* Performance Monitors Registers */ 322 PMCR_EL0, /* Control Register */ 323 PMSELR_EL0, /* Event Counter Selection Register */ 324 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 325 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 326 PMCCNTR_EL0, /* Cycle Counter Register */ 327 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 328 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 329 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 330 PMCNTENSET_EL0, /* Count Enable Set Register */ 331 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 332 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 333 PMUSERENR_EL0, /* User Enable Register */ 334 335 /* Pointer Authentication Registers in a strict increasing order. */ 336 APIAKEYLO_EL1, 337 APIAKEYHI_EL1, 338 APIBKEYLO_EL1, 339 APIBKEYHI_EL1, 340 APDAKEYLO_EL1, 341 APDAKEYHI_EL1, 342 APDBKEYLO_EL1, 343 APDBKEYHI_EL1, 344 APGAKEYLO_EL1, 345 APGAKEYHI_EL1, 346 347 ELR_EL1, 348 SP_EL1, 349 SPSR_EL1, 350 351 CNTVOFF_EL2, 352 CNTV_CVAL_EL0, 353 CNTV_CTL_EL0, 354 CNTP_CVAL_EL0, 355 CNTP_CTL_EL0, 356 357 /* Memory Tagging Extension registers */ 358 RGSR_EL1, /* Random Allocation Tag Seed Register */ 359 GCR_EL1, /* Tag Control Register */ 360 TFSR_EL1, /* Tag Fault Status Register (EL1) */ 361 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 362 363 /* Permission Indirection Extension registers */ 364 PIR_EL1, /* Permission Indirection Register 1 (EL1) */ 365 PIRE0_EL1, /* Permission Indirection Register 0 (EL1) */ 366 367 /* 32bit specific registers. */ 368 DACR32_EL2, /* Domain Access Control Register */ 369 IFSR32_EL2, /* Instruction Fault Status Register */ 370 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 371 DBGVCR32_EL2, /* Debug Vector Catch Register */ 372 373 /* EL2 registers */ 374 VPIDR_EL2, /* Virtualization Processor ID Register */ 375 VMPIDR_EL2, /* Virtualization Multiprocessor ID Register */ 376 SCTLR_EL2, /* System Control Register (EL2) */ 377 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 378 HCR_EL2, /* Hypervisor Configuration Register */ 379 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ 380 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 381 HSTR_EL2, /* Hypervisor System Trap Register */ 382 HACR_EL2, /* Hypervisor Auxiliary Control Register */ 383 HCRX_EL2, /* Extended Hypervisor Configuration Register */ 384 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ 385 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ 386 TCR_EL2, /* Translation Control Register (EL2) */ 387 VTTBR_EL2, /* Virtualization Translation Table Base Register */ 388 VTCR_EL2, /* Virtualization Translation Control Register */ 389 SPSR_EL2, /* EL2 saved program status register */ 390 ELR_EL2, /* EL2 exception link register */ 391 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ 392 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ 393 ESR_EL2, /* Exception Syndrome Register (EL2) */ 394 FAR_EL2, /* Fault Address Register (EL2) */ 395 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ 396 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ 397 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ 398 VBAR_EL2, /* Vector Base Address Register (EL2) */ 399 RVBAR_EL2, /* Reset Vector Base Address Register */ 400 CONTEXTIDR_EL2, /* Context ID Register (EL2) */ 401 TPIDR_EL2, /* EL2 Software Thread ID Register */ 402 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ 403 SP_EL2, /* EL2 Stack Pointer */ 404 HFGRTR_EL2, 405 HFGWTR_EL2, 406 HFGITR_EL2, 407 HDFGRTR_EL2, 408 HDFGWTR_EL2, 409 CNTHP_CTL_EL2, 410 CNTHP_CVAL_EL2, 411 CNTHV_CTL_EL2, 412 CNTHV_CVAL_EL2, 413 414 NR_SYS_REGS /* Nothing after this line! */ 415 }; 416 417 struct kvm_cpu_context { 418 struct user_pt_regs regs; /* sp = sp_el0 */ 419 420 u64 spsr_abt; 421 u64 spsr_und; 422 u64 spsr_irq; 423 u64 spsr_fiq; 424 425 struct user_fpsimd_state fp_regs; 426 427 u64 sys_regs[NR_SYS_REGS]; 428 429 struct kvm_vcpu *__hyp_running_vcpu; 430 }; 431 432 struct kvm_host_data { 433 struct kvm_cpu_context host_ctxt; 434 }; 435 436 struct kvm_host_psci_config { 437 /* PSCI version used by host. */ 438 u32 version; 439 u32 smccc_version; 440 441 /* Function IDs used by host if version is v0.1. */ 442 struct psci_0_1_function_ids function_ids_0_1; 443 444 bool psci_0_1_cpu_suspend_implemented; 445 bool psci_0_1_cpu_on_implemented; 446 bool psci_0_1_cpu_off_implemented; 447 bool psci_0_1_migrate_implemented; 448 }; 449 450 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 451 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 452 453 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 454 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 455 456 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 457 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 458 459 struct vcpu_reset_state { 460 unsigned long pc; 461 unsigned long r0; 462 bool be; 463 bool reset; 464 }; 465 466 struct kvm_vcpu_arch { 467 struct kvm_cpu_context ctxt; 468 469 /* 470 * Guest floating point state 471 * 472 * The architecture has two main floating point extensions, 473 * the original FPSIMD and SVE. These have overlapping 474 * register views, with the FPSIMD V registers occupying the 475 * low 128 bits of the SVE Z registers. When the core 476 * floating point code saves the register state of a task it 477 * records which view it saved in fp_type. 478 */ 479 void *sve_state; 480 enum fp_type fp_type; 481 unsigned int sve_max_vl; 482 u64 svcr; 483 484 /* Stage 2 paging state used by the hardware on next switch */ 485 struct kvm_s2_mmu *hw_mmu; 486 487 /* Values of trap registers for the guest. */ 488 u64 hcr_el2; 489 u64 mdcr_el2; 490 u64 cptr_el2; 491 492 /* Values of trap registers for the host before guest entry. */ 493 u64 mdcr_el2_host; 494 495 /* Exception Information */ 496 struct kvm_vcpu_fault_info fault; 497 498 /* Ownership of the FP regs */ 499 enum { 500 FP_STATE_FREE, 501 FP_STATE_HOST_OWNED, 502 FP_STATE_GUEST_OWNED, 503 } fp_state; 504 505 /* Configuration flags, set once and for all before the vcpu can run */ 506 u8 cflags; 507 508 /* Input flags to the hypervisor code, potentially cleared after use */ 509 u8 iflags; 510 511 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 512 u8 sflags; 513 514 /* 515 * Don't run the guest (internal implementation need). 516 * 517 * Contrary to the flags above, this is set/cleared outside of 518 * a vcpu context, and thus cannot be mixed with the flags 519 * themselves (or the flag accesses need to be made atomic). 520 */ 521 bool pause; 522 523 /* 524 * We maintain more than a single set of debug registers to support 525 * debugging the guest from the host and to maintain separate host and 526 * guest state during world switches. vcpu_debug_state are the debug 527 * registers of the vcpu as the guest sees them. host_debug_state are 528 * the host registers which are saved and restored during 529 * world switches. external_debug_state contains the debug 530 * values we want to debug the guest. This is set via the 531 * KVM_SET_GUEST_DEBUG ioctl. 532 * 533 * debug_ptr points to the set of debug registers that should be loaded 534 * onto the hardware when running the guest. 535 */ 536 struct kvm_guest_debug_arch *debug_ptr; 537 struct kvm_guest_debug_arch vcpu_debug_state; 538 struct kvm_guest_debug_arch external_debug_state; 539 540 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ 541 struct task_struct *parent_task; 542 543 struct { 544 /* {Break,watch}point registers */ 545 struct kvm_guest_debug_arch regs; 546 /* Statistical profiling extension */ 547 u64 pmscr_el1; 548 /* Self-hosted trace */ 549 u64 trfcr_el1; 550 } host_debug_state; 551 552 /* VGIC state */ 553 struct vgic_cpu vgic_cpu; 554 struct arch_timer_cpu timer_cpu; 555 struct kvm_pmu pmu; 556 557 /* 558 * Guest registers we preserve during guest debugging. 559 * 560 * These shadow registers are updated by the kvm_handle_sys_reg 561 * trap handler if the guest accesses or updates them while we 562 * are using guest debug. 563 */ 564 struct { 565 u32 mdscr_el1; 566 bool pstate_ss; 567 } guest_debug_preserved; 568 569 /* vcpu power state */ 570 struct kvm_mp_state mp_state; 571 spinlock_t mp_state_lock; 572 573 /* Cache some mmu pages needed inside spinlock regions */ 574 struct kvm_mmu_memory_cache mmu_page_cache; 575 576 /* Target CPU and feature flags */ 577 int target; 578 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); 579 580 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 581 u64 vsesr_el2; 582 583 /* Additional reset state */ 584 struct vcpu_reset_state reset_state; 585 586 /* Guest PV state */ 587 struct { 588 u64 last_steal; 589 gpa_t base; 590 } steal; 591 592 /* Per-vcpu CCSIDR override or NULL */ 593 u32 *ccsidr; 594 }; 595 596 /* 597 * Each 'flag' is composed of a comma-separated triplet: 598 * 599 * - the flag-set it belongs to in the vcpu->arch structure 600 * - the value for that flag 601 * - the mask for that flag 602 * 603 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 604 * unpack_vcpu_flag() extract the flag value from the triplet for 605 * direct use outside of the flag accessors. 606 */ 607 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 608 609 #define __unpack_flag(_set, _f, _m) _f 610 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 611 612 #define __build_check_flag(v, flagset, f, m) \ 613 do { \ 614 typeof(v->arch.flagset) *_fset; \ 615 \ 616 /* Check that the flags fit in the mask */ \ 617 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 618 /* Check that the flags fit in the type */ \ 619 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 620 } while (0) 621 622 #define __vcpu_get_flag(v, flagset, f, m) \ 623 ({ \ 624 __build_check_flag(v, flagset, f, m); \ 625 \ 626 READ_ONCE(v->arch.flagset) & (m); \ 627 }) 628 629 /* 630 * Note that the set/clear accessors must be preempt-safe in order to 631 * avoid nesting them with load/put which also manipulate flags... 632 */ 633 #ifdef __KVM_NVHE_HYPERVISOR__ 634 /* the nVHE hypervisor is always non-preemptible */ 635 #define __vcpu_flags_preempt_disable() 636 #define __vcpu_flags_preempt_enable() 637 #else 638 #define __vcpu_flags_preempt_disable() preempt_disable() 639 #define __vcpu_flags_preempt_enable() preempt_enable() 640 #endif 641 642 #define __vcpu_set_flag(v, flagset, f, m) \ 643 do { \ 644 typeof(v->arch.flagset) *fset; \ 645 \ 646 __build_check_flag(v, flagset, f, m); \ 647 \ 648 fset = &v->arch.flagset; \ 649 __vcpu_flags_preempt_disable(); \ 650 if (HWEIGHT(m) > 1) \ 651 *fset &= ~(m); \ 652 *fset |= (f); \ 653 __vcpu_flags_preempt_enable(); \ 654 } while (0) 655 656 #define __vcpu_clear_flag(v, flagset, f, m) \ 657 do { \ 658 typeof(v->arch.flagset) *fset; \ 659 \ 660 __build_check_flag(v, flagset, f, m); \ 661 \ 662 fset = &v->arch.flagset; \ 663 __vcpu_flags_preempt_disable(); \ 664 *fset &= ~(m); \ 665 __vcpu_flags_preempt_enable(); \ 666 } while (0) 667 668 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 669 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 670 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 671 672 /* SVE exposed to guest */ 673 #define GUEST_HAS_SVE __vcpu_single_flag(cflags, BIT(0)) 674 /* SVE config completed */ 675 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 676 /* PTRAUTH exposed to guest */ 677 #define GUEST_HAS_PTRAUTH __vcpu_single_flag(cflags, BIT(2)) 678 679 /* Exception pending */ 680 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 681 /* 682 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 683 * be set together with an exception... 684 */ 685 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 686 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 687 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 688 689 /* Helpers to encode exceptions with minimum fuss */ 690 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 691 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 692 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 693 694 /* 695 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 696 * values: 697 * 698 * For AArch32 EL1: 699 */ 700 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 701 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 702 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 703 /* For AArch64: */ 704 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 705 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 706 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 707 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 708 /* For AArch64 with NV: */ 709 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 710 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 711 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 712 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 713 /* Guest debug is live */ 714 #define DEBUG_DIRTY __vcpu_single_flag(iflags, BIT(4)) 715 /* Save SPE context if active */ 716 #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5)) 717 /* Save TRBE context if active */ 718 #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) 719 /* vcpu running in HYP context */ 720 #define VCPU_HYP_CONTEXT __vcpu_single_flag(iflags, BIT(7)) 721 722 /* SVE enabled for host EL0 */ 723 #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) 724 /* SME enabled for EL0 */ 725 #define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1)) 726 /* Physical CPU not in supported_cpus */ 727 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2)) 728 /* WFIT instruction trapped */ 729 #define IN_WFIT __vcpu_single_flag(sflags, BIT(3)) 730 /* vcpu system registers loaded on physical CPU */ 731 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(4)) 732 /* Software step state is Active-pending */ 733 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5)) 734 /* PMUSERENR for the guest EL0 is on physical CPU */ 735 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(6)) 736 /* WFI instruction trapped */ 737 #define IN_WFI __vcpu_single_flag(sflags, BIT(7)) 738 739 740 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 741 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 742 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 743 744 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 745 746 #define vcpu_sve_state_size(vcpu) ({ \ 747 size_t __size_ret; \ 748 unsigned int __vcpu_vq; \ 749 \ 750 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ 751 __size_ret = 0; \ 752 } else { \ 753 __vcpu_vq = vcpu_sve_max_vq(vcpu); \ 754 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ 755 } \ 756 \ 757 __size_ret; \ 758 }) 759 760 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 761 KVM_GUESTDBG_USE_SW_BP | \ 762 KVM_GUESTDBG_USE_HW | \ 763 KVM_GUESTDBG_SINGLESTEP) 764 765 #define vcpu_has_sve(vcpu) (system_supports_sve() && \ 766 vcpu_get_flag(vcpu, GUEST_HAS_SVE)) 767 768 #ifdef CONFIG_ARM64_PTR_AUTH 769 #define vcpu_has_ptrauth(vcpu) \ 770 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 771 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 772 vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH)) 773 #else 774 #define vcpu_has_ptrauth(vcpu) false 775 #endif 776 777 #define vcpu_on_unsupported_cpu(vcpu) \ 778 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 779 780 #define vcpu_set_on_unsupported_cpu(vcpu) \ 781 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 782 783 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 784 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 785 786 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 787 788 /* 789 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 790 * memory backed version of a register, and not the one most recently 791 * accessed by a running VCPU. For example, for userspace access or 792 * for system registers that are never context switched, but only 793 * emulated. 794 */ 795 #define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)]) 796 797 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 798 799 #define __vcpu_sys_reg(v,r) (ctxt_sys_reg(&(v)->arch.ctxt, (r))) 800 801 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 802 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 803 804 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 805 { 806 /* 807 * *** VHE ONLY *** 808 * 809 * System registers listed in the switch are not saved on every 810 * exit from the guest but are only saved on vcpu_put. 811 * 812 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 813 * should never be listed below, because the guest cannot modify its 814 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 815 * thread when emulating cross-VCPU communication. 816 */ 817 if (!has_vhe()) 818 return false; 819 820 switch (reg) { 821 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; 822 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; 823 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; 824 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; 825 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; 826 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; 827 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; 828 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; 829 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; 830 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; 831 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; 832 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 833 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; 834 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 835 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; 836 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; 837 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 838 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; 839 case PAR_EL1: *val = read_sysreg_par(); break; 840 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; 841 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; 842 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 843 default: return false; 844 } 845 846 return true; 847 } 848 849 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 850 { 851 /* 852 * *** VHE ONLY *** 853 * 854 * System registers listed in the switch are not restored on every 855 * entry to the guest but are only restored on vcpu_load. 856 * 857 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 858 * should never be listed below, because the MPIDR should only be set 859 * once, before running the VCPU, and never changed later. 860 */ 861 if (!has_vhe()) 862 return false; 863 864 switch (reg) { 865 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 866 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 867 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 868 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 869 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 870 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 871 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 872 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 873 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 874 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 875 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 876 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 877 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 878 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 879 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 880 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 881 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 882 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 883 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 884 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 885 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 886 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 887 default: return false; 888 } 889 890 return true; 891 } 892 893 struct kvm_vm_stat { 894 struct kvm_vm_stat_generic generic; 895 }; 896 897 struct kvm_vcpu_stat { 898 struct kvm_vcpu_stat_generic generic; 899 u64 hvc_exit_stat; 900 u64 wfe_exit_stat; 901 u64 wfi_exit_stat; 902 u64 mmio_exit_user; 903 u64 mmio_exit_kernel; 904 u64 signal_exits; 905 u64 exits; 906 }; 907 908 void kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 909 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 910 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 911 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 912 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 913 914 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 915 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 916 917 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 918 struct kvm_vcpu_events *events); 919 920 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 921 struct kvm_vcpu_events *events); 922 923 #define KVM_ARCH_WANT_MMU_NOTIFIER 924 925 void kvm_arm_halt_guest(struct kvm *kvm); 926 void kvm_arm_resume_guest(struct kvm *kvm); 927 928 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid) 929 930 #ifndef __KVM_NVHE_HYPERVISOR__ 931 #define kvm_call_hyp_nvhe(f, ...) \ 932 ({ \ 933 struct arm_smccc_res res; \ 934 \ 935 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 936 ##__VA_ARGS__, &res); \ 937 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 938 \ 939 res.a1; \ 940 }) 941 942 /* 943 * The couple of isb() below are there to guarantee the same behaviour 944 * on VHE as on !VHE, where the eret to EL1 acts as a context 945 * synchronization event. 946 */ 947 #define kvm_call_hyp(f, ...) \ 948 do { \ 949 if (has_vhe()) { \ 950 f(__VA_ARGS__); \ 951 isb(); \ 952 } else { \ 953 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 954 } \ 955 } while(0) 956 957 #define kvm_call_hyp_ret(f, ...) \ 958 ({ \ 959 typeof(f(__VA_ARGS__)) ret; \ 960 \ 961 if (has_vhe()) { \ 962 ret = f(__VA_ARGS__); \ 963 isb(); \ 964 } else { \ 965 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 966 } \ 967 \ 968 ret; \ 969 }) 970 #else /* __KVM_NVHE_HYPERVISOR__ */ 971 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 972 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 973 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 974 #endif /* __KVM_NVHE_HYPERVISOR__ */ 975 976 void force_vm_exit(const cpumask_t *mask); 977 978 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 979 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 980 981 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 982 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 983 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 984 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 985 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 986 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 987 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 988 989 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 990 991 int __init kvm_sys_reg_table_init(void); 992 int __init populate_nv_trap_config(void); 993 994 bool lock_all_vcpus(struct kvm *kvm); 995 void unlock_all_vcpus(struct kvm *kvm); 996 997 /* MMIO helpers */ 998 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 999 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 1000 1001 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 1002 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 1003 1004 /* 1005 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 1006 * arrived in guest context. For arm64, any event that arrives while a vCPU is 1007 * loaded is considered to be "in guest". 1008 */ 1009 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 1010 { 1011 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 1012 } 1013 1014 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 1015 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 1016 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 1017 1018 bool kvm_arm_pvtime_supported(void); 1019 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 1020 struct kvm_device_attr *attr); 1021 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 1022 struct kvm_device_attr *attr); 1023 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 1024 struct kvm_device_attr *attr); 1025 1026 extern unsigned int __ro_after_init kvm_arm_vmid_bits; 1027 int __init kvm_arm_vmid_alloc_init(void); 1028 void __init kvm_arm_vmid_alloc_free(void); 1029 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 1030 void kvm_arm_vmid_clear_active(void); 1031 1032 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 1033 { 1034 vcpu_arch->steal.base = INVALID_GPA; 1035 } 1036 1037 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 1038 { 1039 return (vcpu_arch->steal.base != INVALID_GPA); 1040 } 1041 1042 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); 1043 1044 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 1045 1046 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 1047 1048 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 1049 { 1050 /* The host's MPIDR is immutable, so let's set it up at boot time */ 1051 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 1052 } 1053 1054 static inline bool kvm_system_needs_idmapped_vectors(void) 1055 { 1056 return cpus_have_const_cap(ARM64_SPECTRE_V3A); 1057 } 1058 1059 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu); 1060 1061 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 1062 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 1063 1064 void kvm_arm_init_debug(void); 1065 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu); 1066 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 1067 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 1068 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 1069 1070 #define kvm_vcpu_os_lock_enabled(vcpu) \ 1071 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK)) 1072 1073 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 1074 struct kvm_device_attr *attr); 1075 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 1076 struct kvm_device_attr *attr); 1077 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 1078 struct kvm_device_attr *attr); 1079 1080 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 1081 struct kvm_arm_copy_mte_tags *copy_tags); 1082 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, 1083 struct kvm_arm_counter_offset *offset); 1084 1085 /* Guest/host FPSIMD coordination helpers */ 1086 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); 1087 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 1088 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 1089 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 1090 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 1091 void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu); 1092 1093 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 1094 { 1095 return (!has_vhe() && attr->exclude_host); 1096 } 1097 1098 /* Flags for host debug state */ 1099 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu); 1100 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu); 1101 1102 #ifdef CONFIG_KVM 1103 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); 1104 void kvm_clr_pmu_events(u32 clr); 1105 bool kvm_set_pmuserenr(u64 val); 1106 #else 1107 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} 1108 static inline void kvm_clr_pmu_events(u32 clr) {} 1109 static inline bool kvm_set_pmuserenr(u64 val) 1110 { 1111 return false; 1112 } 1113 #endif 1114 1115 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu); 1116 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu); 1117 1118 int __init kvm_set_ipa_limit(void); 1119 1120 #define __KVM_HAVE_ARCH_VM_ALLOC 1121 struct kvm *kvm_arch_alloc_vm(void); 1122 1123 static inline bool kvm_vm_is_protected(struct kvm *kvm) 1124 { 1125 return false; 1126 } 1127 1128 void kvm_init_protected_traps(struct kvm_vcpu *vcpu); 1129 1130 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 1131 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 1132 1133 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 1134 1135 #define kvm_has_mte(kvm) \ 1136 (system_supports_mte() && \ 1137 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 1138 1139 #define kvm_supports_32bit_el0() \ 1140 (system_supports_32bit_el0() && \ 1141 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1142 1143 #define kvm_vm_has_ran_once(kvm) \ 1144 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) 1145 1146 int kvm_trng_call(struct kvm_vcpu *vcpu); 1147 #ifdef CONFIG_KVM 1148 extern phys_addr_t hyp_mem_base; 1149 extern phys_addr_t hyp_mem_size; 1150 void __init kvm_hyp_reserve(void); 1151 #else 1152 static inline void kvm_hyp_reserve(void) { } 1153 #endif 1154 1155 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 1156 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 1157 1158 #endif /* __ARM64_KVM_HOST_H__ */ 1159