1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/arm-smccc.h> 15 #include <linux/bitmap.h> 16 #include <linux/types.h> 17 #include <linux/jump_label.h> 18 #include <linux/kvm_types.h> 19 #include <linux/maple_tree.h> 20 #include <linux/percpu.h> 21 #include <linux/psci.h> 22 #include <asm/arch_gicv3.h> 23 #include <asm/barrier.h> 24 #include <asm/cpufeature.h> 25 #include <asm/cputype.h> 26 #include <asm/daifflags.h> 27 #include <asm/fpsimd.h> 28 #include <asm/kvm.h> 29 #include <asm/kvm_asm.h> 30 31 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 32 33 #define KVM_HALT_POLL_NS_DEFAULT 500000 34 35 #include <kvm/arm_vgic.h> 36 #include <kvm/arm_arch_timer.h> 37 #include <kvm/arm_pmu.h> 38 39 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 40 41 #define KVM_VCPU_MAX_FEATURES 7 42 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) 43 44 #define KVM_REQ_SLEEP \ 45 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 46 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 47 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 48 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 49 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 50 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5) 51 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6) 52 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7) 53 54 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 55 KVM_DIRTY_LOG_INITIALLY_SET) 56 57 #define KVM_HAVE_MMU_RWLOCK 58 59 /* 60 * Mode of operation configurable with kvm-arm.mode early param. 61 * See Documentation/admin-guide/kernel-parameters.txt for more information. 62 */ 63 enum kvm_mode { 64 KVM_MODE_DEFAULT, 65 KVM_MODE_PROTECTED, 66 KVM_MODE_NV, 67 KVM_MODE_NONE, 68 }; 69 #ifdef CONFIG_KVM 70 enum kvm_mode kvm_get_mode(void); 71 #else 72 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; 73 #endif 74 75 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 76 77 extern unsigned int __ro_after_init kvm_sve_max_vl; 78 int __init kvm_arm_init_sve(void); 79 80 u32 __attribute_const__ kvm_target_cpu(void); 81 int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 82 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 83 84 struct kvm_hyp_memcache { 85 phys_addr_t head; 86 unsigned long nr_pages; 87 }; 88 89 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc, 90 phys_addr_t *p, 91 phys_addr_t (*to_pa)(void *virt)) 92 { 93 *p = mc->head; 94 mc->head = to_pa(p); 95 mc->nr_pages++; 96 } 97 98 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc, 99 void *(*to_va)(phys_addr_t phys)) 100 { 101 phys_addr_t *p = to_va(mc->head); 102 103 if (!mc->nr_pages) 104 return NULL; 105 106 mc->head = *p; 107 mc->nr_pages--; 108 109 return p; 110 } 111 112 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc, 113 unsigned long min_pages, 114 void *(*alloc_fn)(void *arg), 115 phys_addr_t (*to_pa)(void *virt), 116 void *arg) 117 { 118 while (mc->nr_pages < min_pages) { 119 phys_addr_t *p = alloc_fn(arg); 120 121 if (!p) 122 return -ENOMEM; 123 push_hyp_memcache(mc, p, to_pa); 124 } 125 126 return 0; 127 } 128 129 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc, 130 void (*free_fn)(void *virt, void *arg), 131 void *(*to_va)(phys_addr_t phys), 132 void *arg) 133 { 134 while (mc->nr_pages) 135 free_fn(pop_hyp_memcache(mc, to_va), arg); 136 } 137 138 void free_hyp_memcache(struct kvm_hyp_memcache *mc); 139 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages); 140 141 struct kvm_vmid { 142 atomic64_t id; 143 }; 144 145 struct kvm_s2_mmu { 146 struct kvm_vmid vmid; 147 148 /* 149 * stage2 entry level table 150 * 151 * Two kvm_s2_mmu structures in the same VM can point to the same 152 * pgd here. This happens when running a guest using a 153 * translation regime that isn't affected by its own stage-2 154 * translation, such as a non-VHE hypervisor running at vEL2, or 155 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the 156 * canonical stage-2 page tables. 157 */ 158 phys_addr_t pgd_phys; 159 struct kvm_pgtable *pgt; 160 161 /* The last vcpu id that ran on each physical CPU */ 162 int __percpu *last_vcpu_ran; 163 164 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0 165 /* 166 * Memory cache used to split 167 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It 168 * is used to allocate stage2 page tables while splitting huge 169 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 170 * influences both the capacity of the split page cache, and 171 * how often KVM reschedules. Be wary of raising CHUNK_SIZE 172 * too high. 173 * 174 * Protected by kvm->slots_lock. 175 */ 176 struct kvm_mmu_memory_cache split_page_cache; 177 uint64_t split_page_chunk_size; 178 179 struct kvm_arch *arch; 180 }; 181 182 struct kvm_arch_memory_slot { 183 }; 184 185 /** 186 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests 187 * 188 * @std_bmap: Bitmap of standard secure service calls 189 * @std_hyp_bmap: Bitmap of standard hypervisor service calls 190 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls 191 */ 192 struct kvm_smccc_features { 193 unsigned long std_bmap; 194 unsigned long std_hyp_bmap; 195 unsigned long vendor_hyp_bmap; 196 }; 197 198 typedef unsigned int pkvm_handle_t; 199 200 struct kvm_protected_vm { 201 pkvm_handle_t handle; 202 struct kvm_hyp_memcache teardown_mc; 203 }; 204 205 struct kvm_arch { 206 struct kvm_s2_mmu mmu; 207 208 /* VTCR_EL2 value for this VM */ 209 u64 vtcr; 210 211 /* Interrupt controller */ 212 struct vgic_dist vgic; 213 214 /* Timers */ 215 struct arch_timer_vm_data timer_data; 216 217 /* Mandated version of PSCI */ 218 u32 psci_version; 219 220 /* Protects VM-scoped configuration data */ 221 struct mutex config_lock; 222 223 /* 224 * If we encounter a data abort without valid instruction syndrome 225 * information, report this to user space. User space can (and 226 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 227 * supported. 228 */ 229 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0 230 /* Memory Tagging Extension enabled for the guest */ 231 #define KVM_ARCH_FLAG_MTE_ENABLED 1 232 /* At least one vCPU has ran in the VM */ 233 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2 234 /* The vCPU feature set for the VM is configured */ 235 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3 236 /* PSCI SYSTEM_SUSPEND enabled for the guest */ 237 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4 238 /* VM counter offset */ 239 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5 240 /* Timer PPIs made immutable */ 241 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6 242 /* SMCCC filter initialized for the VM */ 243 #define KVM_ARCH_FLAG_SMCCC_FILTER_CONFIGURED 7 244 /* Initial ID reg values loaded */ 245 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 8 246 unsigned long flags; 247 248 /* VM-wide vCPU feature set */ 249 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES); 250 251 /* 252 * VM-wide PMU filter, implemented as a bitmap and big enough for 253 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). 254 */ 255 unsigned long *pmu_filter; 256 struct arm_pmu *arm_pmu; 257 258 cpumask_var_t supported_cpus; 259 260 /* Hypercall features firmware registers' descriptor */ 261 struct kvm_smccc_features smccc_feat; 262 struct maple_tree smccc_filter; 263 264 /* 265 * Emulated CPU ID registers per VM 266 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it 267 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. 268 * 269 * These emulated idregs are VM-wide, but accessed from the context of a vCPU. 270 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock. 271 */ 272 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) 273 #define IDREG(kvm, id) ((kvm)->arch.id_regs[IDREG_IDX(id)]) 274 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1) 275 u64 id_regs[KVM_ARM_ID_REG_NUM]; 276 277 /* 278 * For an untrusted host VM, 'pkvm.handle' is used to lookup 279 * the associated pKVM instance in the hypervisor. 280 */ 281 struct kvm_protected_vm pkvm; 282 }; 283 284 struct kvm_vcpu_fault_info { 285 u64 esr_el2; /* Hyp Syndrom Register */ 286 u64 far_el2; /* Hyp Fault Address Register */ 287 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 288 u64 disr_el1; /* Deferred [SError] Status Register */ 289 }; 290 291 enum vcpu_sysreg { 292 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 293 MPIDR_EL1, /* MultiProcessor Affinity Register */ 294 CLIDR_EL1, /* Cache Level ID Register */ 295 CSSELR_EL1, /* Cache Size Selection Register */ 296 SCTLR_EL1, /* System Control Register */ 297 ACTLR_EL1, /* Auxiliary Control Register */ 298 CPACR_EL1, /* Coprocessor Access Control */ 299 ZCR_EL1, /* SVE Control */ 300 TTBR0_EL1, /* Translation Table Base Register 0 */ 301 TTBR1_EL1, /* Translation Table Base Register 1 */ 302 TCR_EL1, /* Translation Control Register */ 303 TCR2_EL1, /* Extended Translation Control Register */ 304 ESR_EL1, /* Exception Syndrome Register */ 305 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ 306 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ 307 FAR_EL1, /* Fault Address Register */ 308 MAIR_EL1, /* Memory Attribute Indirection Register */ 309 VBAR_EL1, /* Vector Base Address Register */ 310 CONTEXTIDR_EL1, /* Context ID Register */ 311 TPIDR_EL0, /* Thread ID, User R/W */ 312 TPIDRRO_EL0, /* Thread ID, User R/O */ 313 TPIDR_EL1, /* Thread ID, Privileged */ 314 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ 315 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 316 PAR_EL1, /* Physical Address Register */ 317 MDSCR_EL1, /* Monitor Debug System Control Register */ 318 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 319 OSLSR_EL1, /* OS Lock Status Register */ 320 DISR_EL1, /* Deferred Interrupt Status Register */ 321 322 /* Performance Monitors Registers */ 323 PMCR_EL0, /* Control Register */ 324 PMSELR_EL0, /* Event Counter Selection Register */ 325 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 326 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 327 PMCCNTR_EL0, /* Cycle Counter Register */ 328 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 329 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 330 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 331 PMCNTENSET_EL0, /* Count Enable Set Register */ 332 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 333 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 334 PMUSERENR_EL0, /* User Enable Register */ 335 336 /* Pointer Authentication Registers in a strict increasing order. */ 337 APIAKEYLO_EL1, 338 APIAKEYHI_EL1, 339 APIBKEYLO_EL1, 340 APIBKEYHI_EL1, 341 APDAKEYLO_EL1, 342 APDAKEYHI_EL1, 343 APDBKEYLO_EL1, 344 APDBKEYHI_EL1, 345 APGAKEYLO_EL1, 346 APGAKEYHI_EL1, 347 348 ELR_EL1, 349 SP_EL1, 350 SPSR_EL1, 351 352 CNTVOFF_EL2, 353 CNTV_CVAL_EL0, 354 CNTV_CTL_EL0, 355 CNTP_CVAL_EL0, 356 CNTP_CTL_EL0, 357 358 /* Memory Tagging Extension registers */ 359 RGSR_EL1, /* Random Allocation Tag Seed Register */ 360 GCR_EL1, /* Tag Control Register */ 361 TFSR_EL1, /* Tag Fault Status Register (EL1) */ 362 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ 363 364 /* Permission Indirection Extension registers */ 365 PIR_EL1, /* Permission Indirection Register 1 (EL1) */ 366 PIRE0_EL1, /* Permission Indirection Register 0 (EL1) */ 367 368 /* 32bit specific registers. */ 369 DACR32_EL2, /* Domain Access Control Register */ 370 IFSR32_EL2, /* Instruction Fault Status Register */ 371 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 372 DBGVCR32_EL2, /* Debug Vector Catch Register */ 373 374 /* EL2 registers */ 375 VPIDR_EL2, /* Virtualization Processor ID Register */ 376 VMPIDR_EL2, /* Virtualization Multiprocessor ID Register */ 377 SCTLR_EL2, /* System Control Register (EL2) */ 378 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 379 HCR_EL2, /* Hypervisor Configuration Register */ 380 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ 381 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 382 HSTR_EL2, /* Hypervisor System Trap Register */ 383 HACR_EL2, /* Hypervisor Auxiliary Control Register */ 384 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ 385 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ 386 TCR_EL2, /* Translation Control Register (EL2) */ 387 VTTBR_EL2, /* Virtualization Translation Table Base Register */ 388 VTCR_EL2, /* Virtualization Translation Control Register */ 389 SPSR_EL2, /* EL2 saved program status register */ 390 ELR_EL2, /* EL2 exception link register */ 391 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ 392 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */ 393 ESR_EL2, /* Exception Syndrome Register (EL2) */ 394 FAR_EL2, /* Fault Address Register (EL2) */ 395 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */ 396 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */ 397 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */ 398 VBAR_EL2, /* Vector Base Address Register (EL2) */ 399 RVBAR_EL2, /* Reset Vector Base Address Register */ 400 CONTEXTIDR_EL2, /* Context ID Register (EL2) */ 401 TPIDR_EL2, /* EL2 Software Thread ID Register */ 402 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ 403 SP_EL2, /* EL2 Stack Pointer */ 404 CNTHP_CTL_EL2, 405 CNTHP_CVAL_EL2, 406 CNTHV_CTL_EL2, 407 CNTHV_CVAL_EL2, 408 409 NR_SYS_REGS /* Nothing after this line! */ 410 }; 411 412 struct kvm_cpu_context { 413 struct user_pt_regs regs; /* sp = sp_el0 */ 414 415 u64 spsr_abt; 416 u64 spsr_und; 417 u64 spsr_irq; 418 u64 spsr_fiq; 419 420 struct user_fpsimd_state fp_regs; 421 422 u64 sys_regs[NR_SYS_REGS]; 423 424 struct kvm_vcpu *__hyp_running_vcpu; 425 }; 426 427 struct kvm_host_data { 428 struct kvm_cpu_context host_ctxt; 429 }; 430 431 struct kvm_host_psci_config { 432 /* PSCI version used by host. */ 433 u32 version; 434 u32 smccc_version; 435 436 /* Function IDs used by host if version is v0.1. */ 437 struct psci_0_1_function_ids function_ids_0_1; 438 439 bool psci_0_1_cpu_suspend_implemented; 440 bool psci_0_1_cpu_on_implemented; 441 bool psci_0_1_cpu_off_implemented; 442 bool psci_0_1_migrate_implemented; 443 }; 444 445 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); 446 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) 447 448 extern s64 kvm_nvhe_sym(hyp_physvirt_offset); 449 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) 450 451 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; 452 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) 453 454 struct vcpu_reset_state { 455 unsigned long pc; 456 unsigned long r0; 457 bool be; 458 bool reset; 459 }; 460 461 struct kvm_vcpu_arch { 462 struct kvm_cpu_context ctxt; 463 464 /* 465 * Guest floating point state 466 * 467 * The architecture has two main floating point extensions, 468 * the original FPSIMD and SVE. These have overlapping 469 * register views, with the FPSIMD V registers occupying the 470 * low 128 bits of the SVE Z registers. When the core 471 * floating point code saves the register state of a task it 472 * records which view it saved in fp_type. 473 */ 474 void *sve_state; 475 enum fp_type fp_type; 476 unsigned int sve_max_vl; 477 u64 svcr; 478 479 /* Stage 2 paging state used by the hardware on next switch */ 480 struct kvm_s2_mmu *hw_mmu; 481 482 /* Values of trap registers for the guest. */ 483 u64 hcr_el2; 484 u64 mdcr_el2; 485 u64 cptr_el2; 486 487 /* Values of trap registers for the host before guest entry. */ 488 u64 mdcr_el2_host; 489 490 /* Exception Information */ 491 struct kvm_vcpu_fault_info fault; 492 493 /* Ownership of the FP regs */ 494 enum { 495 FP_STATE_FREE, 496 FP_STATE_HOST_OWNED, 497 FP_STATE_GUEST_OWNED, 498 } fp_state; 499 500 /* Configuration flags, set once and for all before the vcpu can run */ 501 u8 cflags; 502 503 /* Input flags to the hypervisor code, potentially cleared after use */ 504 u8 iflags; 505 506 /* State flags for kernel bookkeeping, unused by the hypervisor code */ 507 u8 sflags; 508 509 /* 510 * Don't run the guest (internal implementation need). 511 * 512 * Contrary to the flags above, this is set/cleared outside of 513 * a vcpu context, and thus cannot be mixed with the flags 514 * themselves (or the flag accesses need to be made atomic). 515 */ 516 bool pause; 517 518 /* 519 * We maintain more than a single set of debug registers to support 520 * debugging the guest from the host and to maintain separate host and 521 * guest state during world switches. vcpu_debug_state are the debug 522 * registers of the vcpu as the guest sees them. host_debug_state are 523 * the host registers which are saved and restored during 524 * world switches. external_debug_state contains the debug 525 * values we want to debug the guest. This is set via the 526 * KVM_SET_GUEST_DEBUG ioctl. 527 * 528 * debug_ptr points to the set of debug registers that should be loaded 529 * onto the hardware when running the guest. 530 */ 531 struct kvm_guest_debug_arch *debug_ptr; 532 struct kvm_guest_debug_arch vcpu_debug_state; 533 struct kvm_guest_debug_arch external_debug_state; 534 535 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ 536 struct task_struct *parent_task; 537 538 struct { 539 /* {Break,watch}point registers */ 540 struct kvm_guest_debug_arch regs; 541 /* Statistical profiling extension */ 542 u64 pmscr_el1; 543 /* Self-hosted trace */ 544 u64 trfcr_el1; 545 } host_debug_state; 546 547 /* VGIC state */ 548 struct vgic_cpu vgic_cpu; 549 struct arch_timer_cpu timer_cpu; 550 struct kvm_pmu pmu; 551 552 /* 553 * Guest registers we preserve during guest debugging. 554 * 555 * These shadow registers are updated by the kvm_handle_sys_reg 556 * trap handler if the guest accesses or updates them while we 557 * are using guest debug. 558 */ 559 struct { 560 u32 mdscr_el1; 561 bool pstate_ss; 562 } guest_debug_preserved; 563 564 /* vcpu power state */ 565 struct kvm_mp_state mp_state; 566 spinlock_t mp_state_lock; 567 568 /* Cache some mmu pages needed inside spinlock regions */ 569 struct kvm_mmu_memory_cache mmu_page_cache; 570 571 /* Target CPU and feature flags */ 572 int target; 573 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); 574 575 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 576 u64 vsesr_el2; 577 578 /* Additional reset state */ 579 struct vcpu_reset_state reset_state; 580 581 /* Guest PV state */ 582 struct { 583 u64 last_steal; 584 gpa_t base; 585 } steal; 586 587 /* Per-vcpu CCSIDR override or NULL */ 588 u32 *ccsidr; 589 }; 590 591 /* 592 * Each 'flag' is composed of a comma-separated triplet: 593 * 594 * - the flag-set it belongs to in the vcpu->arch structure 595 * - the value for that flag 596 * - the mask for that flag 597 * 598 * __vcpu_single_flag() builds such a triplet for a single-bit flag. 599 * unpack_vcpu_flag() extract the flag value from the triplet for 600 * direct use outside of the flag accessors. 601 */ 602 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f) 603 604 #define __unpack_flag(_set, _f, _m) _f 605 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__) 606 607 #define __build_check_flag(v, flagset, f, m) \ 608 do { \ 609 typeof(v->arch.flagset) *_fset; \ 610 \ 611 /* Check that the flags fit in the mask */ \ 612 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \ 613 /* Check that the flags fit in the type */ \ 614 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \ 615 } while (0) 616 617 #define __vcpu_get_flag(v, flagset, f, m) \ 618 ({ \ 619 __build_check_flag(v, flagset, f, m); \ 620 \ 621 READ_ONCE(v->arch.flagset) & (m); \ 622 }) 623 624 /* 625 * Note that the set/clear accessors must be preempt-safe in order to 626 * avoid nesting them with load/put which also manipulate flags... 627 */ 628 #ifdef __KVM_NVHE_HYPERVISOR__ 629 /* the nVHE hypervisor is always non-preemptible */ 630 #define __vcpu_flags_preempt_disable() 631 #define __vcpu_flags_preempt_enable() 632 #else 633 #define __vcpu_flags_preempt_disable() preempt_disable() 634 #define __vcpu_flags_preempt_enable() preempt_enable() 635 #endif 636 637 #define __vcpu_set_flag(v, flagset, f, m) \ 638 do { \ 639 typeof(v->arch.flagset) *fset; \ 640 \ 641 __build_check_flag(v, flagset, f, m); \ 642 \ 643 fset = &v->arch.flagset; \ 644 __vcpu_flags_preempt_disable(); \ 645 if (HWEIGHT(m) > 1) \ 646 *fset &= ~(m); \ 647 *fset |= (f); \ 648 __vcpu_flags_preempt_enable(); \ 649 } while (0) 650 651 #define __vcpu_clear_flag(v, flagset, f, m) \ 652 do { \ 653 typeof(v->arch.flagset) *fset; \ 654 \ 655 __build_check_flag(v, flagset, f, m); \ 656 \ 657 fset = &v->arch.flagset; \ 658 __vcpu_flags_preempt_disable(); \ 659 *fset &= ~(m); \ 660 __vcpu_flags_preempt_enable(); \ 661 } while (0) 662 663 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__) 664 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__) 665 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__) 666 667 /* SVE exposed to guest */ 668 #define GUEST_HAS_SVE __vcpu_single_flag(cflags, BIT(0)) 669 /* SVE config completed */ 670 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) 671 /* PTRAUTH exposed to guest */ 672 #define GUEST_HAS_PTRAUTH __vcpu_single_flag(cflags, BIT(2)) 673 674 /* Exception pending */ 675 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0)) 676 /* 677 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't 678 * be set together with an exception... 679 */ 680 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1)) 681 /* Target EL/MODE (not a single flag, but let's abuse the macro) */ 682 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1)) 683 684 /* Helpers to encode exceptions with minimum fuss */ 685 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK) 686 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL) 687 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL 688 689 /* 690 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following 691 * values: 692 * 693 * For AArch32 EL1: 694 */ 695 #define EXCEPT_AA32_UND __vcpu_except_flags(0) 696 #define EXCEPT_AA32_IABT __vcpu_except_flags(1) 697 #define EXCEPT_AA32_DABT __vcpu_except_flags(2) 698 /* For AArch64: */ 699 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0) 700 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1) 701 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2) 702 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3) 703 /* For AArch64 with NV: */ 704 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4) 705 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5) 706 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6) 707 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7) 708 /* Guest debug is live */ 709 #define DEBUG_DIRTY __vcpu_single_flag(iflags, BIT(4)) 710 /* Save SPE context if active */ 711 #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5)) 712 /* Save TRBE context if active */ 713 #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6)) 714 /* vcpu running in HYP context */ 715 #define VCPU_HYP_CONTEXT __vcpu_single_flag(iflags, BIT(7)) 716 717 /* SVE enabled for host EL0 */ 718 #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0)) 719 /* SME enabled for EL0 */ 720 #define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1)) 721 /* Physical CPU not in supported_cpus */ 722 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2)) 723 /* WFIT instruction trapped */ 724 #define IN_WFIT __vcpu_single_flag(sflags, BIT(3)) 725 /* vcpu system registers loaded on physical CPU */ 726 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(4)) 727 /* Software step state is Active-pending */ 728 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5)) 729 /* PMUSERENR for the guest EL0 is on physical CPU */ 730 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(6)) 731 /* WFI instruction trapped */ 732 #define IN_WFI __vcpu_single_flag(sflags, BIT(7)) 733 734 735 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 736 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ 737 sve_ffr_offset((vcpu)->arch.sve_max_vl)) 738 739 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) 740 741 #define vcpu_sve_state_size(vcpu) ({ \ 742 size_t __size_ret; \ 743 unsigned int __vcpu_vq; \ 744 \ 745 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ 746 __size_ret = 0; \ 747 } else { \ 748 __vcpu_vq = vcpu_sve_max_vq(vcpu); \ 749 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ 750 } \ 751 \ 752 __size_ret; \ 753 }) 754 755 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ 756 KVM_GUESTDBG_USE_SW_BP | \ 757 KVM_GUESTDBG_USE_HW | \ 758 KVM_GUESTDBG_SINGLESTEP) 759 760 #define vcpu_has_sve(vcpu) (system_supports_sve() && \ 761 vcpu_get_flag(vcpu, GUEST_HAS_SVE)) 762 763 #ifdef CONFIG_ARM64_PTR_AUTH 764 #define vcpu_has_ptrauth(vcpu) \ 765 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ 766 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ 767 vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH)) 768 #else 769 #define vcpu_has_ptrauth(vcpu) false 770 #endif 771 772 #define vcpu_on_unsupported_cpu(vcpu) \ 773 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU) 774 775 #define vcpu_set_on_unsupported_cpu(vcpu) \ 776 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU) 777 778 #define vcpu_clear_on_unsupported_cpu(vcpu) \ 779 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU) 780 781 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) 782 783 /* 784 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the 785 * memory backed version of a register, and not the one most recently 786 * accessed by a running VCPU. For example, for userspace access or 787 * for system registers that are never context switched, but only 788 * emulated. 789 */ 790 #define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)]) 791 792 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) 793 794 #define __vcpu_sys_reg(v,r) (ctxt_sys_reg(&(v)->arch.ctxt, (r))) 795 796 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 797 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 798 799 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 800 { 801 /* 802 * *** VHE ONLY *** 803 * 804 * System registers listed in the switch are not saved on every 805 * exit from the guest but are only saved on vcpu_put. 806 * 807 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 808 * should never be listed below, because the guest cannot modify its 809 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 810 * thread when emulating cross-VCPU communication. 811 */ 812 if (!has_vhe()) 813 return false; 814 815 switch (reg) { 816 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; 817 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; 818 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; 819 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; 820 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; 821 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; 822 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; 823 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; 824 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; 825 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; 826 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; 827 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 828 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; 829 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 830 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; 831 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; 832 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 833 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; 834 case PAR_EL1: *val = read_sysreg_par(); break; 835 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; 836 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; 837 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 838 default: return false; 839 } 840 841 return true; 842 } 843 844 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 845 { 846 /* 847 * *** VHE ONLY *** 848 * 849 * System registers listed in the switch are not restored on every 850 * entry to the guest but are only restored on vcpu_load. 851 * 852 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 853 * should never be listed below, because the MPIDR should only be set 854 * once, before running the VCPU, and never changed later. 855 */ 856 if (!has_vhe()) 857 return false; 858 859 switch (reg) { 860 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 861 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 862 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 863 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 864 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 865 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 866 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 867 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 868 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 869 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 870 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 871 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 872 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 873 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 874 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 875 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 876 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 877 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 878 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 879 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 880 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 881 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 882 default: return false; 883 } 884 885 return true; 886 } 887 888 struct kvm_vm_stat { 889 struct kvm_vm_stat_generic generic; 890 }; 891 892 struct kvm_vcpu_stat { 893 struct kvm_vcpu_stat_generic generic; 894 u64 hvc_exit_stat; 895 u64 wfe_exit_stat; 896 u64 wfi_exit_stat; 897 u64 mmio_exit_user; 898 u64 mmio_exit_kernel; 899 u64 signal_exits; 900 u64 exits; 901 }; 902 903 void kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 904 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 905 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 906 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 907 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 908 909 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); 910 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); 911 912 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 913 struct kvm_vcpu_events *events); 914 915 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 916 struct kvm_vcpu_events *events); 917 918 #define KVM_ARCH_WANT_MMU_NOTIFIER 919 920 void kvm_arm_halt_guest(struct kvm *kvm); 921 void kvm_arm_resume_guest(struct kvm *kvm); 922 923 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid) 924 925 #ifndef __KVM_NVHE_HYPERVISOR__ 926 #define kvm_call_hyp_nvhe(f, ...) \ 927 ({ \ 928 struct arm_smccc_res res; \ 929 \ 930 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ 931 ##__VA_ARGS__, &res); \ 932 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ 933 \ 934 res.a1; \ 935 }) 936 937 /* 938 * The couple of isb() below are there to guarantee the same behaviour 939 * on VHE as on !VHE, where the eret to EL1 acts as a context 940 * synchronization event. 941 */ 942 #define kvm_call_hyp(f, ...) \ 943 do { \ 944 if (has_vhe()) { \ 945 f(__VA_ARGS__); \ 946 isb(); \ 947 } else { \ 948 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 949 } \ 950 } while(0) 951 952 #define kvm_call_hyp_ret(f, ...) \ 953 ({ \ 954 typeof(f(__VA_ARGS__)) ret; \ 955 \ 956 if (has_vhe()) { \ 957 ret = f(__VA_ARGS__); \ 958 isb(); \ 959 } else { \ 960 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 961 } \ 962 \ 963 ret; \ 964 }) 965 #else /* __KVM_NVHE_HYPERVISOR__ */ 966 #define kvm_call_hyp(f, ...) f(__VA_ARGS__) 967 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__) 968 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__) 969 #endif /* __KVM_NVHE_HYPERVISOR__ */ 970 971 void force_vm_exit(const cpumask_t *mask); 972 973 int handle_exit(struct kvm_vcpu *vcpu, int exception_index); 974 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); 975 976 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); 977 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); 978 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); 979 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); 980 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); 981 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); 982 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 983 984 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); 985 986 int __init kvm_sys_reg_table_init(void); 987 988 bool lock_all_vcpus(struct kvm *kvm); 989 void unlock_all_vcpus(struct kvm *kvm); 990 991 /* MMIO helpers */ 992 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 993 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 994 995 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); 996 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); 997 998 /* 999 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 1000 * arrived in guest context. For arm64, any event that arrives while a vCPU is 1001 * loaded is considered to be "in guest". 1002 */ 1003 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 1004 { 1005 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu; 1006 } 1007 1008 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 1009 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 1010 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 1011 1012 bool kvm_arm_pvtime_supported(void); 1013 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 1014 struct kvm_device_attr *attr); 1015 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 1016 struct kvm_device_attr *attr); 1017 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 1018 struct kvm_device_attr *attr); 1019 1020 extern unsigned int __ro_after_init kvm_arm_vmid_bits; 1021 int __init kvm_arm_vmid_alloc_init(void); 1022 void __init kvm_arm_vmid_alloc_free(void); 1023 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid); 1024 void kvm_arm_vmid_clear_active(void); 1025 1026 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 1027 { 1028 vcpu_arch->steal.base = INVALID_GPA; 1029 } 1030 1031 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 1032 { 1033 return (vcpu_arch->steal.base != INVALID_GPA); 1034 } 1035 1036 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); 1037 1038 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 1039 1040 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); 1041 1042 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 1043 { 1044 /* The host's MPIDR is immutable, so let's set it up at boot time */ 1045 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); 1046 } 1047 1048 static inline bool kvm_system_needs_idmapped_vectors(void) 1049 { 1050 return cpus_have_const_cap(ARM64_SPECTRE_V3A); 1051 } 1052 1053 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu); 1054 1055 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 1056 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 1057 1058 void kvm_arm_init_debug(void); 1059 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu); 1060 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 1061 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 1062 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 1063 1064 #define kvm_vcpu_os_lock_enabled(vcpu) \ 1065 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK)) 1066 1067 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 1068 struct kvm_device_attr *attr); 1069 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 1070 struct kvm_device_attr *attr); 1071 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 1072 struct kvm_device_attr *attr); 1073 1074 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, 1075 struct kvm_arm_copy_mte_tags *copy_tags); 1076 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, 1077 struct kvm_arm_counter_offset *offset); 1078 1079 /* Guest/host FPSIMD coordination helpers */ 1080 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); 1081 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 1082 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); 1083 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 1084 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 1085 void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu); 1086 1087 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 1088 { 1089 return (!has_vhe() && attr->exclude_host); 1090 } 1091 1092 /* Flags for host debug state */ 1093 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu); 1094 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu); 1095 1096 #ifdef CONFIG_KVM 1097 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); 1098 void kvm_clr_pmu_events(u32 clr); 1099 bool kvm_set_pmuserenr(u64 val); 1100 #else 1101 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} 1102 static inline void kvm_clr_pmu_events(u32 clr) {} 1103 static inline bool kvm_set_pmuserenr(u64 val) 1104 { 1105 return false; 1106 } 1107 #endif 1108 1109 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu); 1110 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu); 1111 1112 int __init kvm_set_ipa_limit(void); 1113 1114 #define __KVM_HAVE_ARCH_VM_ALLOC 1115 struct kvm *kvm_arch_alloc_vm(void); 1116 1117 static inline bool kvm_vm_is_protected(struct kvm *kvm) 1118 { 1119 return false; 1120 } 1121 1122 void kvm_init_protected_traps(struct kvm_vcpu *vcpu); 1123 1124 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 1125 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 1126 1127 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED) 1128 1129 #define kvm_has_mte(kvm) \ 1130 (system_supports_mte() && \ 1131 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags)) 1132 1133 #define kvm_supports_32bit_el0() \ 1134 (system_supports_32bit_el0() && \ 1135 !static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1136 1137 #define kvm_vm_has_ran_once(kvm) \ 1138 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags)) 1139 1140 int kvm_trng_call(struct kvm_vcpu *vcpu); 1141 #ifdef CONFIG_KVM 1142 extern phys_addr_t hyp_mem_base; 1143 extern phys_addr_t hyp_mem_size; 1144 void __init kvm_hyp_reserve(void); 1145 #else 1146 static inline void kvm_hyp_reserve(void) { } 1147 #endif 1148 1149 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu); 1150 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu); 1151 1152 #endif /* __ARM64_KVM_HOST_H__ */ 1153