1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f8d6632SMarc Zyngier /* 34f8d6632SMarc Zyngier * Copyright (C) 2012,2013 - ARM Ltd 44f8d6632SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 54f8d6632SMarc Zyngier * 64f8d6632SMarc Zyngier * Derived from arch/arm/include/asm/kvm_host.h: 74f8d6632SMarc Zyngier * Copyright (C) 2012 - Virtual Open Systems and Columbia University 84f8d6632SMarc Zyngier * Author: Christoffer Dall <c.dall@virtualopensystems.com> 94f8d6632SMarc Zyngier */ 104f8d6632SMarc Zyngier 114f8d6632SMarc Zyngier #ifndef __ARM64_KVM_HOST_H__ 124f8d6632SMarc Zyngier #define __ARM64_KVM_HOST_H__ 134f8d6632SMarc Zyngier 143f61f409SDave Martin #include <linux/bitmap.h> 1565647300SPaolo Bonzini #include <linux/types.h> 163f61f409SDave Martin #include <linux/jump_label.h> 1765647300SPaolo Bonzini #include <linux/kvm_types.h> 183f61f409SDave Martin #include <linux/percpu.h> 1985738e05SJulien Thierry #include <asm/arch_gicv3.h> 203f61f409SDave Martin #include <asm/barrier.h> 2163a1e1c9SMark Rutland #include <asm/cpufeature.h> 221e0cf16cSMarc Zyngier #include <asm/cputype.h> 234f5abad9SJames Morse #include <asm/daifflags.h> 2417eed27bSDave Martin #include <asm/fpsimd.h> 254f8d6632SMarc Zyngier #include <asm/kvm.h> 263a3604bcSMarc Zyngier #include <asm/kvm_asm.h> 27e6b673b7SDave Martin #include <asm/thread_info.h> 284f8d6632SMarc Zyngier 29c1426e4cSEric Auger #define __KVM_HAVE_ARCH_INTC_INITIALIZED 30c1426e4cSEric Auger 31955a3fc6SLinu Cherian #define KVM_USER_MEM_SLOTS 512 32920552b2SDavid Hildenbrand #define KVM_HALT_POLL_NS_DEFAULT 500000 334f8d6632SMarc Zyngier 344f8d6632SMarc Zyngier #include <kvm/arm_vgic.h> 354f8d6632SMarc Zyngier #include <kvm/arm_arch_timer.h> 3604fe4726SShannon Zhao #include <kvm/arm_pmu.h> 374f8d6632SMarc Zyngier 38ef748917SMing Lei #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 39ef748917SMing Lei 40a22fa321SAmit Daniel Kachhap #define KVM_VCPU_MAX_FEATURES 7 414f8d6632SMarc Zyngier 427b244e2bSAndrew Jones #define KVM_REQ_SLEEP \ 432387149eSAndrew Jones KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 44325f9c64SAndrew Jones #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 45358b28f0SMarc Zyngier #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 468564d637SSteven Price #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 47d9c3872cSMarc Zyngier #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 48b13216cfSChristoffer Dall 49c862626eSKeqian Zhu #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ 50c862626eSKeqian Zhu KVM_DIRTY_LOG_INITIALLY_SET) 51c862626eSKeqian Zhu 5261bbe380SChristoffer Dall DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 5361bbe380SChristoffer Dall 549033bba4SDave Martin extern unsigned int kvm_sve_max_vl; 55a3be836dSDave Martin int kvm_arm_init_sve(void); 560f062bfeSDave Martin 576951e48bSWill Deacon int __attribute_const__ kvm_target_cpu(void); 584f8d6632SMarc Zyngier int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 5919bcc89eSSean Christopherson void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 60375bdd3bSDongjiu Geng int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext); 61c612505fSJames Morse void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start); 624f8d6632SMarc Zyngier 63e329fb75SChristoffer Dall struct kvm_vmid { 644f8d6632SMarc Zyngier /* The VMID generation used for the virt. memory system */ 654f8d6632SMarc Zyngier u64 vmid_gen; 664f8d6632SMarc Zyngier u32 vmid; 67e329fb75SChristoffer Dall }; 68e329fb75SChristoffer Dall 69e329fb75SChristoffer Dall struct kvm_arch { 70e329fb75SChristoffer Dall struct kvm_vmid vmid; 714f8d6632SMarc Zyngier 727665f3a8SSuzuki K Poulose /* stage2 entry level table */ 734f8d6632SMarc Zyngier pgd_t *pgd; 74e329fb75SChristoffer Dall phys_addr_t pgd_phys; 754f8d6632SMarc Zyngier 767665f3a8SSuzuki K Poulose /* VTCR_EL2 value for this VM */ 777665f3a8SSuzuki K Poulose u64 vtcr; 784f8d6632SMarc Zyngier 7994d0e598SMarc Zyngier /* The last vcpu id that ran on each physical CPU */ 8094d0e598SMarc Zyngier int __percpu *last_vcpu_ran; 8194d0e598SMarc Zyngier 823caa2d8cSAndre Przywara /* The maximum number of vCPUs depends on the used GIC model */ 833caa2d8cSAndre Przywara int max_vcpus; 843caa2d8cSAndre Przywara 854f8d6632SMarc Zyngier /* Interrupt controller */ 864f8d6632SMarc Zyngier struct vgic_dist vgic; 8785bd0ba1SMarc Zyngier 8885bd0ba1SMarc Zyngier /* Mandated version of PSCI */ 8985bd0ba1SMarc Zyngier u32 psci_version; 90c726200dSChristoffer Dall 91c726200dSChristoffer Dall /* 92c726200dSChristoffer Dall * If we encounter a data abort without valid instruction syndrome 93c726200dSChristoffer Dall * information, report this to user space. User space can (and 94c726200dSChristoffer Dall * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 95c726200dSChristoffer Dall * supported. 96c726200dSChristoffer Dall */ 97c726200dSChristoffer Dall bool return_nisv_io_abort_to_user; 984f8d6632SMarc Zyngier }; 994f8d6632SMarc Zyngier 1004f8d6632SMarc Zyngier #define KVM_NR_MEM_OBJS 40 1014f8d6632SMarc Zyngier 1024f8d6632SMarc Zyngier /* 1034f8d6632SMarc Zyngier * We don't want allocation failures within the mmu code, so we preallocate 1044f8d6632SMarc Zyngier * enough memory for a single page fault in a cache. 1054f8d6632SMarc Zyngier */ 1064f8d6632SMarc Zyngier struct kvm_mmu_memory_cache { 1074f8d6632SMarc Zyngier int nobjs; 1084f8d6632SMarc Zyngier void *objects[KVM_NR_MEM_OBJS]; 1094f8d6632SMarc Zyngier }; 1104f8d6632SMarc Zyngier 1114f8d6632SMarc Zyngier struct kvm_vcpu_fault_info { 1124f8d6632SMarc Zyngier u32 esr_el2; /* Hyp Syndrom Register */ 1134f8d6632SMarc Zyngier u64 far_el2; /* Hyp Fault Address Register */ 1144f8d6632SMarc Zyngier u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 1150067df41SJames Morse u64 disr_el1; /* Deferred [SError] Status Register */ 1164f8d6632SMarc Zyngier }; 1174f8d6632SMarc Zyngier 1189d8415d6SMarc Zyngier enum vcpu_sysreg { 1198f7f4fe7SMarc Zyngier __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ 1209d8415d6SMarc Zyngier MPIDR_EL1, /* MultiProcessor Affinity Register */ 1219d8415d6SMarc Zyngier CSSELR_EL1, /* Cache Size Selection Register */ 1229d8415d6SMarc Zyngier SCTLR_EL1, /* System Control Register */ 1239d8415d6SMarc Zyngier ACTLR_EL1, /* Auxiliary Control Register */ 1249d8415d6SMarc Zyngier CPACR_EL1, /* Coprocessor Access Control */ 12573433762SDave Martin ZCR_EL1, /* SVE Control */ 1269d8415d6SMarc Zyngier TTBR0_EL1, /* Translation Table Base Register 0 */ 1279d8415d6SMarc Zyngier TTBR1_EL1, /* Translation Table Base Register 1 */ 1289d8415d6SMarc Zyngier TCR_EL1, /* Translation Control Register */ 1299d8415d6SMarc Zyngier ESR_EL1, /* Exception Syndrome Register */ 130ef769e32SAdam Buchbinder AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ 131ef769e32SAdam Buchbinder AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ 1329d8415d6SMarc Zyngier FAR_EL1, /* Fault Address Register */ 1339d8415d6SMarc Zyngier MAIR_EL1, /* Memory Attribute Indirection Register */ 1349d8415d6SMarc Zyngier VBAR_EL1, /* Vector Base Address Register */ 1359d8415d6SMarc Zyngier CONTEXTIDR_EL1, /* Context ID Register */ 1369d8415d6SMarc Zyngier TPIDR_EL0, /* Thread ID, User R/W */ 1379d8415d6SMarc Zyngier TPIDRRO_EL0, /* Thread ID, User R/O */ 1389d8415d6SMarc Zyngier TPIDR_EL1, /* Thread ID, Privileged */ 1399d8415d6SMarc Zyngier AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ 1409d8415d6SMarc Zyngier CNTKCTL_EL1, /* Timer Control Register (EL1) */ 1419d8415d6SMarc Zyngier PAR_EL1, /* Physical Address Register */ 1429d8415d6SMarc Zyngier MDSCR_EL1, /* Monitor Debug System Control Register */ 1439d8415d6SMarc Zyngier MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 144c773ae2bSJames Morse DISR_EL1, /* Deferred Interrupt Status Register */ 1459d8415d6SMarc Zyngier 146ab946834SShannon Zhao /* Performance Monitors Registers */ 147ab946834SShannon Zhao PMCR_EL0, /* Control Register */ 1483965c3ceSShannon Zhao PMSELR_EL0, /* Event Counter Selection Register */ 149051ff581SShannon Zhao PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 150051ff581SShannon Zhao PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 151051ff581SShannon Zhao PMCCNTR_EL0, /* Cycle Counter Register */ 1529feb21acSShannon Zhao PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 1539feb21acSShannon Zhao PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 1549feb21acSShannon Zhao PMCCFILTR_EL0, /* Cycle Count Filter Register */ 15596b0eebcSShannon Zhao PMCNTENSET_EL0, /* Count Enable Set Register */ 1569db52c78SShannon Zhao PMINTENSET_EL1, /* Interrupt Enable Set Register */ 15776d883c4SShannon Zhao PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 1587a0adc70SShannon Zhao PMSWINC_EL0, /* Software Increment Register */ 159d692b8adSShannon Zhao PMUSERENR_EL0, /* User Enable Register */ 160ab946834SShannon Zhao 161384b40caSMark Rutland /* Pointer Authentication Registers in a strict increasing order. */ 162384b40caSMark Rutland APIAKEYLO_EL1, 163384b40caSMark Rutland APIAKEYHI_EL1, 164384b40caSMark Rutland APIBKEYLO_EL1, 165384b40caSMark Rutland APIBKEYHI_EL1, 166384b40caSMark Rutland APDAKEYLO_EL1, 167384b40caSMark Rutland APDAKEYHI_EL1, 168384b40caSMark Rutland APDBKEYLO_EL1, 169384b40caSMark Rutland APDBKEYHI_EL1, 170384b40caSMark Rutland APGAKEYLO_EL1, 171384b40caSMark Rutland APGAKEYHI_EL1, 172384b40caSMark Rutland 1739d8415d6SMarc Zyngier /* 32bit specific registers. Keep them at the end of the range */ 1749d8415d6SMarc Zyngier DACR32_EL2, /* Domain Access Control Register */ 1759d8415d6SMarc Zyngier IFSR32_EL2, /* Instruction Fault Status Register */ 1769d8415d6SMarc Zyngier FPEXC32_EL2, /* Floating-Point Exception Control Register */ 1779d8415d6SMarc Zyngier DBGVCR32_EL2, /* Debug Vector Catch Register */ 1789d8415d6SMarc Zyngier 1799d8415d6SMarc Zyngier NR_SYS_REGS /* Nothing after this line! */ 1809d8415d6SMarc Zyngier }; 1819d8415d6SMarc Zyngier 1829d8415d6SMarc Zyngier /* 32bit mapping */ 1839d8415d6SMarc Zyngier #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ 1849d8415d6SMarc Zyngier #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ 1859d8415d6SMarc Zyngier #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ 1869d8415d6SMarc Zyngier #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ 1879d8415d6SMarc Zyngier #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ 1889d8415d6SMarc Zyngier #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ 1899d8415d6SMarc Zyngier #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ 1909d8415d6SMarc Zyngier #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ 1919d8415d6SMarc Zyngier #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ 1929d8415d6SMarc Zyngier #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ 1939d8415d6SMarc Zyngier #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ 1949d8415d6SMarc Zyngier #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ 1959d8415d6SMarc Zyngier #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ 1969d8415d6SMarc Zyngier #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ 1979d8415d6SMarc Zyngier #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ 1989d8415d6SMarc Zyngier #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ 1999d8415d6SMarc Zyngier #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ 2009d8415d6SMarc Zyngier #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ 2019d8415d6SMarc Zyngier #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ 2029d8415d6SMarc Zyngier #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ 2039d8415d6SMarc Zyngier #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ 2049d8415d6SMarc Zyngier #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ 2059d8415d6SMarc Zyngier #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ 2069d8415d6SMarc Zyngier #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ 2079d8415d6SMarc Zyngier #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ 2089d8415d6SMarc Zyngier #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ 2099d8415d6SMarc Zyngier #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ 2109d8415d6SMarc Zyngier #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ 2119d8415d6SMarc Zyngier #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ 2129d8415d6SMarc Zyngier 2139d8415d6SMarc Zyngier #define cp14_DBGDSCRext (MDSCR_EL1 * 2) 2149d8415d6SMarc Zyngier #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) 2159d8415d6SMarc Zyngier #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) 2169d8415d6SMarc Zyngier #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) 2179d8415d6SMarc Zyngier #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) 2189d8415d6SMarc Zyngier #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) 2199d8415d6SMarc Zyngier #define cp14_DBGDCCINT (MDCCINT_EL1 * 2) 2209d8415d6SMarc Zyngier 2219d8415d6SMarc Zyngier #define NR_COPRO_REGS (NR_SYS_REGS * 2) 2229d8415d6SMarc Zyngier 2234f8d6632SMarc Zyngier struct kvm_cpu_context { 2244f8d6632SMarc Zyngier struct kvm_regs gp_regs; 22540033a61SMarc Zyngier union { 2264f8d6632SMarc Zyngier u64 sys_regs[NR_SYS_REGS]; 22772564016SMarc Zyngier u32 copro[NR_COPRO_REGS]; 22840033a61SMarc Zyngier }; 229c97e166eSJames Morse 230c97e166eSJames Morse struct kvm_vcpu *__hyp_running_vcpu; 2314f8d6632SMarc Zyngier }; 2324f8d6632SMarc Zyngier 233eb41238cSAndrew Murray struct kvm_pmu_events { 234eb41238cSAndrew Murray u32 events_host; 235eb41238cSAndrew Murray u32 events_guest; 236eb41238cSAndrew Murray }; 237eb41238cSAndrew Murray 238630a1685SAndrew Murray struct kvm_host_data { 239630a1685SAndrew Murray struct kvm_cpu_context host_ctxt; 240eb41238cSAndrew Murray struct kvm_pmu_events pmu_events; 241630a1685SAndrew Murray }; 242630a1685SAndrew Murray 243630a1685SAndrew Murray typedef struct kvm_host_data kvm_host_data_t; 2444f8d6632SMarc Zyngier 245358b28f0SMarc Zyngier struct vcpu_reset_state { 246358b28f0SMarc Zyngier unsigned long pc; 247358b28f0SMarc Zyngier unsigned long r0; 248358b28f0SMarc Zyngier bool be; 249358b28f0SMarc Zyngier bool reset; 250358b28f0SMarc Zyngier }; 251358b28f0SMarc Zyngier 2524f8d6632SMarc Zyngier struct kvm_vcpu_arch { 2534f8d6632SMarc Zyngier struct kvm_cpu_context ctxt; 254b43b5dd9SDave Martin void *sve_state; 255b43b5dd9SDave Martin unsigned int sve_max_vl; 2564f8d6632SMarc Zyngier 2574f8d6632SMarc Zyngier /* HYP configuration */ 2584f8d6632SMarc Zyngier u64 hcr_el2; 25956c7f5e7SAlex Bennée u32 mdcr_el2; 2604f8d6632SMarc Zyngier 2614f8d6632SMarc Zyngier /* Exception Information */ 2624f8d6632SMarc Zyngier struct kvm_vcpu_fault_info fault; 2634f8d6632SMarc Zyngier 26455e3748eSMarc Zyngier /* State of various workarounds, see kvm_asm.h for bit assignment */ 26555e3748eSMarc Zyngier u64 workaround_flags; 26655e3748eSMarc Zyngier 267fa89d31cSDave Martin /* Miscellaneous vcpu state flags */ 268fa89d31cSDave Martin u64 flags; 2690c557ed4SMarc Zyngier 27084e690bfSAlex Bennée /* 27184e690bfSAlex Bennée * We maintain more than a single set of debug registers to support 27284e690bfSAlex Bennée * debugging the guest from the host and to maintain separate host and 27384e690bfSAlex Bennée * guest state during world switches. vcpu_debug_state are the debug 27484e690bfSAlex Bennée * registers of the vcpu as the guest sees them. host_debug_state are 275834bf887SAlex Bennée * the host registers which are saved and restored during 276834bf887SAlex Bennée * world switches. external_debug_state contains the debug 277834bf887SAlex Bennée * values we want to debug the guest. This is set via the 278834bf887SAlex Bennée * KVM_SET_GUEST_DEBUG ioctl. 27984e690bfSAlex Bennée * 28084e690bfSAlex Bennée * debug_ptr points to the set of debug registers that should be loaded 28184e690bfSAlex Bennée * onto the hardware when running the guest. 28284e690bfSAlex Bennée */ 28384e690bfSAlex Bennée struct kvm_guest_debug_arch *debug_ptr; 28484e690bfSAlex Bennée struct kvm_guest_debug_arch vcpu_debug_state; 285834bf887SAlex Bennée struct kvm_guest_debug_arch external_debug_state; 28684e690bfSAlex Bennée 287e6b673b7SDave Martin struct thread_info *host_thread_info; /* hyp VA */ 288e6b673b7SDave Martin struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ 289e6b673b7SDave Martin 290f85279b4SWill Deacon struct { 291f85279b4SWill Deacon /* {Break,watch}point registers */ 292f85279b4SWill Deacon struct kvm_guest_debug_arch regs; 293f85279b4SWill Deacon /* Statistical profiling extension */ 294f85279b4SWill Deacon u64 pmscr_el1; 295f85279b4SWill Deacon } host_debug_state; 2964f8d6632SMarc Zyngier 2974f8d6632SMarc Zyngier /* VGIC state */ 2984f8d6632SMarc Zyngier struct vgic_cpu vgic_cpu; 2994f8d6632SMarc Zyngier struct arch_timer_cpu timer_cpu; 30004fe4726SShannon Zhao struct kvm_pmu pmu; 3014f8d6632SMarc Zyngier 3024f8d6632SMarc Zyngier /* 3034f8d6632SMarc Zyngier * Anything that is not used directly from assembly code goes 3044f8d6632SMarc Zyngier * here. 3054f8d6632SMarc Zyngier */ 3064f8d6632SMarc Zyngier 307337b99bfSAlex Bennée /* 308337b99bfSAlex Bennée * Guest registers we preserve during guest debugging. 309337b99bfSAlex Bennée * 310337b99bfSAlex Bennée * These shadow registers are updated by the kvm_handle_sys_reg 311337b99bfSAlex Bennée * trap handler if the guest accesses or updates them while we 312337b99bfSAlex Bennée * are using guest debug. 313337b99bfSAlex Bennée */ 314337b99bfSAlex Bennée struct { 315337b99bfSAlex Bennée u32 mdscr_el1; 316337b99bfSAlex Bennée } guest_debug_preserved; 317337b99bfSAlex Bennée 3183781528eSEric Auger /* vcpu power-off state */ 3193781528eSEric Auger bool power_off; 3204f8d6632SMarc Zyngier 3213b92830aSEric Auger /* Don't run the guest (internal implementation need) */ 3223b92830aSEric Auger bool pause; 3233b92830aSEric Auger 3244f8d6632SMarc Zyngier /* Cache some mmu pages needed inside spinlock regions */ 3254f8d6632SMarc Zyngier struct kvm_mmu_memory_cache mmu_page_cache; 3264f8d6632SMarc Zyngier 3274f8d6632SMarc Zyngier /* Target CPU and feature flags */ 3286c8c0c4dSChen Gang int target; 3294f8d6632SMarc Zyngier DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); 3304f8d6632SMarc Zyngier 3314f8d6632SMarc Zyngier /* Detect first run of a vcpu */ 3324f8d6632SMarc Zyngier bool has_run_once; 3334715c14bSJames Morse 3344715c14bSJames Morse /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 3354715c14bSJames Morse u64 vsesr_el2; 336d47533daSChristoffer Dall 337358b28f0SMarc Zyngier /* Additional reset state */ 338358b28f0SMarc Zyngier struct vcpu_reset_state reset_state; 339358b28f0SMarc Zyngier 340d47533daSChristoffer Dall /* True when deferrable sysregs are loaded on the physical CPU, 341d47533daSChristoffer Dall * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */ 342d47533daSChristoffer Dall bool sysregs_loaded_on_cpu; 3438564d637SSteven Price 3448564d637SSteven Price /* Guest PV state */ 3458564d637SSteven Price struct { 3468564d637SSteven Price u64 steal; 3478564d637SSteven Price u64 last_steal; 3488564d637SSteven Price gpa_t base; 3498564d637SSteven Price } steal; 3504f8d6632SMarc Zyngier }; 3514f8d6632SMarc Zyngier 352b43b5dd9SDave Martin /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 353b43b5dd9SDave Martin #define vcpu_sve_pffr(vcpu) ((void *)((char *)((vcpu)->arch.sve_state) + \ 354b43b5dd9SDave Martin sve_ffr_offset((vcpu)->arch.sve_max_vl))) 355b43b5dd9SDave Martin 356e1c9c983SDave Martin #define vcpu_sve_state_size(vcpu) ({ \ 357e1c9c983SDave Martin size_t __size_ret; \ 358e1c9c983SDave Martin unsigned int __vcpu_vq; \ 359e1c9c983SDave Martin \ 360e1c9c983SDave Martin if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ 361e1c9c983SDave Martin __size_ret = 0; \ 362e1c9c983SDave Martin } else { \ 363e1c9c983SDave Martin __vcpu_vq = sve_vq_from_vl((vcpu)->arch.sve_max_vl); \ 364e1c9c983SDave Martin __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ 365e1c9c983SDave Martin } \ 366e1c9c983SDave Martin \ 367e1c9c983SDave Martin __size_ret; \ 368e1c9c983SDave Martin }) 369e1c9c983SDave Martin 370fa89d31cSDave Martin /* vcpu_arch flags field values: */ 371fa89d31cSDave Martin #define KVM_ARM64_DEBUG_DIRTY (1 << 0) 372e6b673b7SDave Martin #define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */ 373e6b673b7SDave Martin #define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */ 374e6b673b7SDave Martin #define KVM_ARM64_HOST_SVE_IN_USE (1 << 3) /* backup for host TIF_SVE */ 375b3eb56b6SDave Martin #define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */ 3761765edbaSDave Martin #define KVM_ARM64_GUEST_HAS_SVE (1 << 5) /* SVE exposed to guest */ 3779033bba4SDave Martin #define KVM_ARM64_VCPU_SVE_FINALIZED (1 << 6) /* SVE config completed */ 378b890d75cSAmit Daniel Kachhap #define KVM_ARM64_GUEST_HAS_PTRAUTH (1 << 7) /* PTRAUTH exposed to guest */ 3791765edbaSDave Martin 3801765edbaSDave Martin #define vcpu_has_sve(vcpu) (system_supports_sve() && \ 3811765edbaSDave Martin ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_SVE)) 382fa89d31cSDave Martin 383b890d75cSAmit Daniel Kachhap #define vcpu_has_ptrauth(vcpu) ((system_supports_address_auth() || \ 384b890d75cSAmit Daniel Kachhap system_supports_generic_auth()) && \ 385b890d75cSAmit Daniel Kachhap ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_PTRAUTH)) 386b890d75cSAmit Daniel Kachhap 3874f8d6632SMarc Zyngier #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs) 3888d404c4cSChristoffer Dall 3898d404c4cSChristoffer Dall /* 3908d404c4cSChristoffer Dall * Only use __vcpu_sys_reg if you know you want the memory backed version of a 3918d404c4cSChristoffer Dall * register, and not the one most recently accessed by a running VCPU. For 3928d404c4cSChristoffer Dall * example, for userspace access or for system registers that are never context 3938d404c4cSChristoffer Dall * switched, but only emulated. 3948d404c4cSChristoffer Dall */ 3958d404c4cSChristoffer Dall #define __vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) 3968d404c4cSChristoffer Dall 397da6f1666SChristoffer Dall u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 398d47533daSChristoffer Dall void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 3998d404c4cSChristoffer Dall 40072564016SMarc Zyngier /* 40172564016SMarc Zyngier * CP14 and CP15 live in the same array, as they are backed by the 40272564016SMarc Zyngier * same system registers. 40372564016SMarc Zyngier */ 4043204be41SMarc Zyngier #define CPx_BIAS IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) 4053204be41SMarc Zyngier 4063204be41SMarc Zyngier #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r) ^ CPx_BIAS]) 4073204be41SMarc Zyngier #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r) ^ CPx_BIAS]) 4084f8d6632SMarc Zyngier 4094f8d6632SMarc Zyngier struct kvm_vm_stat { 4108a7e75d4SSuraj Jitindar Singh ulong remote_tlb_flush; 4114f8d6632SMarc Zyngier }; 4124f8d6632SMarc Zyngier 4134f8d6632SMarc Zyngier struct kvm_vcpu_stat { 4148a7e75d4SSuraj Jitindar Singh u64 halt_successful_poll; 4158a7e75d4SSuraj Jitindar Singh u64 halt_attempted_poll; 416cb953129SDavid Matlack u64 halt_poll_success_ns; 417cb953129SDavid Matlack u64 halt_poll_fail_ns; 4188a7e75d4SSuraj Jitindar Singh u64 halt_poll_invalid; 4198a7e75d4SSuraj Jitindar Singh u64 halt_wakeup; 4208a7e75d4SSuraj Jitindar Singh u64 hvc_exit_stat; 421b19e6892SAmit Tomar u64 wfe_exit_stat; 422b19e6892SAmit Tomar u64 wfi_exit_stat; 423b19e6892SAmit Tomar u64 mmio_exit_user; 424b19e6892SAmit Tomar u64 mmio_exit_kernel; 425b19e6892SAmit Tomar u64 exits; 4264f8d6632SMarc Zyngier }; 4274f8d6632SMarc Zyngier 428473bdc0eSAnup Patel int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 4294f8d6632SMarc Zyngier unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 4304f8d6632SMarc Zyngier int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 4314f8d6632SMarc Zyngier int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 4324f8d6632SMarc Zyngier int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 433539aee0eSJames Morse int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 434b7b27facSDongjiu Geng struct kvm_vcpu_events *events); 435b7b27facSDongjiu Geng 436539aee0eSJames Morse int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 437b7b27facSDongjiu Geng struct kvm_vcpu_events *events); 4384f8d6632SMarc Zyngier 4394f8d6632SMarc Zyngier #define KVM_ARCH_WANT_MMU_NOTIFIER 4404f8d6632SMarc Zyngier int kvm_unmap_hva_range(struct kvm *kvm, 4414f8d6632SMarc Zyngier unsigned long start, unsigned long end); 442748c0e31SLan Tianyu int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 44335307b9aSMarc Zyngier int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 44435307b9aSMarc Zyngier int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 4454f8d6632SMarc Zyngier 446b13216cfSChristoffer Dall void kvm_arm_halt_guest(struct kvm *kvm); 447b13216cfSChristoffer Dall void kvm_arm_resume_guest(struct kvm *kvm); 4484f8d6632SMarc Zyngier 449a0bf9776SArd Biesheuvel u64 __kvm_call_hyp(void *hypfn, ...); 45018fc7bf8SMarc Zyngier 451f50b6f6aSAndrew Scull #define kvm_call_hyp_nvhe(f, ...) \ 452f50b6f6aSAndrew Scull do { \ 453f50b6f6aSAndrew Scull DECLARE_KVM_NVHE_SYM(f); \ 454f50b6f6aSAndrew Scull __kvm_call_hyp(kvm_ksym_ref_nvhe(f), ##__VA_ARGS__); \ 455f50b6f6aSAndrew Scull } while(0) 456f50b6f6aSAndrew Scull 457f50b6f6aSAndrew Scull #define kvm_call_hyp_nvhe_ret(f, ...) \ 458f50b6f6aSAndrew Scull ({ \ 459f50b6f6aSAndrew Scull DECLARE_KVM_NVHE_SYM(f); \ 460f50b6f6aSAndrew Scull __kvm_call_hyp(kvm_ksym_ref_nvhe(f), ##__VA_ARGS__); \ 461f50b6f6aSAndrew Scull }) 462f50b6f6aSAndrew Scull 46318fc7bf8SMarc Zyngier /* 46418fc7bf8SMarc Zyngier * The couple of isb() below are there to guarantee the same behaviour 46518fc7bf8SMarc Zyngier * on VHE as on !VHE, where the eret to EL1 acts as a context 46618fc7bf8SMarc Zyngier * synchronization event. 46718fc7bf8SMarc Zyngier */ 46818fc7bf8SMarc Zyngier #define kvm_call_hyp(f, ...) \ 46918fc7bf8SMarc Zyngier do { \ 47018fc7bf8SMarc Zyngier if (has_vhe()) { \ 47118fc7bf8SMarc Zyngier f(__VA_ARGS__); \ 47218fc7bf8SMarc Zyngier isb(); \ 47318fc7bf8SMarc Zyngier } else { \ 474f50b6f6aSAndrew Scull kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ 47518fc7bf8SMarc Zyngier } \ 47618fc7bf8SMarc Zyngier } while(0) 47718fc7bf8SMarc Zyngier 47818fc7bf8SMarc Zyngier #define kvm_call_hyp_ret(f, ...) \ 47918fc7bf8SMarc Zyngier ({ \ 48018fc7bf8SMarc Zyngier typeof(f(__VA_ARGS__)) ret; \ 48118fc7bf8SMarc Zyngier \ 48218fc7bf8SMarc Zyngier if (has_vhe()) { \ 48318fc7bf8SMarc Zyngier ret = f(__VA_ARGS__); \ 48418fc7bf8SMarc Zyngier isb(); \ 48518fc7bf8SMarc Zyngier } else { \ 486f50b6f6aSAndrew Scull ret = kvm_call_hyp_nvhe_ret(f, ##__VA_ARGS__); \ 48718fc7bf8SMarc Zyngier } \ 48818fc7bf8SMarc Zyngier \ 48918fc7bf8SMarc Zyngier ret; \ 49018fc7bf8SMarc Zyngier }) 49122b39ca3SMarc Zyngier 492cf5d3188SChristoffer Dall void force_vm_exit(const cpumask_t *mask); 4938199ed0eSMario Smarduch void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); 4944f8d6632SMarc Zyngier 4954f8d6632SMarc Zyngier int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, 4964f8d6632SMarc Zyngier int exception_index); 4973368bd80SJames Morse void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run, 4983368bd80SJames Morse int exception_index); 4994f8d6632SMarc Zyngier 5000e20f5e2SMarc Zyngier /* MMIO helpers */ 5010e20f5e2SMarc Zyngier void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 5020e20f5e2SMarc Zyngier unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 5030e20f5e2SMarc Zyngier 5040e20f5e2SMarc Zyngier int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run); 5050e20f5e2SMarc Zyngier int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run, 5060e20f5e2SMarc Zyngier phys_addr_t fault_ipa); 5070e20f5e2SMarc Zyngier 5084f8d6632SMarc Zyngier int kvm_perf_init(void); 5094f8d6632SMarc Zyngier int kvm_perf_teardown(void); 5104f8d6632SMarc Zyngier 511b48c1a45SSteven Price long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 5128564d637SSteven Price gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 5138564d637SSteven Price void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 5148564d637SSteven Price 51558772e9aSSteven Price int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 51658772e9aSSteven Price struct kvm_device_attr *attr); 51758772e9aSSteven Price int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 51858772e9aSSteven Price struct kvm_device_attr *attr); 51958772e9aSSteven Price int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 52058772e9aSSteven Price struct kvm_device_attr *attr); 52158772e9aSSteven Price 5228564d637SSteven Price static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 5238564d637SSteven Price { 5248564d637SSteven Price vcpu_arch->steal.base = GPA_INVALID; 5258564d637SSteven Price } 5268564d637SSteven Price 5278564d637SSteven Price static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 5288564d637SSteven Price { 5298564d637SSteven Price return (vcpu_arch->steal.base != GPA_INVALID); 5308564d637SSteven Price } 531b48c1a45SSteven Price 532b7b27facSDongjiu Geng void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); 533b7b27facSDongjiu Geng 5344429fc64SAndre Przywara struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 5354429fc64SAndre Przywara 536630a1685SAndrew Murray DECLARE_PER_CPU(kvm_host_data_t, kvm_host_data); 5374464e210SChristoffer Dall 5381e0cf16cSMarc Zyngier static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 53932f13955SMarc Zyngier { 54032f13955SMarc Zyngier /* The host's MPIDR is immutable, so let's set it up at boot time */ 5411e0cf16cSMarc Zyngier cpu_ctxt->sys_regs[MPIDR_EL1] = read_cpuid_mpidr(); 54232f13955SMarc Zyngier } 54332f13955SMarc Zyngier 54433e5f4e5SMarc Zyngier static inline bool kvm_arch_requires_vhe(void) 54585acda3bSDave Martin { 54685acda3bSDave Martin /* 54785acda3bSDave Martin * The Arm architecture specifies that implementation of SVE 54885acda3bSDave Martin * requires VHE also to be implemented. The KVM code for arm64 54985acda3bSDave Martin * relies on this when SVE is present: 55085acda3bSDave Martin */ 55185acda3bSDave Martin if (system_supports_sve()) 55285acda3bSDave Martin return true; 55333e5f4e5SMarc Zyngier 55433e5f4e5SMarc Zyngier return false; 55585acda3bSDave Martin } 55685acda3bSDave Martin 557384b40caSMark Rutland void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu); 558384b40caSMark Rutland 5590865e636SRadim Krčmář static inline void kvm_arch_hardware_unsetup(void) {} 5600865e636SRadim Krčmář static inline void kvm_arch_sync_events(struct kvm *kvm) {} 5610865e636SRadim Krčmář static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 5623491caf2SChristian Borntraeger static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 5630865e636SRadim Krčmář 56456c7f5e7SAlex Bennée void kvm_arm_init_debug(void); 56556c7f5e7SAlex Bennée void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 56656c7f5e7SAlex Bennée void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 56784e690bfSAlex Bennée void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 568bb0c70bcSShannon Zhao int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 569bb0c70bcSShannon Zhao struct kvm_device_attr *attr); 570bb0c70bcSShannon Zhao int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 571bb0c70bcSShannon Zhao struct kvm_device_attr *attr); 572bb0c70bcSShannon Zhao int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 573bb0c70bcSShannon Zhao struct kvm_device_attr *attr); 57456c7f5e7SAlex Bennée 575e6b673b7SDave Martin /* Guest/host FPSIMD coordination helpers */ 576e6b673b7SDave Martin int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); 577e6b673b7SDave Martin void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 578e6b673b7SDave Martin void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 579e6b673b7SDave Martin void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 580e6b673b7SDave Martin 581eb41238cSAndrew Murray static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 582eb41238cSAndrew Murray { 583435e53fbSAndrew Murray return (!has_vhe() && attr->exclude_host); 584eb41238cSAndrew Murray } 585eb41238cSAndrew Murray 586e6b673b7SDave Martin #ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */ 587e6b673b7SDave Martin static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) 58817eed27bSDave Martin { 589e6b673b7SDave Martin return kvm_arch_vcpu_run_map_fp(vcpu); 59017eed27bSDave Martin } 591eb41238cSAndrew Murray 592eb41238cSAndrew Murray void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); 593eb41238cSAndrew Murray void kvm_clr_pmu_events(u32 clr); 5943d91befbSAndrew Murray 595435e53fbSAndrew Murray void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu); 596435e53fbSAndrew Murray void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); 597eb41238cSAndrew Murray #else 598eb41238cSAndrew Murray static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} 599eb41238cSAndrew Murray static inline void kvm_clr_pmu_events(u32 clr) {} 600e6b673b7SDave Martin #endif 60117eed27bSDave Martin 602c118bbb5SAndre Przywara #define KVM_BP_HARDEN_UNKNOWN -1 603c118bbb5SAndre Przywara #define KVM_BP_HARDEN_WA_NEEDED 0 604c118bbb5SAndre Przywara #define KVM_BP_HARDEN_NOT_REQUIRED 1 605c118bbb5SAndre Przywara 606c118bbb5SAndre Przywara static inline int kvm_arm_harden_branch_predictor(void) 6076167ec5cSMarc Zyngier { 608c118bbb5SAndre Przywara switch (get_spectre_v2_workaround_state()) { 609c118bbb5SAndre Przywara case ARM64_BP_HARDEN_WA_NEEDED: 610c118bbb5SAndre Przywara return KVM_BP_HARDEN_WA_NEEDED; 611c118bbb5SAndre Przywara case ARM64_BP_HARDEN_NOT_REQUIRED: 612c118bbb5SAndre Przywara return KVM_BP_HARDEN_NOT_REQUIRED; 613c118bbb5SAndre Przywara case ARM64_BP_HARDEN_UNKNOWN: 614c118bbb5SAndre Przywara default: 615c118bbb5SAndre Przywara return KVM_BP_HARDEN_UNKNOWN; 616c118bbb5SAndre Przywara } 6176167ec5cSMarc Zyngier } 6186167ec5cSMarc Zyngier 6195d81f7dcSMarc Zyngier #define KVM_SSBD_UNKNOWN -1 6205d81f7dcSMarc Zyngier #define KVM_SSBD_FORCE_DISABLE 0 6215d81f7dcSMarc Zyngier #define KVM_SSBD_KERNEL 1 6225d81f7dcSMarc Zyngier #define KVM_SSBD_FORCE_ENABLE 2 6235d81f7dcSMarc Zyngier #define KVM_SSBD_MITIGATED 3 6245d81f7dcSMarc Zyngier 6255d81f7dcSMarc Zyngier static inline int kvm_arm_have_ssbd(void) 6265d81f7dcSMarc Zyngier { 6275d81f7dcSMarc Zyngier switch (arm64_get_ssbd_state()) { 6285d81f7dcSMarc Zyngier case ARM64_SSBD_FORCE_DISABLE: 6295d81f7dcSMarc Zyngier return KVM_SSBD_FORCE_DISABLE; 6305d81f7dcSMarc Zyngier case ARM64_SSBD_KERNEL: 6315d81f7dcSMarc Zyngier return KVM_SSBD_KERNEL; 6325d81f7dcSMarc Zyngier case ARM64_SSBD_FORCE_ENABLE: 6335d81f7dcSMarc Zyngier return KVM_SSBD_FORCE_ENABLE; 6345d81f7dcSMarc Zyngier case ARM64_SSBD_MITIGATED: 6355d81f7dcSMarc Zyngier return KVM_SSBD_MITIGATED; 6365d81f7dcSMarc Zyngier case ARM64_SSBD_UNKNOWN: 6375d81f7dcSMarc Zyngier default: 6385d81f7dcSMarc Zyngier return KVM_SSBD_UNKNOWN; 6395d81f7dcSMarc Zyngier } 6405d81f7dcSMarc Zyngier } 6415d81f7dcSMarc Zyngier 642bc192ceeSChristoffer Dall void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu); 643bc192ceeSChristoffer Dall void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu); 644bc192ceeSChristoffer Dall 645b130a8f7SMarc Zyngier int kvm_set_ipa_limit(void); 6460f62f0e9SSuzuki K Poulose 647d1e5b0e9SMarc Orr #define __KVM_HAVE_ARCH_VM_ALLOC 648d1e5b0e9SMarc Orr struct kvm *kvm_arch_alloc_vm(void); 649d1e5b0e9SMarc Orr void kvm_arch_free_vm(struct kvm *kvm); 650d1e5b0e9SMarc Orr 651bca607ebSMarc Zyngier int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type); 6525b6c6742SSuzuki K Poulose 65392e68b2bSDave Martin int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 6549033bba4SDave Martin bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 6559033bba4SDave Martin 6569033bba4SDave Martin #define kvm_arm_vcpu_sve_finalized(vcpu) \ 6579033bba4SDave Martin ((vcpu)->arch.flags & KVM_ARM64_VCPU_SVE_FINALIZED) 6587dd32a0dSDave Martin 6594f8d6632SMarc Zyngier #endif /* __ARM64_KVM_HOST_H__ */ 660