14f8d6632SMarc Zyngier /* 24f8d6632SMarc Zyngier * Copyright (C) 2012,2013 - ARM Ltd 34f8d6632SMarc Zyngier * Author: Marc Zyngier <marc.zyngier@arm.com> 44f8d6632SMarc Zyngier * 54f8d6632SMarc Zyngier * Derived from arch/arm/include/asm/kvm_host.h: 64f8d6632SMarc Zyngier * Copyright (C) 2012 - Virtual Open Systems and Columbia University 74f8d6632SMarc Zyngier * Author: Christoffer Dall <c.dall@virtualopensystems.com> 84f8d6632SMarc Zyngier * 94f8d6632SMarc Zyngier * This program is free software; you can redistribute it and/or modify 104f8d6632SMarc Zyngier * it under the terms of the GNU General Public License version 2 as 114f8d6632SMarc Zyngier * published by the Free Software Foundation. 124f8d6632SMarc Zyngier * 134f8d6632SMarc Zyngier * This program is distributed in the hope that it will be useful, 144f8d6632SMarc Zyngier * but WITHOUT ANY WARRANTY; without even the implied warranty of 154f8d6632SMarc Zyngier * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 164f8d6632SMarc Zyngier * GNU General Public License for more details. 174f8d6632SMarc Zyngier * 184f8d6632SMarc Zyngier * You should have received a copy of the GNU General Public License 194f8d6632SMarc Zyngier * along with this program. If not, see <http://www.gnu.org/licenses/>. 204f8d6632SMarc Zyngier */ 214f8d6632SMarc Zyngier 224f8d6632SMarc Zyngier #ifndef __ARM64_KVM_HOST_H__ 234f8d6632SMarc Zyngier #define __ARM64_KVM_HOST_H__ 244f8d6632SMarc Zyngier 2565647300SPaolo Bonzini #include <linux/types.h> 2665647300SPaolo Bonzini #include <linux/kvm_types.h> 274f8d6632SMarc Zyngier #include <asm/kvm.h> 283a3604bcSMarc Zyngier #include <asm/kvm_asm.h> 294f8d6632SMarc Zyngier #include <asm/kvm_mmio.h> 30ad882137SMarc Zyngier #include <asm/kvm_perf_event.h> 314f8d6632SMarc Zyngier 32c1426e4cSEric Auger #define __KVM_HAVE_ARCH_INTC_INITIALIZED 33c1426e4cSEric Auger 344f8d6632SMarc Zyngier #define KVM_USER_MEM_SLOTS 32 354f8d6632SMarc Zyngier #define KVM_PRIVATE_MEM_SLOTS 4 364f8d6632SMarc Zyngier #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 37920552b2SDavid Hildenbrand #define KVM_HALT_POLL_NS_DEFAULT 500000 384f8d6632SMarc Zyngier 394f8d6632SMarc Zyngier #include <kvm/arm_vgic.h> 404f8d6632SMarc Zyngier #include <kvm/arm_arch_timer.h> 4104fe4726SShannon Zhao #include <kvm/arm_pmu.h> 424f8d6632SMarc Zyngier 43ef748917SMing Lei #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 44ef748917SMing Lei 457d0f84aaSAnup Patel #define KVM_VCPU_MAX_FEATURES 3 464f8d6632SMarc Zyngier 476951e48bSWill Deacon int __attribute_const__ kvm_target_cpu(void); 484f8d6632SMarc Zyngier int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 494f8d6632SMarc Zyngier int kvm_arch_dev_ioctl_check_extension(long ext); 504f8d6632SMarc Zyngier 514f8d6632SMarc Zyngier struct kvm_arch { 524f8d6632SMarc Zyngier /* The VMID generation used for the virt. memory system */ 534f8d6632SMarc Zyngier u64 vmid_gen; 544f8d6632SMarc Zyngier u32 vmid; 554f8d6632SMarc Zyngier 564f8d6632SMarc Zyngier /* 1-level 2nd stage table and lock */ 574f8d6632SMarc Zyngier spinlock_t pgd_lock; 584f8d6632SMarc Zyngier pgd_t *pgd; 594f8d6632SMarc Zyngier 604f8d6632SMarc Zyngier /* VTTBR value associated with above pgd and vmid */ 614f8d6632SMarc Zyngier u64 vttbr; 624f8d6632SMarc Zyngier 633caa2d8cSAndre Przywara /* The maximum number of vCPUs depends on the used GIC model */ 643caa2d8cSAndre Przywara int max_vcpus; 653caa2d8cSAndre Przywara 664f8d6632SMarc Zyngier /* Interrupt controller */ 674f8d6632SMarc Zyngier struct vgic_dist vgic; 684f8d6632SMarc Zyngier 694f8d6632SMarc Zyngier /* Timer */ 704f8d6632SMarc Zyngier struct arch_timer_kvm timer; 714f8d6632SMarc Zyngier }; 724f8d6632SMarc Zyngier 734f8d6632SMarc Zyngier #define KVM_NR_MEM_OBJS 40 744f8d6632SMarc Zyngier 754f8d6632SMarc Zyngier /* 764f8d6632SMarc Zyngier * We don't want allocation failures within the mmu code, so we preallocate 774f8d6632SMarc Zyngier * enough memory for a single page fault in a cache. 784f8d6632SMarc Zyngier */ 794f8d6632SMarc Zyngier struct kvm_mmu_memory_cache { 804f8d6632SMarc Zyngier int nobjs; 814f8d6632SMarc Zyngier void *objects[KVM_NR_MEM_OBJS]; 824f8d6632SMarc Zyngier }; 834f8d6632SMarc Zyngier 844f8d6632SMarc Zyngier struct kvm_vcpu_fault_info { 854f8d6632SMarc Zyngier u32 esr_el2; /* Hyp Syndrom Register */ 864f8d6632SMarc Zyngier u64 far_el2; /* Hyp Fault Address Register */ 874f8d6632SMarc Zyngier u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 884f8d6632SMarc Zyngier }; 894f8d6632SMarc Zyngier 909d8415d6SMarc Zyngier /* 919d8415d6SMarc Zyngier * 0 is reserved as an invalid value. 929d8415d6SMarc Zyngier * Order should be kept in sync with the save/restore code. 939d8415d6SMarc Zyngier */ 949d8415d6SMarc Zyngier enum vcpu_sysreg { 959d8415d6SMarc Zyngier __INVALID_SYSREG__, 969d8415d6SMarc Zyngier MPIDR_EL1, /* MultiProcessor Affinity Register */ 979d8415d6SMarc Zyngier CSSELR_EL1, /* Cache Size Selection Register */ 989d8415d6SMarc Zyngier SCTLR_EL1, /* System Control Register */ 999d8415d6SMarc Zyngier ACTLR_EL1, /* Auxiliary Control Register */ 1009d8415d6SMarc Zyngier CPACR_EL1, /* Coprocessor Access Control */ 1019d8415d6SMarc Zyngier TTBR0_EL1, /* Translation Table Base Register 0 */ 1029d8415d6SMarc Zyngier TTBR1_EL1, /* Translation Table Base Register 1 */ 1039d8415d6SMarc Zyngier TCR_EL1, /* Translation Control Register */ 1049d8415d6SMarc Zyngier ESR_EL1, /* Exception Syndrome Register */ 1059d8415d6SMarc Zyngier AFSR0_EL1, /* Auxilary Fault Status Register 0 */ 1069d8415d6SMarc Zyngier AFSR1_EL1, /* Auxilary Fault Status Register 1 */ 1079d8415d6SMarc Zyngier FAR_EL1, /* Fault Address Register */ 1089d8415d6SMarc Zyngier MAIR_EL1, /* Memory Attribute Indirection Register */ 1099d8415d6SMarc Zyngier VBAR_EL1, /* Vector Base Address Register */ 1109d8415d6SMarc Zyngier CONTEXTIDR_EL1, /* Context ID Register */ 1119d8415d6SMarc Zyngier TPIDR_EL0, /* Thread ID, User R/W */ 1129d8415d6SMarc Zyngier TPIDRRO_EL0, /* Thread ID, User R/O */ 1139d8415d6SMarc Zyngier TPIDR_EL1, /* Thread ID, Privileged */ 1149d8415d6SMarc Zyngier AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ 1159d8415d6SMarc Zyngier CNTKCTL_EL1, /* Timer Control Register (EL1) */ 1169d8415d6SMarc Zyngier PAR_EL1, /* Physical Address Register */ 1179d8415d6SMarc Zyngier MDSCR_EL1, /* Monitor Debug System Control Register */ 1189d8415d6SMarc Zyngier MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 1199d8415d6SMarc Zyngier 120ab946834SShannon Zhao /* Performance Monitors Registers */ 121ab946834SShannon Zhao PMCR_EL0, /* Control Register */ 1223965c3ceSShannon Zhao PMSELR_EL0, /* Event Counter Selection Register */ 123ab946834SShannon Zhao 1249d8415d6SMarc Zyngier /* 32bit specific registers. Keep them at the end of the range */ 1259d8415d6SMarc Zyngier DACR32_EL2, /* Domain Access Control Register */ 1269d8415d6SMarc Zyngier IFSR32_EL2, /* Instruction Fault Status Register */ 1279d8415d6SMarc Zyngier FPEXC32_EL2, /* Floating-Point Exception Control Register */ 1289d8415d6SMarc Zyngier DBGVCR32_EL2, /* Debug Vector Catch Register */ 1299d8415d6SMarc Zyngier 1309d8415d6SMarc Zyngier NR_SYS_REGS /* Nothing after this line! */ 1319d8415d6SMarc Zyngier }; 1329d8415d6SMarc Zyngier 1339d8415d6SMarc Zyngier /* 32bit mapping */ 1349d8415d6SMarc Zyngier #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ 1359d8415d6SMarc Zyngier #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ 1369d8415d6SMarc Zyngier #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ 1379d8415d6SMarc Zyngier #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ 1389d8415d6SMarc Zyngier #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ 1399d8415d6SMarc Zyngier #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ 1409d8415d6SMarc Zyngier #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ 1419d8415d6SMarc Zyngier #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ 1429d8415d6SMarc Zyngier #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ 1439d8415d6SMarc Zyngier #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ 1449d8415d6SMarc Zyngier #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ 1459d8415d6SMarc Zyngier #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ 1469d8415d6SMarc Zyngier #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ 1479d8415d6SMarc Zyngier #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ 1489d8415d6SMarc Zyngier #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ 1499d8415d6SMarc Zyngier #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ 1509d8415d6SMarc Zyngier #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ 1519d8415d6SMarc Zyngier #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ 1529d8415d6SMarc Zyngier #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ 1539d8415d6SMarc Zyngier #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ 1549d8415d6SMarc Zyngier #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ 1559d8415d6SMarc Zyngier #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ 1569d8415d6SMarc Zyngier #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ 1579d8415d6SMarc Zyngier #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ 1589d8415d6SMarc Zyngier #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ 1599d8415d6SMarc Zyngier #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ 1609d8415d6SMarc Zyngier #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ 1619d8415d6SMarc Zyngier #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ 1629d8415d6SMarc Zyngier #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ 1639d8415d6SMarc Zyngier 1649d8415d6SMarc Zyngier #define cp14_DBGDSCRext (MDSCR_EL1 * 2) 1659d8415d6SMarc Zyngier #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) 1669d8415d6SMarc Zyngier #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) 1679d8415d6SMarc Zyngier #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) 1689d8415d6SMarc Zyngier #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) 1699d8415d6SMarc Zyngier #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) 1709d8415d6SMarc Zyngier #define cp14_DBGDCCINT (MDCCINT_EL1 * 2) 1719d8415d6SMarc Zyngier 1729d8415d6SMarc Zyngier #define NR_COPRO_REGS (NR_SYS_REGS * 2) 1739d8415d6SMarc Zyngier 1744f8d6632SMarc Zyngier struct kvm_cpu_context { 1754f8d6632SMarc Zyngier struct kvm_regs gp_regs; 17640033a61SMarc Zyngier union { 1774f8d6632SMarc Zyngier u64 sys_regs[NR_SYS_REGS]; 17872564016SMarc Zyngier u32 copro[NR_COPRO_REGS]; 17940033a61SMarc Zyngier }; 1804f8d6632SMarc Zyngier }; 1814f8d6632SMarc Zyngier 1824f8d6632SMarc Zyngier typedef struct kvm_cpu_context kvm_cpu_context_t; 1834f8d6632SMarc Zyngier 1844f8d6632SMarc Zyngier struct kvm_vcpu_arch { 1854f8d6632SMarc Zyngier struct kvm_cpu_context ctxt; 1864f8d6632SMarc Zyngier 1874f8d6632SMarc Zyngier /* HYP configuration */ 1884f8d6632SMarc Zyngier u64 hcr_el2; 18956c7f5e7SAlex Bennée u32 mdcr_el2; 1904f8d6632SMarc Zyngier 1914f8d6632SMarc Zyngier /* Exception Information */ 1924f8d6632SMarc Zyngier struct kvm_vcpu_fault_info fault; 1934f8d6632SMarc Zyngier 19484e690bfSAlex Bennée /* Guest debug state */ 1950c557ed4SMarc Zyngier u64 debug_flags; 1960c557ed4SMarc Zyngier 19784e690bfSAlex Bennée /* 19884e690bfSAlex Bennée * We maintain more than a single set of debug registers to support 19984e690bfSAlex Bennée * debugging the guest from the host and to maintain separate host and 20084e690bfSAlex Bennée * guest state during world switches. vcpu_debug_state are the debug 20184e690bfSAlex Bennée * registers of the vcpu as the guest sees them. host_debug_state are 202834bf887SAlex Bennée * the host registers which are saved and restored during 203834bf887SAlex Bennée * world switches. external_debug_state contains the debug 204834bf887SAlex Bennée * values we want to debug the guest. This is set via the 205834bf887SAlex Bennée * KVM_SET_GUEST_DEBUG ioctl. 20684e690bfSAlex Bennée * 20784e690bfSAlex Bennée * debug_ptr points to the set of debug registers that should be loaded 20884e690bfSAlex Bennée * onto the hardware when running the guest. 20984e690bfSAlex Bennée */ 21084e690bfSAlex Bennée struct kvm_guest_debug_arch *debug_ptr; 21184e690bfSAlex Bennée struct kvm_guest_debug_arch vcpu_debug_state; 212834bf887SAlex Bennée struct kvm_guest_debug_arch external_debug_state; 21384e690bfSAlex Bennée 2144f8d6632SMarc Zyngier /* Pointer to host CPU context */ 2154f8d6632SMarc Zyngier kvm_cpu_context_t *host_cpu_context; 21684e690bfSAlex Bennée struct kvm_guest_debug_arch host_debug_state; 2174f8d6632SMarc Zyngier 2184f8d6632SMarc Zyngier /* VGIC state */ 2194f8d6632SMarc Zyngier struct vgic_cpu vgic_cpu; 2204f8d6632SMarc Zyngier struct arch_timer_cpu timer_cpu; 22104fe4726SShannon Zhao struct kvm_pmu pmu; 2224f8d6632SMarc Zyngier 2234f8d6632SMarc Zyngier /* 2244f8d6632SMarc Zyngier * Anything that is not used directly from assembly code goes 2254f8d6632SMarc Zyngier * here. 2264f8d6632SMarc Zyngier */ 2274f8d6632SMarc Zyngier 228337b99bfSAlex Bennée /* 229337b99bfSAlex Bennée * Guest registers we preserve during guest debugging. 230337b99bfSAlex Bennée * 231337b99bfSAlex Bennée * These shadow registers are updated by the kvm_handle_sys_reg 232337b99bfSAlex Bennée * trap handler if the guest accesses or updates them while we 233337b99bfSAlex Bennée * are using guest debug. 234337b99bfSAlex Bennée */ 235337b99bfSAlex Bennée struct { 236337b99bfSAlex Bennée u32 mdscr_el1; 237337b99bfSAlex Bennée } guest_debug_preserved; 238337b99bfSAlex Bennée 2393781528eSEric Auger /* vcpu power-off state */ 2403781528eSEric Auger bool power_off; 2414f8d6632SMarc Zyngier 2423b92830aSEric Auger /* Don't run the guest (internal implementation need) */ 2433b92830aSEric Auger bool pause; 2443b92830aSEric Auger 2454f8d6632SMarc Zyngier /* IO related fields */ 2464f8d6632SMarc Zyngier struct kvm_decode mmio_decode; 2474f8d6632SMarc Zyngier 2484f8d6632SMarc Zyngier /* Interrupt related fields */ 2494f8d6632SMarc Zyngier u64 irq_lines; /* IRQ and FIQ levels */ 2504f8d6632SMarc Zyngier 2514f8d6632SMarc Zyngier /* Cache some mmu pages needed inside spinlock regions */ 2524f8d6632SMarc Zyngier struct kvm_mmu_memory_cache mmu_page_cache; 2534f8d6632SMarc Zyngier 2544f8d6632SMarc Zyngier /* Target CPU and feature flags */ 2556c8c0c4dSChen Gang int target; 2564f8d6632SMarc Zyngier DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); 2574f8d6632SMarc Zyngier 2584f8d6632SMarc Zyngier /* Detect first run of a vcpu */ 2594f8d6632SMarc Zyngier bool has_run_once; 2604f8d6632SMarc Zyngier }; 2614f8d6632SMarc Zyngier 2624f8d6632SMarc Zyngier #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs) 2634f8d6632SMarc Zyngier #define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) 26472564016SMarc Zyngier /* 26572564016SMarc Zyngier * CP14 and CP15 live in the same array, as they are backed by the 26672564016SMarc Zyngier * same system registers. 26772564016SMarc Zyngier */ 26872564016SMarc Zyngier #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)]) 26972564016SMarc Zyngier #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)]) 2704f8d6632SMarc Zyngier 271f0a3eaffSVictor Kamensky #ifdef CONFIG_CPU_BIG_ENDIAN 272dedf97e8SMarc Zyngier #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r)) 273dedf97e8SMarc Zyngier #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r) + 1) 274f0a3eaffSVictor Kamensky #else 275dedf97e8SMarc Zyngier #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r) + 1) 276dedf97e8SMarc Zyngier #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r)) 277f0a3eaffSVictor Kamensky #endif 278f0a3eaffSVictor Kamensky 2794f8d6632SMarc Zyngier struct kvm_vm_stat { 2804f8d6632SMarc Zyngier u32 remote_tlb_flush; 2814f8d6632SMarc Zyngier }; 2824f8d6632SMarc Zyngier 2834f8d6632SMarc Zyngier struct kvm_vcpu_stat { 284f7819512SPaolo Bonzini u32 halt_successful_poll; 28562bea5bfSPaolo Bonzini u32 halt_attempted_poll; 2864f8d6632SMarc Zyngier u32 halt_wakeup; 287b19e6892SAmit Tomar u32 hvc_exit_stat; 288b19e6892SAmit Tomar u64 wfe_exit_stat; 289b19e6892SAmit Tomar u64 wfi_exit_stat; 290b19e6892SAmit Tomar u64 mmio_exit_user; 291b19e6892SAmit Tomar u64 mmio_exit_kernel; 292b19e6892SAmit Tomar u64 exits; 2934f8d6632SMarc Zyngier }; 2944f8d6632SMarc Zyngier 295473bdc0eSAnup Patel int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 2964f8d6632SMarc Zyngier unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 2974f8d6632SMarc Zyngier int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 2984f8d6632SMarc Zyngier int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 2994f8d6632SMarc Zyngier int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 3004f8d6632SMarc Zyngier 3014f8d6632SMarc Zyngier #define KVM_ARCH_WANT_MMU_NOTIFIER 3024f8d6632SMarc Zyngier int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); 3034f8d6632SMarc Zyngier int kvm_unmap_hva_range(struct kvm *kvm, 3044f8d6632SMarc Zyngier unsigned long start, unsigned long end); 3054f8d6632SMarc Zyngier void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 30635307b9aSMarc Zyngier int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 30735307b9aSMarc Zyngier int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 3084f8d6632SMarc Zyngier 3094f8d6632SMarc Zyngier /* We do not have shadow page tables, hence the empty hooks */ 310fe71557aSTang Chen static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm, 311fe71557aSTang Chen unsigned long address) 312fe71557aSTang Chen { 313fe71557aSTang Chen } 314fe71557aSTang Chen 3154f8d6632SMarc Zyngier struct kvm_vcpu *kvm_arm_get_running_vcpu(void); 3164000be42SWill Deacon struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void); 3174f8d6632SMarc Zyngier 3184f8d6632SMarc Zyngier u64 kvm_call_hyp(void *hypfn, ...); 319cf5d3188SChristoffer Dall void force_vm_exit(const cpumask_t *mask); 3208199ed0eSMario Smarduch void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); 3214f8d6632SMarc Zyngier 3224f8d6632SMarc Zyngier int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, 3234f8d6632SMarc Zyngier int exception_index); 3244f8d6632SMarc Zyngier 3254f8d6632SMarc Zyngier int kvm_perf_init(void); 3264f8d6632SMarc Zyngier int kvm_perf_teardown(void); 3274f8d6632SMarc Zyngier 3284429fc64SAndre Przywara struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 3294429fc64SAndre Przywara 330092bd143SMarc Zyngier static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr, 331092bd143SMarc Zyngier phys_addr_t pgd_ptr, 332092bd143SMarc Zyngier unsigned long hyp_stack_ptr, 333092bd143SMarc Zyngier unsigned long vector_ptr) 334092bd143SMarc Zyngier { 335092bd143SMarc Zyngier /* 336092bd143SMarc Zyngier * Call initialization code, and switch to the full blown 337092bd143SMarc Zyngier * HYP code. 338092bd143SMarc Zyngier */ 339092bd143SMarc Zyngier kvm_call_hyp((void *)boot_pgd_ptr, pgd_ptr, 340092bd143SMarc Zyngier hyp_stack_ptr, vector_ptr); 341092bd143SMarc Zyngier } 342092bd143SMarc Zyngier 34313a34e06SRadim Krčmář static inline void kvm_arch_hardware_disable(void) {} 3440865e636SRadim Krčmář static inline void kvm_arch_hardware_unsetup(void) {} 3450865e636SRadim Krčmář static inline void kvm_arch_sync_events(struct kvm *kvm) {} 3460865e636SRadim Krčmář static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} 3470865e636SRadim Krčmář static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 3480865e636SRadim Krčmář 34956c7f5e7SAlex Bennée void kvm_arm_init_debug(void); 35056c7f5e7SAlex Bennée void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 35156c7f5e7SAlex Bennée void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 35284e690bfSAlex Bennée void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 35356c7f5e7SAlex Bennée 35421a4179cSMarc Zyngier /* #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__) */ 35521a4179cSMarc Zyngier 35621a4179cSMarc Zyngier static inline void __cpu_init_stage2(void) 35721a4179cSMarc Zyngier { 35821a4179cSMarc Zyngier kvm_call_hyp(__init_stage2_translation); 35921a4179cSMarc Zyngier } 36021a4179cSMarc Zyngier 3614f8d6632SMarc Zyngier #endif /* __ARM64_KVM_HOST_H__ */ 362