1 /* 2 * Copyright (C) 2012,2013 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __ARM_KVM_ASM_H__ 19 #define __ARM_KVM_ASM_H__ 20 21 /* 22 * 0 is reserved as an invalid value. 23 * Order *must* be kept in sync with the hyp switch code. 24 */ 25 #define MPIDR_EL1 1 /* MultiProcessor Affinity Register */ 26 #define CSSELR_EL1 2 /* Cache Size Selection Register */ 27 #define SCTLR_EL1 3 /* System Control Register */ 28 #define ACTLR_EL1 4 /* Auxilliary Control Register */ 29 #define CPACR_EL1 5 /* Coprocessor Access Control */ 30 #define TTBR0_EL1 6 /* Translation Table Base Register 0 */ 31 #define TTBR1_EL1 7 /* Translation Table Base Register 1 */ 32 #define TCR_EL1 8 /* Translation Control Register */ 33 #define ESR_EL1 9 /* Exception Syndrome Register */ 34 #define AFSR0_EL1 10 /* Auxilary Fault Status Register 0 */ 35 #define AFSR1_EL1 11 /* Auxilary Fault Status Register 1 */ 36 #define FAR_EL1 12 /* Fault Address Register */ 37 #define MAIR_EL1 13 /* Memory Attribute Indirection Register */ 38 #define VBAR_EL1 14 /* Vector Base Address Register */ 39 #define CONTEXTIDR_EL1 15 /* Context ID Register */ 40 #define TPIDR_EL0 16 /* Thread ID, User R/W */ 41 #define TPIDRRO_EL0 17 /* Thread ID, User R/O */ 42 #define TPIDR_EL1 18 /* Thread ID, Privileged */ 43 #define AMAIR_EL1 19 /* Aux Memory Attribute Indirection Register */ 44 #define CNTKCTL_EL1 20 /* Timer Control Register (EL1) */ 45 #define PAR_EL1 21 /* Physical Address Register */ 46 /* 32bit specific registers. Keep them at the end of the range */ 47 #define DACR32_EL2 22 /* Domain Access Control Register */ 48 #define IFSR32_EL2 23 /* Instruction Fault Status Register */ 49 #define FPEXC32_EL2 24 /* Floating-Point Exception Control Register */ 50 #define DBGVCR32_EL2 25 /* Debug Vector Catch Register */ 51 #define TEECR32_EL1 26 /* ThumbEE Configuration Register */ 52 #define TEEHBR32_EL1 27 /* ThumbEE Handler Base Register */ 53 #define NR_SYS_REGS 28 54 55 /* 32bit mapping */ 56 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ 57 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ 58 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ 59 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ 60 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ 61 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ 62 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ 63 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ 64 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ 65 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ 66 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ 67 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ 68 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ 69 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ 70 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ 71 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ 72 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ 73 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ 74 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ 75 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ 76 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ 77 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ 78 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ 79 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ 80 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ 81 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ 82 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ 83 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ 84 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ 85 #define NR_CP15_REGS (NR_SYS_REGS * 2) 86 87 #define ARM_EXCEPTION_IRQ 0 88 #define ARM_EXCEPTION_TRAP 1 89 90 #ifndef __ASSEMBLY__ 91 struct kvm; 92 struct kvm_vcpu; 93 94 extern char __kvm_hyp_init[]; 95 extern char __kvm_hyp_init_end[]; 96 97 extern char __kvm_hyp_vector[]; 98 99 extern char __kvm_hyp_code_start[]; 100 extern char __kvm_hyp_code_end[]; 101 102 extern void __kvm_flush_vm_context(void); 103 extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa); 104 105 extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu); 106 #endif 107 108 #endif /* __ARM_KVM_ASM_H__ */ 109