1 /* 2 * Copyright (C) 2012,2013 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __ARM64_KVM_ARM_H__ 19 #define __ARM64_KVM_ARM_H__ 20 21 #include <asm/esr.h> 22 #include <asm/memory.h> 23 #include <asm/types.h> 24 25 /* Hyp Configuration Register (HCR) bits */ 26 #define HCR_FWB (UL(1) << 46) 27 #define HCR_TEA (UL(1) << 37) 28 #define HCR_TERR (UL(1) << 36) 29 #define HCR_TLOR (UL(1) << 35) 30 #define HCR_E2H (UL(1) << 34) 31 #define HCR_ID (UL(1) << 33) 32 #define HCR_CD (UL(1) << 32) 33 #define HCR_RW_SHIFT 31 34 #define HCR_RW (UL(1) << HCR_RW_SHIFT) 35 #define HCR_TRVM (UL(1) << 30) 36 #define HCR_HCD (UL(1) << 29) 37 #define HCR_TDZ (UL(1) << 28) 38 #define HCR_TGE (UL(1) << 27) 39 #define HCR_TVM (UL(1) << 26) 40 #define HCR_TTLB (UL(1) << 25) 41 #define HCR_TPU (UL(1) << 24) 42 #define HCR_TPC (UL(1) << 23) 43 #define HCR_TSW (UL(1) << 22) 44 #define HCR_TAC (UL(1) << 21) 45 #define HCR_TIDCP (UL(1) << 20) 46 #define HCR_TSC (UL(1) << 19) 47 #define HCR_TID3 (UL(1) << 18) 48 #define HCR_TID2 (UL(1) << 17) 49 #define HCR_TID1 (UL(1) << 16) 50 #define HCR_TID0 (UL(1) << 15) 51 #define HCR_TWE (UL(1) << 14) 52 #define HCR_TWI (UL(1) << 13) 53 #define HCR_DC (UL(1) << 12) 54 #define HCR_BSU (3 << 10) 55 #define HCR_BSU_IS (UL(1) << 10) 56 #define HCR_FB (UL(1) << 9) 57 #define HCR_VSE (UL(1) << 8) 58 #define HCR_VI (UL(1) << 7) 59 #define HCR_VF (UL(1) << 6) 60 #define HCR_AMO (UL(1) << 5) 61 #define HCR_IMO (UL(1) << 4) 62 #define HCR_FMO (UL(1) << 3) 63 #define HCR_PTW (UL(1) << 2) 64 #define HCR_SWIO (UL(1) << 1) 65 #define HCR_VM (UL(1) << 0) 66 67 /* 68 * The bits we set in HCR: 69 * TLOR: Trap LORegion register accesses 70 * RW: 64bit by default, can be overridden for 32bit VMs 71 * TAC: Trap ACTLR 72 * TSC: Trap SMC 73 * TVM: Trap VM ops (until M+C set in SCTLR_EL1) 74 * TSW: Trap cache operations by set/way 75 * TWE: Trap WFE 76 * TWI: Trap WFI 77 * TIDCP: Trap L2CTLR/L2ECTLR 78 * BSU_IS: Upgrade barriers to the inner shareable domain 79 * FB: Force broadcast of all maintainance operations 80 * AMO: Override CPSR.A and enable signaling with VA 81 * IMO: Override CPSR.I and enable signaling with VI 82 * FMO: Override CPSR.F and enable signaling with VF 83 * SWIO: Turn set/way invalidates into set/way clean+invalidate 84 */ 85 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ 86 HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \ 87 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ 88 HCR_FMO | HCR_IMO) 89 #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) 90 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) 91 92 /* TCR_EL2 Registers bits */ 93 #define TCR_EL2_RES1 ((1 << 31) | (1 << 23)) 94 #define TCR_EL2_TBI (1 << 20) 95 #define TCR_EL2_PS_SHIFT 16 96 #define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT) 97 #define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT) 98 #define TCR_EL2_TG0_MASK TCR_TG0_MASK 99 #define TCR_EL2_SH0_MASK TCR_SH0_MASK 100 #define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK 101 #define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK 102 #define TCR_EL2_T0SZ_MASK 0x3f 103 #define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \ 104 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK) 105 106 /* VTCR_EL2 Registers bits */ 107 #define VTCR_EL2_RES1 (1 << 31) 108 #define VTCR_EL2_HD (1 << 22) 109 #define VTCR_EL2_HA (1 << 21) 110 #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK 111 #define VTCR_EL2_TG0_MASK TCR_TG0_MASK 112 #define VTCR_EL2_TG0_4K TCR_TG0_4K 113 #define VTCR_EL2_TG0_16K TCR_TG0_16K 114 #define VTCR_EL2_TG0_64K TCR_TG0_64K 115 #define VTCR_EL2_SH0_MASK TCR_SH0_MASK 116 #define VTCR_EL2_SH0_INNER TCR_SH0_INNER 117 #define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK 118 #define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA 119 #define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK 120 #define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA 121 #define VTCR_EL2_SL0_SHIFT 6 122 #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT) 123 #define VTCR_EL2_SL0_LVL1 (1 << VTCR_EL2_SL0_SHIFT) 124 #define VTCR_EL2_T0SZ_MASK 0x3f 125 #define VTCR_EL2_T0SZ_40B 24 126 #define VTCR_EL2_VS_SHIFT 19 127 #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT) 128 #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT) 129 130 /* 131 * We configure the Stage-2 page tables to always restrict the IPA space to be 132 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are 133 * not known to exist and will break with this configuration. 134 * 135 * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time 136 * (see hyp-init.S). 137 * 138 * Note that when using 4K pages, we concatenate two first level page tables 139 * together. With 16K pages, we concatenate 16 first level page tables. 140 * 141 * The magic numbers used for VTTBR_X in this patch can be found in Tables 142 * D4-23 and D4-25 in ARM DDI 0487A.b. 143 */ 144 145 #define VTCR_EL2_T0SZ_IPA VTCR_EL2_T0SZ_40B 146 #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ 147 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1) 148 149 #ifdef CONFIG_ARM64_64K_PAGES 150 /* 151 * Stage2 translation configuration: 152 * 64kB pages (TG0 = 1) 153 * 2 level page tables (SL = 1) 154 */ 155 #define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1) 156 #define VTTBR_X_TGRAN_MAGIC 38 157 #elif defined(CONFIG_ARM64_16K_PAGES) 158 /* 159 * Stage2 translation configuration: 160 * 16kB pages (TG0 = 2) 161 * 2 level page tables (SL = 1) 162 */ 163 #define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_16K | VTCR_EL2_SL0_LVL1) 164 #define VTTBR_X_TGRAN_MAGIC 42 165 #else /* 4K */ 166 /* 167 * Stage2 translation configuration: 168 * 4kB pages (TG0 = 0) 169 * 3 level page tables (SL = 1) 170 */ 171 #define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SL0_LVL1) 172 #define VTTBR_X_TGRAN_MAGIC 37 173 #endif 174 175 #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS) 176 #define VTTBR_X (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA) 177 178 #define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_X) 179 #define VTTBR_VMID_SHIFT (UL(48)) 180 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) 181 182 /* Hyp System Trap Register */ 183 #define HSTR_EL2_T(x) (1 << x) 184 185 /* Hyp Coprocessor Trap Register Shifts */ 186 #define CPTR_EL2_TFP_SHIFT 10 187 188 /* Hyp Coprocessor Trap Register */ 189 #define CPTR_EL2_TCPAC (1 << 31) 190 #define CPTR_EL2_TTA (1 << 20) 191 #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT) 192 #define CPTR_EL2_TZ (1 << 8) 193 #define CPTR_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 */ 194 #define CPTR_EL2_DEFAULT CPTR_EL2_RES1 195 196 /* Hyp Debug Configuration Register bits */ 197 #define MDCR_EL2_TPMS (1 << 14) 198 #define MDCR_EL2_E2PB_MASK (UL(0x3)) 199 #define MDCR_EL2_E2PB_SHIFT (UL(12)) 200 #define MDCR_EL2_TDRA (1 << 11) 201 #define MDCR_EL2_TDOSA (1 << 10) 202 #define MDCR_EL2_TDA (1 << 9) 203 #define MDCR_EL2_TDE (1 << 8) 204 #define MDCR_EL2_HPME (1 << 7) 205 #define MDCR_EL2_TPM (1 << 6) 206 #define MDCR_EL2_TPMCR (1 << 5) 207 #define MDCR_EL2_HPMN_MASK (0x1F) 208 209 /* For compatibility with fault code shared with 32-bit */ 210 #define FSC_FAULT ESR_ELx_FSC_FAULT 211 #define FSC_ACCESS ESR_ELx_FSC_ACCESS 212 #define FSC_PERM ESR_ELx_FSC_PERM 213 #define FSC_SEA ESR_ELx_FSC_EXTABT 214 #define FSC_SEA_TTW0 (0x14) 215 #define FSC_SEA_TTW1 (0x15) 216 #define FSC_SEA_TTW2 (0x16) 217 #define FSC_SEA_TTW3 (0x17) 218 #define FSC_SECC (0x18) 219 #define FSC_SECC_TTW0 (0x1c) 220 #define FSC_SECC_TTW1 (0x1d) 221 #define FSC_SECC_TTW2 (0x1e) 222 #define FSC_SECC_TTW3 (0x1f) 223 224 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ 225 #define HPFAR_MASK (~UL(0xf)) 226 227 #define kvm_arm_exception_type \ 228 {0, "IRQ" }, \ 229 {1, "TRAP" } 230 231 #define ECN(x) { ESR_ELx_EC_##x, #x } 232 233 #define kvm_arm_exception_class \ 234 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \ 235 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \ 236 ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \ 237 ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \ 238 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \ 239 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \ 240 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \ 241 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64) 242 243 #define CPACR_EL1_FPEN (3 << 20) 244 #define CPACR_EL1_TTA (1 << 28) 245 #define CPACR_EL1_DEFAULT (CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN) 246 247 #endif /* __ARM64_KVM_ARM_H__ */ 248