1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM64_KVM_ARM_H__ 8 #define __ARM64_KVM_ARM_H__ 9 10 #include <asm/esr.h> 11 #include <asm/memory.h> 12 #include <asm/types.h> 13 14 /* Hyp Configuration Register (HCR) bits */ 15 16 #define HCR_TID5 (UL(1) << 58) 17 #define HCR_DCT (UL(1) << 57) 18 #define HCR_ATA_SHIFT 56 19 #define HCR_ATA (UL(1) << HCR_ATA_SHIFT) 20 #define HCR_AMVOFFEN (UL(1) << 51) 21 #define HCR_FIEN (UL(1) << 47) 22 #define HCR_FWB (UL(1) << 46) 23 #define HCR_API (UL(1) << 41) 24 #define HCR_APK (UL(1) << 40) 25 #define HCR_TEA (UL(1) << 37) 26 #define HCR_TERR (UL(1) << 36) 27 #define HCR_TLOR (UL(1) << 35) 28 #define HCR_E2H (UL(1) << 34) 29 #define HCR_ID (UL(1) << 33) 30 #define HCR_CD (UL(1) << 32) 31 #define HCR_RW_SHIFT 31 32 #define HCR_RW (UL(1) << HCR_RW_SHIFT) 33 #define HCR_TRVM (UL(1) << 30) 34 #define HCR_HCD (UL(1) << 29) 35 #define HCR_TDZ (UL(1) << 28) 36 #define HCR_TGE (UL(1) << 27) 37 #define HCR_TVM (UL(1) << 26) 38 #define HCR_TTLB (UL(1) << 25) 39 #define HCR_TPU (UL(1) << 24) 40 #define HCR_TPC (UL(1) << 23) /* HCR_TPCP if FEAT_DPB */ 41 #define HCR_TSW (UL(1) << 22) 42 #define HCR_TACR (UL(1) << 21) 43 #define HCR_TIDCP (UL(1) << 20) 44 #define HCR_TSC (UL(1) << 19) 45 #define HCR_TID3 (UL(1) << 18) 46 #define HCR_TID2 (UL(1) << 17) 47 #define HCR_TID1 (UL(1) << 16) 48 #define HCR_TID0 (UL(1) << 15) 49 #define HCR_TWE (UL(1) << 14) 50 #define HCR_TWI (UL(1) << 13) 51 #define HCR_DC (UL(1) << 12) 52 #define HCR_BSU (3 << 10) 53 #define HCR_BSU_IS (UL(1) << 10) 54 #define HCR_FB (UL(1) << 9) 55 #define HCR_VSE (UL(1) << 8) 56 #define HCR_VI (UL(1) << 7) 57 #define HCR_VF (UL(1) << 6) 58 #define HCR_AMO (UL(1) << 5) 59 #define HCR_IMO (UL(1) << 4) 60 #define HCR_FMO (UL(1) << 3) 61 #define HCR_PTW (UL(1) << 2) 62 #define HCR_SWIO (UL(1) << 1) 63 #define HCR_VM (UL(1) << 0) 64 #define HCR_RES0 ((UL(1) << 48) | (UL(1) << 39)) 65 66 /* 67 * The bits we set in HCR: 68 * TLOR: Trap LORegion register accesses 69 * RW: 64bit by default, can be overridden for 32bit VMs 70 * TACR: Trap ACTLR 71 * TSC: Trap SMC 72 * TSW: Trap cache operations by set/way 73 * TWE: Trap WFE 74 * TWI: Trap WFI 75 * TIDCP: Trap L2CTLR/L2ECTLR 76 * BSU_IS: Upgrade barriers to the inner shareable domain 77 * FB: Force broadcast of all maintenance operations 78 * AMO: Override CPSR.A and enable signaling with VA 79 * IMO: Override CPSR.I and enable signaling with VI 80 * FMO: Override CPSR.F and enable signaling with VF 81 * SWIO: Turn set/way invalidates into set/way clean+invalidate 82 * PTW: Take a stage2 fault if a stage1 walk steps in device memory 83 */ 84 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ 85 HCR_BSU_IS | HCR_FB | HCR_TACR | \ 86 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ 87 HCR_FMO | HCR_IMO | HCR_PTW ) 88 #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) 89 #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) 90 #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) 91 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) 92 93 /* TCR_EL2 Registers bits */ 94 #define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) 95 #define TCR_EL2_TBI (1 << 20) 96 #define TCR_EL2_PS_SHIFT 16 97 #define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT) 98 #define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT) 99 #define TCR_EL2_TG0_MASK TCR_TG0_MASK 100 #define TCR_EL2_SH0_MASK TCR_SH0_MASK 101 #define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK 102 #define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK 103 #define TCR_EL2_T0SZ_MASK 0x3f 104 #define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \ 105 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK) 106 107 /* VTCR_EL2 Registers bits */ 108 #define VTCR_EL2_RES1 (1U << 31) 109 #define VTCR_EL2_HD (1 << 22) 110 #define VTCR_EL2_HA (1 << 21) 111 #define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT 112 #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK 113 #define VTCR_EL2_TG0_MASK TCR_TG0_MASK 114 #define VTCR_EL2_TG0_4K TCR_TG0_4K 115 #define VTCR_EL2_TG0_16K TCR_TG0_16K 116 #define VTCR_EL2_TG0_64K TCR_TG0_64K 117 #define VTCR_EL2_SH0_MASK TCR_SH0_MASK 118 #define VTCR_EL2_SH0_INNER TCR_SH0_INNER 119 #define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK 120 #define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA 121 #define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK 122 #define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA 123 #define VTCR_EL2_SL0_SHIFT 6 124 #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT) 125 #define VTCR_EL2_T0SZ_MASK 0x3f 126 #define VTCR_EL2_VS_SHIFT 19 127 #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT) 128 #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT) 129 130 #define VTCR_EL2_T0SZ(x) TCR_T0SZ(x) 131 132 /* 133 * We configure the Stage-2 page tables to always restrict the IPA space to be 134 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are 135 * not known to exist and will break with this configuration. 136 * 137 * The VTCR_EL2 is configured per VM and is initialised in kvm_arm_setup_stage2(). 138 * 139 * Note that when using 4K pages, we concatenate two first level page tables 140 * together. With 16K pages, we concatenate 16 first level page tables. 141 * 142 */ 143 144 #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ 145 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1) 146 147 /* 148 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation. 149 * Interestingly, it depends on the page size. 150 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a 151 * 152 * ----------------------------------------- 153 * | Entry level | 4K | 16K/64K | 154 * ------------------------------------------ 155 * | Level: 0 | 2 | - | 156 * ------------------------------------------ 157 * | Level: 1 | 1 | 2 | 158 * ------------------------------------------ 159 * | Level: 2 | 0 | 1 | 160 * ------------------------------------------ 161 * | Level: 3 | - | 0 | 162 * ------------------------------------------ 163 * 164 * The table roughly translates to : 165 * 166 * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level 167 * 168 * Where TGRAN_SL0_BASE is a magic number depending on the page size: 169 * TGRAN_SL0_BASE(4K) = 2 170 * TGRAN_SL0_BASE(16K) = 3 171 * TGRAN_SL0_BASE(64K) = 3 172 * provided we take care of ruling out the unsupported cases and 173 * Entry_Level = 4 - Number_of_levels. 174 * 175 */ 176 #ifdef CONFIG_ARM64_64K_PAGES 177 178 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K 179 #define VTCR_EL2_TGRAN_SL0_BASE 3UL 180 181 #elif defined(CONFIG_ARM64_16K_PAGES) 182 183 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K 184 #define VTCR_EL2_TGRAN_SL0_BASE 3UL 185 186 #else /* 4K */ 187 188 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K 189 #define VTCR_EL2_TGRAN_SL0_BASE 2UL 190 191 #endif 192 193 #define VTCR_EL2_LVLS_TO_SL0(levels) \ 194 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT) 195 #define VTCR_EL2_SL0_TO_LVLS(sl0) \ 196 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE) 197 #define VTCR_EL2_LVLS(vtcr) \ 198 VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT) 199 200 #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN) 201 #define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK)) 202 203 /* 204 * ARM VMSAv8-64 defines an algorithm for finding the translation table 205 * descriptors in section D4.2.8 in ARM DDI 0487C.a. 206 * 207 * The algorithm defines the expectations on the translation table 208 * addresses for each level, based on PAGE_SIZE, entry level 209 * and the translation table size (T0SZ). The variable "x" in the 210 * algorithm determines the alignment of a table base address at a given 211 * level and thus determines the alignment of VTTBR:BADDR for stage2 212 * page table entry level. 213 * Since the number of bits resolved at the entry level could vary 214 * depending on the T0SZ, the value of "x" is defined based on a 215 * Magic constant for a given PAGE_SIZE and Entry Level. The 216 * intermediate levels must be always aligned to the PAGE_SIZE (i.e, 217 * x = PAGE_SHIFT). 218 * 219 * The value of "x" for entry level is calculated as : 220 * x = Magic_N - T0SZ 221 * 222 * where Magic_N is an integer depending on the page size and the entry 223 * level of the page table as below: 224 * 225 * -------------------------------------------- 226 * | Entry level | 4K 16K 64K | 227 * -------------------------------------------- 228 * | Level: 0 (4 levels) | 28 | - | - | 229 * -------------------------------------------- 230 * | Level: 1 (3 levels) | 37 | 31 | 25 | 231 * -------------------------------------------- 232 * | Level: 2 (2 levels) | 46 | 42 | 38 | 233 * -------------------------------------------- 234 * | Level: 3 (1 level) | - | 53 | 51 | 235 * -------------------------------------------- 236 * 237 * We have a magic formula for the Magic_N below: 238 * 239 * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels) 240 * 241 * where Number_of_levels = (4 - Level). We are only interested in the 242 * value for Entry_Level for the stage2 page table. 243 * 244 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows: 245 * 246 * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT) 247 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels) 248 * 249 * Here is one way to explain the Magic Formula: 250 * 251 * x = log2(Size_of_Entry_Level_Table) 252 * 253 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another 254 * PAGE_SHIFT bits in the PTE, we have : 255 * 256 * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT) 257 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3 258 * where n = number of levels, and since each pointer is 8bytes, we have: 259 * 260 * x = Bits_Entry_Level + 3 261 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n 262 * 263 * The only constraint here is that, we have to find the number of page table 264 * levels for a given IPA size (which we do, see stage2_pt_levels()) 265 */ 266 #define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3))) 267 268 #define VTTBR_CNP_BIT (UL(1)) 269 #define VTTBR_VMID_SHIFT (UL(48)) 270 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) 271 272 /* Hyp System Trap Register */ 273 #define HSTR_EL2_T(x) (1 << x) 274 275 /* Hyp Coprocessor Trap Register Shifts */ 276 #define CPTR_EL2_TFP_SHIFT 10 277 278 /* Hyp Coprocessor Trap Register */ 279 #define CPTR_EL2_TCPAC (1U << 31) 280 #define CPTR_EL2_TAM (1 << 30) 281 #define CPTR_EL2_TTA (1 << 20) 282 #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT) 283 #define CPTR_EL2_TZ (1 << 8) 284 #define CPTR_NVHE_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */ 285 #define CPTR_EL2_DEFAULT CPTR_NVHE_EL2_RES1 286 #define CPTR_NVHE_EL2_RES0 (GENMASK(63, 32) | \ 287 GENMASK(29, 21) | \ 288 GENMASK(19, 14) | \ 289 BIT(11)) 290 291 /* Hyp Debug Configuration Register bits */ 292 #define MDCR_EL2_E2TB_MASK (UL(0x3)) 293 #define MDCR_EL2_E2TB_SHIFT (UL(24)) 294 #define MDCR_EL2_HPMFZS (UL(1) << 36) 295 #define MDCR_EL2_HPMFZO (UL(1) << 29) 296 #define MDCR_EL2_MTPME (UL(1) << 28) 297 #define MDCR_EL2_TDCC (UL(1) << 27) 298 #define MDCR_EL2_HLP (UL(1) << 26) 299 #define MDCR_EL2_HCCD (UL(1) << 23) 300 #define MDCR_EL2_TTRF (UL(1) << 19) 301 #define MDCR_EL2_HPMD (UL(1) << 17) 302 #define MDCR_EL2_TPMS (UL(1) << 14) 303 #define MDCR_EL2_E2PB_MASK (UL(0x3)) 304 #define MDCR_EL2_E2PB_SHIFT (UL(12)) 305 #define MDCR_EL2_TDRA (UL(1) << 11) 306 #define MDCR_EL2_TDOSA (UL(1) << 10) 307 #define MDCR_EL2_TDA (UL(1) << 9) 308 #define MDCR_EL2_TDE (UL(1) << 8) 309 #define MDCR_EL2_HPME (UL(1) << 7) 310 #define MDCR_EL2_TPM (UL(1) << 6) 311 #define MDCR_EL2_TPMCR (UL(1) << 5) 312 #define MDCR_EL2_HPMN_MASK (UL(0x1F)) 313 #define MDCR_EL2_RES0 (GENMASK(63, 37) | \ 314 GENMASK(35, 30) | \ 315 GENMASK(25, 24) | \ 316 GENMASK(22, 20) | \ 317 BIT(18) | \ 318 GENMASK(16, 15)) 319 320 /* For compatibility with fault code shared with 32-bit */ 321 #define FSC_FAULT ESR_ELx_FSC_FAULT 322 #define FSC_ACCESS ESR_ELx_FSC_ACCESS 323 #define FSC_PERM ESR_ELx_FSC_PERM 324 #define FSC_SEA ESR_ELx_FSC_EXTABT 325 #define FSC_SEA_TTW0 (0x14) 326 #define FSC_SEA_TTW1 (0x15) 327 #define FSC_SEA_TTW2 (0x16) 328 #define FSC_SEA_TTW3 (0x17) 329 #define FSC_SECC (0x18) 330 #define FSC_SECC_TTW0 (0x1c) 331 #define FSC_SECC_TTW1 (0x1d) 332 #define FSC_SECC_TTW2 (0x1e) 333 #define FSC_SECC_TTW3 (0x1f) 334 335 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ 336 #define HPFAR_MASK (~UL(0xf)) 337 /* 338 * We have 339 * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12] 340 * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12] 341 */ 342 #define PAR_TO_HPFAR(par) \ 343 (((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8) 344 345 #define ECN(x) { ESR_ELx_EC_##x, #x } 346 347 #define kvm_arm_exception_class \ 348 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \ 349 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \ 350 ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \ 351 ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \ 352 ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \ 353 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \ 354 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \ 355 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \ 356 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64) 357 358 #define CPACR_EL1_FPEN (3 << 20) 359 #define CPACR_EL1_TTA (1 << 28) 360 #define CPACR_EL1_DEFAULT (CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN) 361 362 #endif /* __ARM64_KVM_ARM_H__ */ 363