1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM64_KVM_ARM_H__ 8 #define __ARM64_KVM_ARM_H__ 9 10 #include <asm/esr.h> 11 #include <asm/memory.h> 12 #include <asm/sysreg.h> 13 #include <asm/types.h> 14 15 /* Hyp Configuration Register (HCR) bits */ 16 17 #define HCR_TID5 (UL(1) << 58) 18 #define HCR_DCT (UL(1) << 57) 19 #define HCR_ATA_SHIFT 56 20 #define HCR_ATA (UL(1) << HCR_ATA_SHIFT) 21 #define HCR_AMVOFFEN (UL(1) << 51) 22 #define HCR_FIEN (UL(1) << 47) 23 #define HCR_FWB (UL(1) << 46) 24 #define HCR_API (UL(1) << 41) 25 #define HCR_APK (UL(1) << 40) 26 #define HCR_TEA (UL(1) << 37) 27 #define HCR_TERR (UL(1) << 36) 28 #define HCR_TLOR (UL(1) << 35) 29 #define HCR_E2H (UL(1) << 34) 30 #define HCR_ID (UL(1) << 33) 31 #define HCR_CD (UL(1) << 32) 32 #define HCR_RW_SHIFT 31 33 #define HCR_RW (UL(1) << HCR_RW_SHIFT) 34 #define HCR_TRVM (UL(1) << 30) 35 #define HCR_HCD (UL(1) << 29) 36 #define HCR_TDZ (UL(1) << 28) 37 #define HCR_TGE (UL(1) << 27) 38 #define HCR_TVM (UL(1) << 26) 39 #define HCR_TTLB (UL(1) << 25) 40 #define HCR_TPU (UL(1) << 24) 41 #define HCR_TPC (UL(1) << 23) /* HCR_TPCP if FEAT_DPB */ 42 #define HCR_TSW (UL(1) << 22) 43 #define HCR_TACR (UL(1) << 21) 44 #define HCR_TIDCP (UL(1) << 20) 45 #define HCR_TSC (UL(1) << 19) 46 #define HCR_TID3 (UL(1) << 18) 47 #define HCR_TID2 (UL(1) << 17) 48 #define HCR_TID1 (UL(1) << 16) 49 #define HCR_TID0 (UL(1) << 15) 50 #define HCR_TWE (UL(1) << 14) 51 #define HCR_TWI (UL(1) << 13) 52 #define HCR_DC (UL(1) << 12) 53 #define HCR_BSU (3 << 10) 54 #define HCR_BSU_IS (UL(1) << 10) 55 #define HCR_FB (UL(1) << 9) 56 #define HCR_VSE (UL(1) << 8) 57 #define HCR_VI (UL(1) << 7) 58 #define HCR_VF (UL(1) << 6) 59 #define HCR_AMO (UL(1) << 5) 60 #define HCR_IMO (UL(1) << 4) 61 #define HCR_FMO (UL(1) << 3) 62 #define HCR_PTW (UL(1) << 2) 63 #define HCR_SWIO (UL(1) << 1) 64 #define HCR_VM (UL(1) << 0) 65 #define HCR_RES0 ((UL(1) << 48) | (UL(1) << 39)) 66 67 /* 68 * The bits we set in HCR: 69 * TLOR: Trap LORegion register accesses 70 * RW: 64bit by default, can be overridden for 32bit VMs 71 * TACR: Trap ACTLR 72 * TSC: Trap SMC 73 * TSW: Trap cache operations by set/way 74 * TWE: Trap WFE 75 * TWI: Trap WFI 76 * TIDCP: Trap L2CTLR/L2ECTLR 77 * BSU_IS: Upgrade barriers to the inner shareable domain 78 * FB: Force broadcast of all maintenance operations 79 * AMO: Override CPSR.A and enable signaling with VA 80 * IMO: Override CPSR.I and enable signaling with VI 81 * FMO: Override CPSR.F and enable signaling with VF 82 * SWIO: Turn set/way invalidates into set/way clean+invalidate 83 * PTW: Take a stage2 fault if a stage1 walk steps in device memory 84 * TID3: Trap EL1 reads of group 3 ID registers 85 * TID2: Trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1 86 */ 87 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ 88 HCR_BSU_IS | HCR_FB | HCR_TACR | \ 89 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ 90 HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 | HCR_TID2) 91 #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) 92 #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) 93 #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) 94 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) 95 96 #define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En) 97 #define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En) 98 99 /* TCR_EL2 Registers bits */ 100 #define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) 101 #define TCR_EL2_TBI (1 << 20) 102 #define TCR_EL2_PS_SHIFT 16 103 #define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT) 104 #define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT) 105 #define TCR_EL2_TG0_MASK TCR_TG0_MASK 106 #define TCR_EL2_SH0_MASK TCR_SH0_MASK 107 #define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK 108 #define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK 109 #define TCR_EL2_T0SZ_MASK 0x3f 110 #define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \ 111 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK) 112 113 /* VTCR_EL2 Registers bits */ 114 #define VTCR_EL2_RES1 (1U << 31) 115 #define VTCR_EL2_HD (1 << 22) 116 #define VTCR_EL2_HA (1 << 21) 117 #define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT 118 #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK 119 #define VTCR_EL2_TG0_MASK TCR_TG0_MASK 120 #define VTCR_EL2_TG0_4K TCR_TG0_4K 121 #define VTCR_EL2_TG0_16K TCR_TG0_16K 122 #define VTCR_EL2_TG0_64K TCR_TG0_64K 123 #define VTCR_EL2_SH0_MASK TCR_SH0_MASK 124 #define VTCR_EL2_SH0_INNER TCR_SH0_INNER 125 #define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK 126 #define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA 127 #define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK 128 #define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA 129 #define VTCR_EL2_SL0_SHIFT 6 130 #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT) 131 #define VTCR_EL2_T0SZ_MASK 0x3f 132 #define VTCR_EL2_VS_SHIFT 19 133 #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT) 134 #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT) 135 136 #define VTCR_EL2_T0SZ(x) TCR_T0SZ(x) 137 138 /* 139 * We configure the Stage-2 page tables to always restrict the IPA space to be 140 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are 141 * not known to exist and will break with this configuration. 142 * 143 * The VTCR_EL2 is configured per VM and is initialised in kvm_init_stage2_mmu. 144 * 145 * Note that when using 4K pages, we concatenate two first level page tables 146 * together. With 16K pages, we concatenate 16 first level page tables. 147 * 148 */ 149 150 #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ 151 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1) 152 153 /* 154 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation. 155 * Interestingly, it depends on the page size. 156 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a 157 * 158 * ----------------------------------------- 159 * | Entry level | 4K | 16K/64K | 160 * ------------------------------------------ 161 * | Level: 0 | 2 | - | 162 * ------------------------------------------ 163 * | Level: 1 | 1 | 2 | 164 * ------------------------------------------ 165 * | Level: 2 | 0 | 1 | 166 * ------------------------------------------ 167 * | Level: 3 | - | 0 | 168 * ------------------------------------------ 169 * 170 * The table roughly translates to : 171 * 172 * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level 173 * 174 * Where TGRAN_SL0_BASE is a magic number depending on the page size: 175 * TGRAN_SL0_BASE(4K) = 2 176 * TGRAN_SL0_BASE(16K) = 3 177 * TGRAN_SL0_BASE(64K) = 3 178 * provided we take care of ruling out the unsupported cases and 179 * Entry_Level = 4 - Number_of_levels. 180 * 181 */ 182 #ifdef CONFIG_ARM64_64K_PAGES 183 184 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K 185 #define VTCR_EL2_TGRAN_SL0_BASE 3UL 186 187 #elif defined(CONFIG_ARM64_16K_PAGES) 188 189 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K 190 #define VTCR_EL2_TGRAN_SL0_BASE 3UL 191 192 #else /* 4K */ 193 194 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K 195 #define VTCR_EL2_TGRAN_SL0_BASE 2UL 196 197 #endif 198 199 #define VTCR_EL2_LVLS_TO_SL0(levels) \ 200 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT) 201 #define VTCR_EL2_SL0_TO_LVLS(sl0) \ 202 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE) 203 #define VTCR_EL2_LVLS(vtcr) \ 204 VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT) 205 206 #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN) 207 #define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK)) 208 209 /* 210 * ARM VMSAv8-64 defines an algorithm for finding the translation table 211 * descriptors in section D4.2.8 in ARM DDI 0487C.a. 212 * 213 * The algorithm defines the expectations on the translation table 214 * addresses for each level, based on PAGE_SIZE, entry level 215 * and the translation table size (T0SZ). The variable "x" in the 216 * algorithm determines the alignment of a table base address at a given 217 * level and thus determines the alignment of VTTBR:BADDR for stage2 218 * page table entry level. 219 * Since the number of bits resolved at the entry level could vary 220 * depending on the T0SZ, the value of "x" is defined based on a 221 * Magic constant for a given PAGE_SIZE and Entry Level. The 222 * intermediate levels must be always aligned to the PAGE_SIZE (i.e, 223 * x = PAGE_SHIFT). 224 * 225 * The value of "x" for entry level is calculated as : 226 * x = Magic_N - T0SZ 227 * 228 * where Magic_N is an integer depending on the page size and the entry 229 * level of the page table as below: 230 * 231 * -------------------------------------------- 232 * | Entry level | 4K 16K 64K | 233 * -------------------------------------------- 234 * | Level: 0 (4 levels) | 28 | - | - | 235 * -------------------------------------------- 236 * | Level: 1 (3 levels) | 37 | 31 | 25 | 237 * -------------------------------------------- 238 * | Level: 2 (2 levels) | 46 | 42 | 38 | 239 * -------------------------------------------- 240 * | Level: 3 (1 level) | - | 53 | 51 | 241 * -------------------------------------------- 242 * 243 * We have a magic formula for the Magic_N below: 244 * 245 * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels) 246 * 247 * where Number_of_levels = (4 - Level). We are only interested in the 248 * value for Entry_Level for the stage2 page table. 249 * 250 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows: 251 * 252 * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT) 253 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels) 254 * 255 * Here is one way to explain the Magic Formula: 256 * 257 * x = log2(Size_of_Entry_Level_Table) 258 * 259 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another 260 * PAGE_SHIFT bits in the PTE, we have : 261 * 262 * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT) 263 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3 264 * where n = number of levels, and since each pointer is 8bytes, we have: 265 * 266 * x = Bits_Entry_Level + 3 267 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n 268 * 269 * The only constraint here is that, we have to find the number of page table 270 * levels for a given IPA size (which we do, see stage2_pt_levels()) 271 */ 272 #define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3))) 273 274 #define VTTBR_CNP_BIT (UL(1)) 275 #define VTTBR_VMID_SHIFT (UL(48)) 276 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) 277 278 /* Hyp System Trap Register */ 279 #define HSTR_EL2_T(x) (1 << x) 280 281 /* Hyp Coprocessor Trap Register Shifts */ 282 #define CPTR_EL2_TFP_SHIFT 10 283 284 /* Hyp Coprocessor Trap Register */ 285 #define CPTR_EL2_TCPAC (1U << 31) 286 #define CPTR_EL2_TAM (1 << 30) 287 #define CPTR_EL2_TTA (1 << 20) 288 #define CPTR_EL2_TSM (1 << 12) 289 #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT) 290 #define CPTR_EL2_TZ (1 << 8) 291 #define CPTR_NVHE_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */ 292 #define CPTR_EL2_DEFAULT CPTR_NVHE_EL2_RES1 293 #define CPTR_NVHE_EL2_RES0 (GENMASK(63, 32) | \ 294 GENMASK(29, 21) | \ 295 GENMASK(19, 14) | \ 296 BIT(11)) 297 298 /* Hyp Debug Configuration Register bits */ 299 #define MDCR_EL2_E2TB_MASK (UL(0x3)) 300 #define MDCR_EL2_E2TB_SHIFT (UL(24)) 301 #define MDCR_EL2_HPMFZS (UL(1) << 36) 302 #define MDCR_EL2_HPMFZO (UL(1) << 29) 303 #define MDCR_EL2_MTPME (UL(1) << 28) 304 #define MDCR_EL2_TDCC (UL(1) << 27) 305 #define MDCR_EL2_HLP (UL(1) << 26) 306 #define MDCR_EL2_HCCD (UL(1) << 23) 307 #define MDCR_EL2_TTRF (UL(1) << 19) 308 #define MDCR_EL2_HPMD (UL(1) << 17) 309 #define MDCR_EL2_TPMS (UL(1) << 14) 310 #define MDCR_EL2_E2PB_MASK (UL(0x3)) 311 #define MDCR_EL2_E2PB_SHIFT (UL(12)) 312 #define MDCR_EL2_TDRA (UL(1) << 11) 313 #define MDCR_EL2_TDOSA (UL(1) << 10) 314 #define MDCR_EL2_TDA (UL(1) << 9) 315 #define MDCR_EL2_TDE (UL(1) << 8) 316 #define MDCR_EL2_HPME (UL(1) << 7) 317 #define MDCR_EL2_TPM (UL(1) << 6) 318 #define MDCR_EL2_TPMCR (UL(1) << 5) 319 #define MDCR_EL2_HPMN_MASK (UL(0x1F)) 320 #define MDCR_EL2_RES0 (GENMASK(63, 37) | \ 321 GENMASK(35, 30) | \ 322 GENMASK(25, 24) | \ 323 GENMASK(22, 20) | \ 324 BIT(18) | \ 325 GENMASK(16, 15)) 326 327 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ 328 #define HPFAR_MASK (~UL(0xf)) 329 /* 330 * We have 331 * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12] 332 * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12] 333 * 334 * Always assume 52 bit PA since at this point, we don't know how many PA bits 335 * the page table has been set up for. This should be safe since unused address 336 * bits in PAR are res0. 337 */ 338 #define PAR_TO_HPFAR(par) \ 339 (((par) & GENMASK_ULL(52 - 1, 12)) >> 8) 340 341 #define ECN(x) { ESR_ELx_EC_##x, #x } 342 343 #define kvm_arm_exception_class \ 344 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \ 345 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \ 346 ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \ 347 ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \ 348 ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \ 349 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \ 350 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \ 351 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \ 352 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64), ECN(ERET) 353 354 #define CPACR_EL1_DEFAULT (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN |\ 355 CPACR_EL1_ZEN_EL1EN) 356 357 #define kvm_mode_names \ 358 { PSR_MODE_EL0t, "EL0t" }, \ 359 { PSR_MODE_EL1t, "EL1t" }, \ 360 { PSR_MODE_EL1h, "EL1h" }, \ 361 { PSR_MODE_EL2t, "EL2t" }, \ 362 { PSR_MODE_EL2h, "EL2h" }, \ 363 { PSR_MODE_EL3t, "EL3t" }, \ 364 { PSR_MODE_EL3h, "EL3h" }, \ 365 { PSR_AA32_MODE_USR, "32-bit USR" }, \ 366 { PSR_AA32_MODE_FIQ, "32-bit FIQ" }, \ 367 { PSR_AA32_MODE_IRQ, "32-bit IRQ" }, \ 368 { PSR_AA32_MODE_SVC, "32-bit SVC" }, \ 369 { PSR_AA32_MODE_ABT, "32-bit ABT" }, \ 370 { PSR_AA32_MODE_HYP, "32-bit HYP" }, \ 371 { PSR_AA32_MODE_UND, "32-bit UND" }, \ 372 { PSR_AA32_MODE_SYS, "32-bit SYS" } 373 374 #endif /* __ARM64_KVM_ARM_H__ */ 375