1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM64_KVM_ARM_H__ 8 #define __ARM64_KVM_ARM_H__ 9 10 #include <asm/esr.h> 11 #include <asm/memory.h> 12 #include <asm/sysreg.h> 13 #include <asm/types.h> 14 15 /* Hyp Configuration Register (HCR) bits */ 16 17 #define HCR_TID5 (UL(1) << 58) 18 #define HCR_DCT (UL(1) << 57) 19 #define HCR_ATA_SHIFT 56 20 #define HCR_ATA (UL(1) << HCR_ATA_SHIFT) 21 #define HCR_TTLBOS (UL(1) << 55) 22 #define HCR_TTLBIS (UL(1) << 54) 23 #define HCR_ENSCXT (UL(1) << 53) 24 #define HCR_TOCU (UL(1) << 52) 25 #define HCR_AMVOFFEN (UL(1) << 51) 26 #define HCR_TICAB (UL(1) << 50) 27 #define HCR_TID4 (UL(1) << 49) 28 #define HCR_FIEN (UL(1) << 47) 29 #define HCR_FWB (UL(1) << 46) 30 #define HCR_NV2 (UL(1) << 45) 31 #define HCR_AT (UL(1) << 44) 32 #define HCR_NV1 (UL(1) << 43) 33 #define HCR_NV (UL(1) << 42) 34 #define HCR_API (UL(1) << 41) 35 #define HCR_APK (UL(1) << 40) 36 #define HCR_TEA (UL(1) << 37) 37 #define HCR_TERR (UL(1) << 36) 38 #define HCR_TLOR (UL(1) << 35) 39 #define HCR_E2H (UL(1) << 34) 40 #define HCR_ID (UL(1) << 33) 41 #define HCR_CD (UL(1) << 32) 42 #define HCR_RW_SHIFT 31 43 #define HCR_RW (UL(1) << HCR_RW_SHIFT) 44 #define HCR_TRVM (UL(1) << 30) 45 #define HCR_HCD (UL(1) << 29) 46 #define HCR_TDZ (UL(1) << 28) 47 #define HCR_TGE (UL(1) << 27) 48 #define HCR_TVM (UL(1) << 26) 49 #define HCR_TTLB (UL(1) << 25) 50 #define HCR_TPU (UL(1) << 24) 51 #define HCR_TPC (UL(1) << 23) /* HCR_TPCP if FEAT_DPB */ 52 #define HCR_TSW (UL(1) << 22) 53 #define HCR_TACR (UL(1) << 21) 54 #define HCR_TIDCP (UL(1) << 20) 55 #define HCR_TSC (UL(1) << 19) 56 #define HCR_TID3 (UL(1) << 18) 57 #define HCR_TID2 (UL(1) << 17) 58 #define HCR_TID1 (UL(1) << 16) 59 #define HCR_TID0 (UL(1) << 15) 60 #define HCR_TWE (UL(1) << 14) 61 #define HCR_TWI (UL(1) << 13) 62 #define HCR_DC (UL(1) << 12) 63 #define HCR_BSU (3 << 10) 64 #define HCR_BSU_IS (UL(1) << 10) 65 #define HCR_FB (UL(1) << 9) 66 #define HCR_VSE (UL(1) << 8) 67 #define HCR_VI (UL(1) << 7) 68 #define HCR_VF (UL(1) << 6) 69 #define HCR_AMO (UL(1) << 5) 70 #define HCR_IMO (UL(1) << 4) 71 #define HCR_FMO (UL(1) << 3) 72 #define HCR_PTW (UL(1) << 2) 73 #define HCR_SWIO (UL(1) << 1) 74 #define HCR_VM (UL(1) << 0) 75 #define HCR_RES0 ((UL(1) << 48) | (UL(1) << 39)) 76 77 /* 78 * The bits we set in HCR: 79 * TLOR: Trap LORegion register accesses 80 * RW: 64bit by default, can be overridden for 32bit VMs 81 * TACR: Trap ACTLR 82 * TSC: Trap SMC 83 * TSW: Trap cache operations by set/way 84 * TWE: Trap WFE 85 * TWI: Trap WFI 86 * TIDCP: Trap L2CTLR/L2ECTLR 87 * BSU_IS: Upgrade barriers to the inner shareable domain 88 * FB: Force broadcast of all maintenance operations 89 * AMO: Override CPSR.A and enable signaling with VA 90 * IMO: Override CPSR.I and enable signaling with VI 91 * FMO: Override CPSR.F and enable signaling with VF 92 * SWIO: Turn set/way invalidates into set/way clean+invalidate 93 * PTW: Take a stage2 fault if a stage1 walk steps in device memory 94 * TID3: Trap EL1 reads of group 3 ID registers 95 * TID2: Trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1 96 */ 97 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ 98 HCR_BSU_IS | HCR_FB | HCR_TACR | \ 99 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ 100 HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3) 101 #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) 102 #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) 103 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) 104 105 #define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En) 106 #define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En) 107 108 /* TCR_EL2 Registers bits */ 109 #define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) 110 #define TCR_EL2_TBI (1 << 20) 111 #define TCR_EL2_PS_SHIFT 16 112 #define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT) 113 #define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT) 114 #define TCR_EL2_TG0_MASK TCR_TG0_MASK 115 #define TCR_EL2_SH0_MASK TCR_SH0_MASK 116 #define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK 117 #define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK 118 #define TCR_EL2_T0SZ_MASK 0x3f 119 #define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \ 120 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK) 121 122 /* VTCR_EL2 Registers bits */ 123 #define VTCR_EL2_RES1 (1U << 31) 124 #define VTCR_EL2_HD (1 << 22) 125 #define VTCR_EL2_HA (1 << 21) 126 #define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT 127 #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK 128 #define VTCR_EL2_TG0_MASK TCR_TG0_MASK 129 #define VTCR_EL2_TG0_4K TCR_TG0_4K 130 #define VTCR_EL2_TG0_16K TCR_TG0_16K 131 #define VTCR_EL2_TG0_64K TCR_TG0_64K 132 #define VTCR_EL2_SH0_MASK TCR_SH0_MASK 133 #define VTCR_EL2_SH0_INNER TCR_SH0_INNER 134 #define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK 135 #define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA 136 #define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK 137 #define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA 138 #define VTCR_EL2_SL0_SHIFT 6 139 #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT) 140 #define VTCR_EL2_T0SZ_MASK 0x3f 141 #define VTCR_EL2_VS_SHIFT 19 142 #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT) 143 #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT) 144 145 #define VTCR_EL2_T0SZ(x) TCR_T0SZ(x) 146 147 /* 148 * We configure the Stage-2 page tables to always restrict the IPA space to be 149 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are 150 * not known to exist and will break with this configuration. 151 * 152 * The VTCR_EL2 is configured per VM and is initialised in kvm_init_stage2_mmu. 153 * 154 * Note that when using 4K pages, we concatenate two first level page tables 155 * together. With 16K pages, we concatenate 16 first level page tables. 156 * 157 */ 158 159 #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ 160 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1) 161 162 /* 163 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation. 164 * Interestingly, it depends on the page size. 165 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a 166 * 167 * ----------------------------------------- 168 * | Entry level | 4K | 16K/64K | 169 * ------------------------------------------ 170 * | Level: 0 | 2 | - | 171 * ------------------------------------------ 172 * | Level: 1 | 1 | 2 | 173 * ------------------------------------------ 174 * | Level: 2 | 0 | 1 | 175 * ------------------------------------------ 176 * | Level: 3 | - | 0 | 177 * ------------------------------------------ 178 * 179 * The table roughly translates to : 180 * 181 * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level 182 * 183 * Where TGRAN_SL0_BASE is a magic number depending on the page size: 184 * TGRAN_SL0_BASE(4K) = 2 185 * TGRAN_SL0_BASE(16K) = 3 186 * TGRAN_SL0_BASE(64K) = 3 187 * provided we take care of ruling out the unsupported cases and 188 * Entry_Level = 4 - Number_of_levels. 189 * 190 */ 191 #ifdef CONFIG_ARM64_64K_PAGES 192 193 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K 194 #define VTCR_EL2_TGRAN_SL0_BASE 3UL 195 196 #elif defined(CONFIG_ARM64_16K_PAGES) 197 198 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K 199 #define VTCR_EL2_TGRAN_SL0_BASE 3UL 200 201 #else /* 4K */ 202 203 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K 204 #define VTCR_EL2_TGRAN_SL0_BASE 2UL 205 206 #endif 207 208 #define VTCR_EL2_LVLS_TO_SL0(levels) \ 209 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT) 210 #define VTCR_EL2_SL0_TO_LVLS(sl0) \ 211 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE) 212 #define VTCR_EL2_LVLS(vtcr) \ 213 VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT) 214 215 #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN) 216 #define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK)) 217 218 /* 219 * ARM VMSAv8-64 defines an algorithm for finding the translation table 220 * descriptors in section D4.2.8 in ARM DDI 0487C.a. 221 * 222 * The algorithm defines the expectations on the translation table 223 * addresses for each level, based on PAGE_SIZE, entry level 224 * and the translation table size (T0SZ). The variable "x" in the 225 * algorithm determines the alignment of a table base address at a given 226 * level and thus determines the alignment of VTTBR:BADDR for stage2 227 * page table entry level. 228 * Since the number of bits resolved at the entry level could vary 229 * depending on the T0SZ, the value of "x" is defined based on a 230 * Magic constant for a given PAGE_SIZE and Entry Level. The 231 * intermediate levels must be always aligned to the PAGE_SIZE (i.e, 232 * x = PAGE_SHIFT). 233 * 234 * The value of "x" for entry level is calculated as : 235 * x = Magic_N - T0SZ 236 * 237 * where Magic_N is an integer depending on the page size and the entry 238 * level of the page table as below: 239 * 240 * -------------------------------------------- 241 * | Entry level | 4K 16K 64K | 242 * -------------------------------------------- 243 * | Level: 0 (4 levels) | 28 | - | - | 244 * -------------------------------------------- 245 * | Level: 1 (3 levels) | 37 | 31 | 25 | 246 * -------------------------------------------- 247 * | Level: 2 (2 levels) | 46 | 42 | 38 | 248 * -------------------------------------------- 249 * | Level: 3 (1 level) | - | 53 | 51 | 250 * -------------------------------------------- 251 * 252 * We have a magic formula for the Magic_N below: 253 * 254 * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels) 255 * 256 * where Number_of_levels = (4 - Level). We are only interested in the 257 * value for Entry_Level for the stage2 page table. 258 * 259 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows: 260 * 261 * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT) 262 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels) 263 * 264 * Here is one way to explain the Magic Formula: 265 * 266 * x = log2(Size_of_Entry_Level_Table) 267 * 268 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another 269 * PAGE_SHIFT bits in the PTE, we have : 270 * 271 * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT) 272 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3 273 * where n = number of levels, and since each pointer is 8bytes, we have: 274 * 275 * x = Bits_Entry_Level + 3 276 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n 277 * 278 * The only constraint here is that, we have to find the number of page table 279 * levels for a given IPA size (which we do, see stage2_pt_levels()) 280 */ 281 #define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3))) 282 283 #define VTTBR_CNP_BIT (UL(1)) 284 #define VTTBR_VMID_SHIFT (UL(48)) 285 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) 286 287 /* Hyp System Trap Register */ 288 #define HSTR_EL2_T(x) (1 << x) 289 290 /* Hyp Coprocessor Trap Register Shifts */ 291 #define CPTR_EL2_TFP_SHIFT 10 292 293 /* Hyp Coprocessor Trap Register */ 294 #define CPTR_EL2_TCPAC (1U << 31) 295 #define CPTR_EL2_TAM (1 << 30) 296 #define CPTR_EL2_TTA (1 << 20) 297 #define CPTR_EL2_TSM (1 << 12) 298 #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT) 299 #define CPTR_EL2_TZ (1 << 8) 300 #define CPTR_NVHE_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */ 301 #define CPTR_NVHE_EL2_RES0 (GENMASK(63, 32) | \ 302 GENMASK(29, 21) | \ 303 GENMASK(19, 14) | \ 304 BIT(11)) 305 306 /* Hyp Debug Configuration Register bits */ 307 #define MDCR_EL2_E2TB_MASK (UL(0x3)) 308 #define MDCR_EL2_E2TB_SHIFT (UL(24)) 309 #define MDCR_EL2_HPMFZS (UL(1) << 36) 310 #define MDCR_EL2_HPMFZO (UL(1) << 29) 311 #define MDCR_EL2_MTPME (UL(1) << 28) 312 #define MDCR_EL2_TDCC (UL(1) << 27) 313 #define MDCR_EL2_HLP (UL(1) << 26) 314 #define MDCR_EL2_HCCD (UL(1) << 23) 315 #define MDCR_EL2_TTRF (UL(1) << 19) 316 #define MDCR_EL2_HPMD (UL(1) << 17) 317 #define MDCR_EL2_TPMS (UL(1) << 14) 318 #define MDCR_EL2_E2PB_MASK (UL(0x3)) 319 #define MDCR_EL2_E2PB_SHIFT (UL(12)) 320 #define MDCR_EL2_TDRA (UL(1) << 11) 321 #define MDCR_EL2_TDOSA (UL(1) << 10) 322 #define MDCR_EL2_TDA (UL(1) << 9) 323 #define MDCR_EL2_TDE (UL(1) << 8) 324 #define MDCR_EL2_HPME (UL(1) << 7) 325 #define MDCR_EL2_TPM (UL(1) << 6) 326 #define MDCR_EL2_TPMCR (UL(1) << 5) 327 #define MDCR_EL2_HPMN_MASK (UL(0x1F)) 328 #define MDCR_EL2_RES0 (GENMASK(63, 37) | \ 329 GENMASK(35, 30) | \ 330 GENMASK(25, 24) | \ 331 GENMASK(22, 20) | \ 332 BIT(18) | \ 333 GENMASK(16, 15)) 334 335 /* 336 * FGT register definitions 337 * 338 * RES0 and polarity masks as of DDI0487J.a, to be updated as needed. 339 * We're not using the generated masks as they are usually ahead of 340 * the published ARM ARM, which we use as a reference. 341 * 342 * Once we get to a point where the two describe the same thing, we'll 343 * merge the definitions. One day. 344 */ 345 #define __HFGRTR_EL2_RES0 (GENMASK(63, 56) | GENMASK(53, 51)) 346 #define __HFGRTR_EL2_MASK GENMASK(49, 0) 347 #define __HFGRTR_EL2_nMASK (GENMASK(58, 57) | GENMASK(55, 54) | BIT(50)) 348 349 #define __HFGWTR_EL2_RES0 (GENMASK(63, 56) | GENMASK(53, 51) | \ 350 BIT(46) | BIT(42) | BIT(40) | BIT(28) | \ 351 GENMASK(26, 25) | BIT(21) | BIT(18) | \ 352 GENMASK(15, 14) | GENMASK(10, 9) | BIT(2)) 353 #define __HFGWTR_EL2_MASK GENMASK(49, 0) 354 #define __HFGWTR_EL2_nMASK (GENMASK(58, 57) | GENMASK(55, 54) | BIT(50)) 355 356 #define __HFGITR_EL2_RES0 GENMASK(63, 57) 357 #define __HFGITR_EL2_MASK GENMASK(54, 0) 358 #define __HFGITR_EL2_nMASK GENMASK(56, 55) 359 360 #define __HDFGRTR_EL2_RES0 (BIT(49) | BIT(42) | GENMASK(39, 38) | \ 361 GENMASK(21, 20) | BIT(8)) 362 #define __HDFGRTR_EL2_MASK ~__HDFGRTR_EL2_nMASK 363 #define __HDFGRTR_EL2_nMASK GENMASK(62, 59) 364 365 #define __HDFGWTR_EL2_RES0 (BIT(63) | GENMASK(59, 58) | BIT(51) | BIT(47) | \ 366 BIT(43) | GENMASK(40, 38) | BIT(34) | BIT(30) | \ 367 BIT(22) | BIT(9) | BIT(6)) 368 #define __HDFGWTR_EL2_MASK ~__HDFGWTR_EL2_nMASK 369 #define __HDFGWTR_EL2_nMASK GENMASK(62, 60) 370 371 /* Similar definitions for HCRX_EL2 */ 372 #define __HCRX_EL2_RES0 (GENMASK(63, 16) | GENMASK(13, 12)) 373 #define __HCRX_EL2_MASK (0) 374 #define __HCRX_EL2_nMASK (GENMASK(15, 14) | GENMASK(4, 0)) 375 376 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ 377 #define HPFAR_MASK (~UL(0xf)) 378 /* 379 * We have 380 * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12] 381 * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12] 382 * 383 * Always assume 52 bit PA since at this point, we don't know how many PA bits 384 * the page table has been set up for. This should be safe since unused address 385 * bits in PAR are res0. 386 */ 387 #define PAR_TO_HPFAR(par) \ 388 (((par) & GENMASK_ULL(52 - 1, 12)) >> 8) 389 390 #define ECN(x) { ESR_ELx_EC_##x, #x } 391 392 #define kvm_arm_exception_class \ 393 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \ 394 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \ 395 ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \ 396 ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \ 397 ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \ 398 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \ 399 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \ 400 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \ 401 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64), ECN(ERET) 402 403 #define CPACR_EL1_TTA (1 << 28) 404 405 #define kvm_mode_names \ 406 { PSR_MODE_EL0t, "EL0t" }, \ 407 { PSR_MODE_EL1t, "EL1t" }, \ 408 { PSR_MODE_EL1h, "EL1h" }, \ 409 { PSR_MODE_EL2t, "EL2t" }, \ 410 { PSR_MODE_EL2h, "EL2h" }, \ 411 { PSR_MODE_EL3t, "EL3t" }, \ 412 { PSR_MODE_EL3h, "EL3h" }, \ 413 { PSR_AA32_MODE_USR, "32-bit USR" }, \ 414 { PSR_AA32_MODE_FIQ, "32-bit FIQ" }, \ 415 { PSR_AA32_MODE_IRQ, "32-bit IRQ" }, \ 416 { PSR_AA32_MODE_SVC, "32-bit SVC" }, \ 417 { PSR_AA32_MODE_ABT, "32-bit ABT" }, \ 418 { PSR_AA32_MODE_HYP, "32-bit HYP" }, \ 419 { PSR_AA32_MODE_UND, "32-bit UND" }, \ 420 { PSR_AA32_MODE_SYS, "32-bit SYS" } 421 422 #endif /* __ARM64_KVM_ARM_H__ */ 423