1 /* 2 * Copyright (C) 2012,2013 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __ARM64_KVM_ARM_H__ 19 #define __ARM64_KVM_ARM_H__ 20 21 #include <asm/esr.h> 22 #include <asm/memory.h> 23 #include <asm/types.h> 24 25 /* Hyp Configuration Register (HCR) bits */ 26 #define HCR_E2H (UL(1) << 34) 27 #define HCR_ID (UL(1) << 33) 28 #define HCR_CD (UL(1) << 32) 29 #define HCR_RW_SHIFT 31 30 #define HCR_RW (UL(1) << HCR_RW_SHIFT) 31 #define HCR_TRVM (UL(1) << 30) 32 #define HCR_HCD (UL(1) << 29) 33 #define HCR_TDZ (UL(1) << 28) 34 #define HCR_TGE (UL(1) << 27) 35 #define HCR_TVM (UL(1) << 26) 36 #define HCR_TTLB (UL(1) << 25) 37 #define HCR_TPU (UL(1) << 24) 38 #define HCR_TPC (UL(1) << 23) 39 #define HCR_TSW (UL(1) << 22) 40 #define HCR_TAC (UL(1) << 21) 41 #define HCR_TIDCP (UL(1) << 20) 42 #define HCR_TSC (UL(1) << 19) 43 #define HCR_TID3 (UL(1) << 18) 44 #define HCR_TID2 (UL(1) << 17) 45 #define HCR_TID1 (UL(1) << 16) 46 #define HCR_TID0 (UL(1) << 15) 47 #define HCR_TWE (UL(1) << 14) 48 #define HCR_TWI (UL(1) << 13) 49 #define HCR_DC (UL(1) << 12) 50 #define HCR_BSU (3 << 10) 51 #define HCR_BSU_IS (UL(1) << 10) 52 #define HCR_FB (UL(1) << 9) 53 #define HCR_VA (UL(1) << 8) 54 #define HCR_VI (UL(1) << 7) 55 #define HCR_VF (UL(1) << 6) 56 #define HCR_AMO (UL(1) << 5) 57 #define HCR_IMO (UL(1) << 4) 58 #define HCR_FMO (UL(1) << 3) 59 #define HCR_PTW (UL(1) << 2) 60 #define HCR_SWIO (UL(1) << 1) 61 #define HCR_VM (UL(1) << 0) 62 63 /* 64 * The bits we set in HCR: 65 * RW: 64bit by default, can be overridden for 32bit VMs 66 * TAC: Trap ACTLR 67 * TSC: Trap SMC 68 * TVM: Trap VM ops (until M+C set in SCTLR_EL1) 69 * TSW: Trap cache operations by set/way 70 * TWE: Trap WFE 71 * TWI: Trap WFI 72 * TIDCP: Trap L2CTLR/L2ECTLR 73 * BSU_IS: Upgrade barriers to the inner shareable domain 74 * FB: Force broadcast of all maintainance operations 75 * AMO: Override CPSR.A and enable signaling with VA 76 * IMO: Override CPSR.I and enable signaling with VI 77 * FMO: Override CPSR.F and enable signaling with VF 78 * SWIO: Turn set/way invalidates into set/way clean+invalidate 79 */ 80 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ 81 HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \ 82 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW) 83 #define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF) 84 #define HCR_INT_OVERRIDE (HCR_FMO | HCR_IMO) 85 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) 86 87 /* Hyp System Control Register (SCTLR_EL2) bits */ 88 #define SCTLR_EL2_EE (1 << 25) 89 #define SCTLR_EL2_WXN (1 << 19) 90 #define SCTLR_EL2_I (1 << 12) 91 #define SCTLR_EL2_SA (1 << 3) 92 #define SCTLR_EL2_C (1 << 2) 93 #define SCTLR_EL2_A (1 << 1) 94 #define SCTLR_EL2_M 1 95 #define SCTLR_EL2_FLAGS (SCTLR_EL2_M | SCTLR_EL2_A | SCTLR_EL2_C | \ 96 SCTLR_EL2_SA | SCTLR_EL2_I) 97 98 /* TCR_EL2 Registers bits */ 99 #define TCR_EL2_RES1 ((1 << 31) | (1 << 23)) 100 #define TCR_EL2_TBI (1 << 20) 101 #define TCR_EL2_PS (7 << 16) 102 #define TCR_EL2_PS_40B (2 << 16) 103 #define TCR_EL2_TG0 (1 << 14) 104 #define TCR_EL2_SH0 (3 << 12) 105 #define TCR_EL2_ORGN0 (3 << 10) 106 #define TCR_EL2_IRGN0 (3 << 8) 107 #define TCR_EL2_T0SZ 0x3f 108 #define TCR_EL2_MASK (TCR_EL2_TG0 | TCR_EL2_SH0 | \ 109 TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ) 110 111 /* VTCR_EL2 Registers bits */ 112 #define VTCR_EL2_RES1 (1 << 31) 113 #define VTCR_EL2_PS_MASK (7 << 16) 114 #define VTCR_EL2_TG0_MASK (1 << 14) 115 #define VTCR_EL2_TG0_4K (0 << 14) 116 #define VTCR_EL2_TG0_64K (1 << 14) 117 #define VTCR_EL2_SH0_MASK (3 << 12) 118 #define VTCR_EL2_SH0_INNER (3 << 12) 119 #define VTCR_EL2_ORGN0_MASK (3 << 10) 120 #define VTCR_EL2_ORGN0_WBWA (1 << 10) 121 #define VTCR_EL2_IRGN0_MASK (3 << 8) 122 #define VTCR_EL2_IRGN0_WBWA (1 << 8) 123 #define VTCR_EL2_SL0_MASK (3 << 6) 124 #define VTCR_EL2_SL0_LVL1 (1 << 6) 125 #define VTCR_EL2_T0SZ_MASK 0x3f 126 #define VTCR_EL2_T0SZ_40B 24 127 #define VTCR_EL2_VS_SHIFT 19 128 #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT) 129 #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT) 130 131 /* 132 * We configure the Stage-2 page tables to always restrict the IPA space to be 133 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are 134 * not known to exist and will break with this configuration. 135 * 136 * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time 137 * (see hyp-init.S). 138 * 139 * Note that when using 4K pages, we concatenate two first level page tables 140 * together. 141 * 142 * The magic numbers used for VTTBR_X in this patch can be found in Tables 143 * D4-23 and D4-25 in ARM DDI 0487A.b. 144 */ 145 #ifdef CONFIG_ARM64_64K_PAGES 146 /* 147 * Stage2 translation configuration: 148 * 40bits input (T0SZ = 24) 149 * 64kB pages (TG0 = 1) 150 * 2 level page tables (SL = 1) 151 */ 152 #define VTCR_EL2_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \ 153 VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ 154 VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B | \ 155 VTCR_EL2_RES1) 156 #define VTTBR_X (38 - VTCR_EL2_T0SZ_40B) 157 #else 158 /* 159 * Stage2 translation configuration: 160 * 40bits input (T0SZ = 24) 161 * 4kB pages (TG0 = 0) 162 * 3 level page tables (SL = 1) 163 */ 164 #define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \ 165 VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ 166 VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B | \ 167 VTCR_EL2_RES1) 168 #define VTTBR_X (37 - VTCR_EL2_T0SZ_40B) 169 #endif 170 171 #define VTTBR_BADDR_SHIFT (VTTBR_X - 1) 172 #define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT) 173 #define VTTBR_VMID_SHIFT (UL(48)) 174 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) 175 176 /* Hyp System Trap Register */ 177 #define HSTR_EL2_T(x) (1 << x) 178 179 /* Hyp Coproccessor Trap Register Shifts */ 180 #define CPTR_EL2_TFP_SHIFT 10 181 182 /* Hyp Coprocessor Trap Register */ 183 #define CPTR_EL2_TCPAC (1 << 31) 184 #define CPTR_EL2_TTA (1 << 20) 185 #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT) 186 #define CPTR_EL2_DEFAULT 0x000033ff 187 188 /* Hyp Debug Configuration Register bits */ 189 #define MDCR_EL2_TDRA (1 << 11) 190 #define MDCR_EL2_TDOSA (1 << 10) 191 #define MDCR_EL2_TDA (1 << 9) 192 #define MDCR_EL2_TDE (1 << 8) 193 #define MDCR_EL2_HPME (1 << 7) 194 #define MDCR_EL2_TPM (1 << 6) 195 #define MDCR_EL2_TPMCR (1 << 5) 196 #define MDCR_EL2_HPMN_MASK (0x1F) 197 198 /* For compatibility with fault code shared with 32-bit */ 199 #define FSC_FAULT ESR_ELx_FSC_FAULT 200 #define FSC_ACCESS ESR_ELx_FSC_ACCESS 201 #define FSC_PERM ESR_ELx_FSC_PERM 202 203 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ 204 #define HPFAR_MASK (~UL(0xf)) 205 206 #define kvm_arm_exception_type \ 207 {0, "IRQ" }, \ 208 {1, "TRAP" } 209 210 #define ECN(x) { ESR_ELx_EC_##x, #x } 211 212 #define kvm_arm_exception_class \ 213 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \ 214 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \ 215 ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \ 216 ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \ 217 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \ 218 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \ 219 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \ 220 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64) 221 222 #define CPACR_EL1_FPEN (3 << 20) 223 #define CPACR_EL1_TTA (1 << 28) 224 225 #endif /* __ARM64_KVM_ARM_H__ */ 226