1 /* 2 * Based on arch/arm/include/asm/io.h 3 * 4 * Copyright (C) 1996-2000 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASM_IO_H 20 #define __ASM_IO_H 21 22 #ifdef __KERNEL__ 23 24 #include <linux/types.h> 25 26 #include <asm/byteorder.h> 27 #include <asm/barrier.h> 28 #include <asm/memory.h> 29 #include <asm/pgtable.h> 30 #include <asm/early_ioremap.h> 31 #include <asm/alternative.h> 32 #include <asm/cpufeature.h> 33 34 /* 35 * Generic IO read/write. These perform native-endian accesses. 36 */ 37 #define __raw_writeb __raw_writeb 38 static inline void __raw_writeb(u8 val, volatile void __iomem *addr) 39 { 40 asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr)); 41 } 42 43 #define __raw_writew __raw_writew 44 static inline void __raw_writew(u16 val, volatile void __iomem *addr) 45 { 46 asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr)); 47 } 48 49 #define __raw_writel __raw_writel 50 static inline void __raw_writel(u32 val, volatile void __iomem *addr) 51 { 52 asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr)); 53 } 54 55 #define __raw_writeq __raw_writeq 56 static inline void __raw_writeq(u64 val, volatile void __iomem *addr) 57 { 58 asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr)); 59 } 60 61 #define __raw_readb __raw_readb 62 static inline u8 __raw_readb(const volatile void __iomem *addr) 63 { 64 u8 val; 65 asm volatile(ALTERNATIVE("ldrb %w0, [%1]", 66 "ldarb %w0, [%1]", 67 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) 68 : "=r" (val) : "r" (addr)); 69 return val; 70 } 71 72 #define __raw_readw __raw_readw 73 static inline u16 __raw_readw(const volatile void __iomem *addr) 74 { 75 u16 val; 76 77 asm volatile(ALTERNATIVE("ldrh %w0, [%1]", 78 "ldarh %w0, [%1]", 79 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) 80 : "=r" (val) : "r" (addr)); 81 return val; 82 } 83 84 #define __raw_readl __raw_readl 85 static inline u32 __raw_readl(const volatile void __iomem *addr) 86 { 87 u32 val; 88 asm volatile(ALTERNATIVE("ldr %w0, [%1]", 89 "ldar %w0, [%1]", 90 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) 91 : "=r" (val) : "r" (addr)); 92 return val; 93 } 94 95 #define __raw_readq __raw_readq 96 static inline u64 __raw_readq(const volatile void __iomem *addr) 97 { 98 u64 val; 99 asm volatile(ALTERNATIVE("ldr %0, [%1]", 100 "ldar %0, [%1]", 101 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) 102 : "=r" (val) : "r" (addr)); 103 return val; 104 } 105 106 /* IO barriers */ 107 #define __iormb(v) \ 108 ({ \ 109 unsigned long tmp; \ 110 \ 111 rmb(); \ 112 \ 113 /* \ 114 * Create a dummy control dependency from the IO read to any \ 115 * later instructions. This ensures that a subsequent call to \ 116 * udelay() will be ordered due to the ISB in get_cycles(). \ 117 */ \ 118 asm volatile("eor %0, %1, %1\n" \ 119 "cbnz %0, ." \ 120 : "=r" (tmp) : "r" ((unsigned long)(v)) \ 121 : "memory"); \ 122 }) 123 124 #define __io_par(v) __iormb(v) 125 #define __iowmb() wmb() 126 127 #define mmiowb() do { } while (0) 128 129 /* 130 * Relaxed I/O memory access primitives. These follow the Device memory 131 * ordering rules but do not guarantee any ordering relative to Normal memory 132 * accesses. 133 */ 134 #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) 135 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) 136 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) 137 #define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) 138 139 #define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c))) 140 #define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) 141 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) 142 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) 143 144 /* 145 * I/O memory access primitives. Reads are ordered relative to any 146 * following Normal memory access. Writes are ordered relative to any prior 147 * Normal memory access. 148 */ 149 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(__v); __v; }) 150 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(__v); __v; }) 151 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; }) 152 #define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(__v); __v; }) 153 154 #define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); }) 155 #define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); }) 156 #define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); }) 157 #define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); }) 158 159 /* 160 * I/O port access primitives. 161 */ 162 #define arch_has_dev_port() (1) 163 #define IO_SPACE_LIMIT (PCI_IO_SIZE - 1) 164 #define PCI_IOBASE ((void __iomem *)PCI_IO_START) 165 166 /* 167 * String version of I/O memory access operations. 168 */ 169 extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t); 170 extern void __memcpy_toio(volatile void __iomem *, const void *, size_t); 171 extern void __memset_io(volatile void __iomem *, int, size_t); 172 173 #define memset_io(c,v,l) __memset_io((c),(v),(l)) 174 #define memcpy_fromio(a,c,l) __memcpy_fromio((a),(c),(l)) 175 #define memcpy_toio(c,a,l) __memcpy_toio((c),(a),(l)) 176 177 /* 178 * I/O memory mapping functions. 179 */ 180 extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot); 181 extern void __iounmap(volatile void __iomem *addr); 182 extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); 183 184 #define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) 185 #define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) 186 #define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC)) 187 #define ioremap_wt(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) 188 #define iounmap __iounmap 189 190 /* 191 * PCI configuration space mapping function. 192 * 193 * The PCI specification disallows posted write configuration transactions. 194 * Add an arch specific pci_remap_cfgspace() definition that is implemented 195 * through nGnRnE device memory attribute as recommended by the ARM v8 196 * Architecture reference manual Issue A.k B2.8.2 "Device memory". 197 */ 198 #define pci_remap_cfgspace(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRnE)) 199 200 /* 201 * io{read,write}{16,32,64}be() macros 202 */ 203 #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __v; }) 204 #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; }) 205 #define ioread64be(p) ({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; }) 206 207 #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); }) 208 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); }) 209 #define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); }) 210 211 #include <asm-generic/io.h> 212 213 /* 214 * More restrictive address range checking than the default implementation 215 * (PHYS_OFFSET and PHYS_MASK taken into account). 216 */ 217 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 218 extern int valid_phys_addr_range(phys_addr_t addr, size_t size); 219 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 220 221 extern int devmem_is_allowed(unsigned long pfn); 222 223 #endif /* __KERNEL__ */ 224 #endif /* __ASM_IO_H */ 225