xref: /openbmc/linux/arch/arm64/include/asm/insn.h (revision fc062ad8)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Huawei Ltd.
4  * Author: Jiang Liu <liuj97@gmail.com>
5  *
6  * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
7  */
8 #ifndef	__ASM_INSN_H
9 #define	__ASM_INSN_H
10 #include <linux/build_bug.h>
11 #include <linux/types.h>
12 
13 #include <asm/insn-def.h>
14 
15 #ifndef __ASSEMBLY__
16 /*
17  * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
18  * Section C3.1 "A64 instruction index by encoding":
19  * AArch64 main encoding table
20  *  Bit position
21  *   28 27 26 25	Encoding Group
22  *   0  0  -  -		Unallocated
23  *   1  0  0  -		Data processing, immediate
24  *   1  0  1  -		Branch, exception generation and system instructions
25  *   -  1  -  0		Loads and stores
26  *   -  1  0  1		Data processing - register
27  *   0  1  1  1		Data processing - SIMD and floating point
28  *   1  1  1  1		Data processing - SIMD and floating point
29  * "-" means "don't care"
30  */
31 enum aarch64_insn_encoding_class {
32 	AARCH64_INSN_CLS_UNKNOWN,	/* UNALLOCATED */
33 	AARCH64_INSN_CLS_SVE,		/* SVE instructions */
34 	AARCH64_INSN_CLS_DP_IMM,	/* Data processing - immediate */
35 	AARCH64_INSN_CLS_DP_REG,	/* Data processing - register */
36 	AARCH64_INSN_CLS_DP_FPSIMD,	/* Data processing - SIMD and FP */
37 	AARCH64_INSN_CLS_LDST,		/* Loads and stores */
38 	AARCH64_INSN_CLS_BR_SYS,	/* Branch, exception generation and
39 					 * system instructions */
40 };
41 
42 enum aarch64_insn_hint_cr_op {
43 	AARCH64_INSN_HINT_NOP	= 0x0 << 5,
44 	AARCH64_INSN_HINT_YIELD	= 0x1 << 5,
45 	AARCH64_INSN_HINT_WFE	= 0x2 << 5,
46 	AARCH64_INSN_HINT_WFI	= 0x3 << 5,
47 	AARCH64_INSN_HINT_SEV	= 0x4 << 5,
48 	AARCH64_INSN_HINT_SEVL	= 0x5 << 5,
49 
50 	AARCH64_INSN_HINT_XPACLRI    = 0x07 << 5,
51 	AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
52 	AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
53 	AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
54 	AARCH64_INSN_HINT_AUTIB_1716 = 0x0E << 5,
55 	AARCH64_INSN_HINT_PACIAZ     = 0x18 << 5,
56 	AARCH64_INSN_HINT_PACIASP    = 0x19 << 5,
57 	AARCH64_INSN_HINT_PACIBZ     = 0x1A << 5,
58 	AARCH64_INSN_HINT_PACIBSP    = 0x1B << 5,
59 	AARCH64_INSN_HINT_AUTIAZ     = 0x1C << 5,
60 	AARCH64_INSN_HINT_AUTIASP    = 0x1D << 5,
61 	AARCH64_INSN_HINT_AUTIBZ     = 0x1E << 5,
62 	AARCH64_INSN_HINT_AUTIBSP    = 0x1F << 5,
63 
64 	AARCH64_INSN_HINT_ESB  = 0x10 << 5,
65 	AARCH64_INSN_HINT_PSB  = 0x11 << 5,
66 	AARCH64_INSN_HINT_TSB  = 0x12 << 5,
67 	AARCH64_INSN_HINT_CSDB = 0x14 << 5,
68 
69 	AARCH64_INSN_HINT_BTI   = 0x20 << 5,
70 	AARCH64_INSN_HINT_BTIC  = 0x22 << 5,
71 	AARCH64_INSN_HINT_BTIJ  = 0x24 << 5,
72 	AARCH64_INSN_HINT_BTIJC = 0x26 << 5,
73 };
74 
75 enum aarch64_insn_imm_type {
76 	AARCH64_INSN_IMM_ADR,
77 	AARCH64_INSN_IMM_26,
78 	AARCH64_INSN_IMM_19,
79 	AARCH64_INSN_IMM_16,
80 	AARCH64_INSN_IMM_14,
81 	AARCH64_INSN_IMM_12,
82 	AARCH64_INSN_IMM_9,
83 	AARCH64_INSN_IMM_7,
84 	AARCH64_INSN_IMM_6,
85 	AARCH64_INSN_IMM_S,
86 	AARCH64_INSN_IMM_R,
87 	AARCH64_INSN_IMM_N,
88 	AARCH64_INSN_IMM_MAX
89 };
90 
91 enum aarch64_insn_register_type {
92 	AARCH64_INSN_REGTYPE_RT,
93 	AARCH64_INSN_REGTYPE_RN,
94 	AARCH64_INSN_REGTYPE_RT2,
95 	AARCH64_INSN_REGTYPE_RM,
96 	AARCH64_INSN_REGTYPE_RD,
97 	AARCH64_INSN_REGTYPE_RA,
98 	AARCH64_INSN_REGTYPE_RS,
99 };
100 
101 enum aarch64_insn_register {
102 	AARCH64_INSN_REG_0  = 0,
103 	AARCH64_INSN_REG_1  = 1,
104 	AARCH64_INSN_REG_2  = 2,
105 	AARCH64_INSN_REG_3  = 3,
106 	AARCH64_INSN_REG_4  = 4,
107 	AARCH64_INSN_REG_5  = 5,
108 	AARCH64_INSN_REG_6  = 6,
109 	AARCH64_INSN_REG_7  = 7,
110 	AARCH64_INSN_REG_8  = 8,
111 	AARCH64_INSN_REG_9  = 9,
112 	AARCH64_INSN_REG_10 = 10,
113 	AARCH64_INSN_REG_11 = 11,
114 	AARCH64_INSN_REG_12 = 12,
115 	AARCH64_INSN_REG_13 = 13,
116 	AARCH64_INSN_REG_14 = 14,
117 	AARCH64_INSN_REG_15 = 15,
118 	AARCH64_INSN_REG_16 = 16,
119 	AARCH64_INSN_REG_17 = 17,
120 	AARCH64_INSN_REG_18 = 18,
121 	AARCH64_INSN_REG_19 = 19,
122 	AARCH64_INSN_REG_20 = 20,
123 	AARCH64_INSN_REG_21 = 21,
124 	AARCH64_INSN_REG_22 = 22,
125 	AARCH64_INSN_REG_23 = 23,
126 	AARCH64_INSN_REG_24 = 24,
127 	AARCH64_INSN_REG_25 = 25,
128 	AARCH64_INSN_REG_26 = 26,
129 	AARCH64_INSN_REG_27 = 27,
130 	AARCH64_INSN_REG_28 = 28,
131 	AARCH64_INSN_REG_29 = 29,
132 	AARCH64_INSN_REG_FP = 29, /* Frame pointer */
133 	AARCH64_INSN_REG_30 = 30,
134 	AARCH64_INSN_REG_LR = 30, /* Link register */
135 	AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
136 	AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
137 };
138 
139 enum aarch64_insn_special_register {
140 	AARCH64_INSN_SPCLREG_SPSR_EL1	= 0xC200,
141 	AARCH64_INSN_SPCLREG_ELR_EL1	= 0xC201,
142 	AARCH64_INSN_SPCLREG_SP_EL0	= 0xC208,
143 	AARCH64_INSN_SPCLREG_SPSEL	= 0xC210,
144 	AARCH64_INSN_SPCLREG_CURRENTEL	= 0xC212,
145 	AARCH64_INSN_SPCLREG_DAIF	= 0xDA11,
146 	AARCH64_INSN_SPCLREG_NZCV	= 0xDA10,
147 	AARCH64_INSN_SPCLREG_FPCR	= 0xDA20,
148 	AARCH64_INSN_SPCLREG_DSPSR_EL0	= 0xDA28,
149 	AARCH64_INSN_SPCLREG_DLR_EL0	= 0xDA29,
150 	AARCH64_INSN_SPCLREG_SPSR_EL2	= 0xE200,
151 	AARCH64_INSN_SPCLREG_ELR_EL2	= 0xE201,
152 	AARCH64_INSN_SPCLREG_SP_EL1	= 0xE208,
153 	AARCH64_INSN_SPCLREG_SPSR_INQ	= 0xE218,
154 	AARCH64_INSN_SPCLREG_SPSR_ABT	= 0xE219,
155 	AARCH64_INSN_SPCLREG_SPSR_UND	= 0xE21A,
156 	AARCH64_INSN_SPCLREG_SPSR_FIQ	= 0xE21B,
157 	AARCH64_INSN_SPCLREG_SPSR_EL3	= 0xF200,
158 	AARCH64_INSN_SPCLREG_ELR_EL3	= 0xF201,
159 	AARCH64_INSN_SPCLREG_SP_EL2	= 0xF210
160 };
161 
162 enum aarch64_insn_variant {
163 	AARCH64_INSN_VARIANT_32BIT,
164 	AARCH64_INSN_VARIANT_64BIT
165 };
166 
167 enum aarch64_insn_condition {
168 	AARCH64_INSN_COND_EQ = 0x0, /* == */
169 	AARCH64_INSN_COND_NE = 0x1, /* != */
170 	AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
171 	AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
172 	AARCH64_INSN_COND_MI = 0x4, /* < 0 */
173 	AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
174 	AARCH64_INSN_COND_VS = 0x6, /* overflow */
175 	AARCH64_INSN_COND_VC = 0x7, /* no overflow */
176 	AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
177 	AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
178 	AARCH64_INSN_COND_GE = 0xa, /* signed >= */
179 	AARCH64_INSN_COND_LT = 0xb, /* signed < */
180 	AARCH64_INSN_COND_GT = 0xc, /* signed > */
181 	AARCH64_INSN_COND_LE = 0xd, /* signed <= */
182 	AARCH64_INSN_COND_AL = 0xe, /* always */
183 };
184 
185 enum aarch64_insn_branch_type {
186 	AARCH64_INSN_BRANCH_NOLINK,
187 	AARCH64_INSN_BRANCH_LINK,
188 	AARCH64_INSN_BRANCH_RETURN,
189 	AARCH64_INSN_BRANCH_COMP_ZERO,
190 	AARCH64_INSN_BRANCH_COMP_NONZERO,
191 };
192 
193 enum aarch64_insn_size_type {
194 	AARCH64_INSN_SIZE_8,
195 	AARCH64_INSN_SIZE_16,
196 	AARCH64_INSN_SIZE_32,
197 	AARCH64_INSN_SIZE_64,
198 };
199 
200 enum aarch64_insn_ldst_type {
201 	AARCH64_INSN_LDST_LOAD_REG_OFFSET,
202 	AARCH64_INSN_LDST_STORE_REG_OFFSET,
203 	AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
204 	AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
205 	AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
206 	AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
207 	AARCH64_INSN_LDST_LOAD_EX,
208 	AARCH64_INSN_LDST_STORE_EX,
209 };
210 
211 enum aarch64_insn_adsb_type {
212 	AARCH64_INSN_ADSB_ADD,
213 	AARCH64_INSN_ADSB_SUB,
214 	AARCH64_INSN_ADSB_ADD_SETFLAGS,
215 	AARCH64_INSN_ADSB_SUB_SETFLAGS
216 };
217 
218 enum aarch64_insn_movewide_type {
219 	AARCH64_INSN_MOVEWIDE_ZERO,
220 	AARCH64_INSN_MOVEWIDE_KEEP,
221 	AARCH64_INSN_MOVEWIDE_INVERSE
222 };
223 
224 enum aarch64_insn_bitfield_type {
225 	AARCH64_INSN_BITFIELD_MOVE,
226 	AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
227 	AARCH64_INSN_BITFIELD_MOVE_SIGNED
228 };
229 
230 enum aarch64_insn_data1_type {
231 	AARCH64_INSN_DATA1_REVERSE_16,
232 	AARCH64_INSN_DATA1_REVERSE_32,
233 	AARCH64_INSN_DATA1_REVERSE_64,
234 };
235 
236 enum aarch64_insn_data2_type {
237 	AARCH64_INSN_DATA2_UDIV,
238 	AARCH64_INSN_DATA2_SDIV,
239 	AARCH64_INSN_DATA2_LSLV,
240 	AARCH64_INSN_DATA2_LSRV,
241 	AARCH64_INSN_DATA2_ASRV,
242 	AARCH64_INSN_DATA2_RORV,
243 };
244 
245 enum aarch64_insn_data3_type {
246 	AARCH64_INSN_DATA3_MADD,
247 	AARCH64_INSN_DATA3_MSUB,
248 };
249 
250 enum aarch64_insn_logic_type {
251 	AARCH64_INSN_LOGIC_AND,
252 	AARCH64_INSN_LOGIC_BIC,
253 	AARCH64_INSN_LOGIC_ORR,
254 	AARCH64_INSN_LOGIC_ORN,
255 	AARCH64_INSN_LOGIC_EOR,
256 	AARCH64_INSN_LOGIC_EON,
257 	AARCH64_INSN_LOGIC_AND_SETFLAGS,
258 	AARCH64_INSN_LOGIC_BIC_SETFLAGS
259 };
260 
261 enum aarch64_insn_prfm_type {
262 	AARCH64_INSN_PRFM_TYPE_PLD,
263 	AARCH64_INSN_PRFM_TYPE_PLI,
264 	AARCH64_INSN_PRFM_TYPE_PST,
265 };
266 
267 enum aarch64_insn_prfm_target {
268 	AARCH64_INSN_PRFM_TARGET_L1,
269 	AARCH64_INSN_PRFM_TARGET_L2,
270 	AARCH64_INSN_PRFM_TARGET_L3,
271 };
272 
273 enum aarch64_insn_prfm_policy {
274 	AARCH64_INSN_PRFM_POLICY_KEEP,
275 	AARCH64_INSN_PRFM_POLICY_STRM,
276 };
277 
278 enum aarch64_insn_adr_type {
279 	AARCH64_INSN_ADR_TYPE_ADRP,
280 	AARCH64_INSN_ADR_TYPE_ADR,
281 };
282 
283 #define	__AARCH64_INSN_FUNCS(abbr, mask, val)				\
284 static __always_inline bool aarch64_insn_is_##abbr(u32 code)		\
285 {									\
286 	BUILD_BUG_ON(~(mask) & (val));					\
287 	return (code & (mask)) == (val);				\
288 }									\
289 static __always_inline u32 aarch64_insn_get_##abbr##_value(void)	\
290 {									\
291 	return (val);							\
292 }
293 
294 __AARCH64_INSN_FUNCS(adr,	0x9F000000, 0x10000000)
295 __AARCH64_INSN_FUNCS(adrp,	0x9F000000, 0x90000000)
296 __AARCH64_INSN_FUNCS(prfm,	0x3FC00000, 0x39800000)
297 __AARCH64_INSN_FUNCS(prfm_lit,	0xFF000000, 0xD8000000)
298 __AARCH64_INSN_FUNCS(store_imm,	0x3FC00000, 0x39000000)
299 __AARCH64_INSN_FUNCS(load_imm,	0x3FC00000, 0x39400000)
300 __AARCH64_INSN_FUNCS(store_pre,	0x3FE00C00, 0x38000C00)
301 __AARCH64_INSN_FUNCS(load_pre,	0x3FE00C00, 0x38400C00)
302 __AARCH64_INSN_FUNCS(store_post,	0x3FE00C00, 0x38000400)
303 __AARCH64_INSN_FUNCS(load_post,	0x3FE00C00, 0x38400400)
304 __AARCH64_INSN_FUNCS(str_reg,	0x3FE0EC00, 0x38206800)
305 __AARCH64_INSN_FUNCS(ldadd,	0x3F20FC00, 0x38200000)
306 __AARCH64_INSN_FUNCS(ldr_reg,	0x3FE0EC00, 0x38606800)
307 __AARCH64_INSN_FUNCS(ldr_lit,	0xBF000000, 0x18000000)
308 __AARCH64_INSN_FUNCS(ldrsw_lit,	0xFF000000, 0x98000000)
309 __AARCH64_INSN_FUNCS(exclusive,	0x3F800000, 0x08000000)
310 __AARCH64_INSN_FUNCS(load_ex,	0x3F400000, 0x08400000)
311 __AARCH64_INSN_FUNCS(store_ex,	0x3F400000, 0x08000000)
312 __AARCH64_INSN_FUNCS(stp,	0x7FC00000, 0x29000000)
313 __AARCH64_INSN_FUNCS(ldp,	0x7FC00000, 0x29400000)
314 __AARCH64_INSN_FUNCS(stp_post,	0x7FC00000, 0x28800000)
315 __AARCH64_INSN_FUNCS(ldp_post,	0x7FC00000, 0x28C00000)
316 __AARCH64_INSN_FUNCS(stp_pre,	0x7FC00000, 0x29800000)
317 __AARCH64_INSN_FUNCS(ldp_pre,	0x7FC00000, 0x29C00000)
318 __AARCH64_INSN_FUNCS(add_imm,	0x7F000000, 0x11000000)
319 __AARCH64_INSN_FUNCS(adds_imm,	0x7F000000, 0x31000000)
320 __AARCH64_INSN_FUNCS(sub_imm,	0x7F000000, 0x51000000)
321 __AARCH64_INSN_FUNCS(subs_imm,	0x7F000000, 0x71000000)
322 __AARCH64_INSN_FUNCS(movn,	0x7F800000, 0x12800000)
323 __AARCH64_INSN_FUNCS(sbfm,	0x7F800000, 0x13000000)
324 __AARCH64_INSN_FUNCS(bfm,	0x7F800000, 0x33000000)
325 __AARCH64_INSN_FUNCS(movz,	0x7F800000, 0x52800000)
326 __AARCH64_INSN_FUNCS(ubfm,	0x7F800000, 0x53000000)
327 __AARCH64_INSN_FUNCS(movk,	0x7F800000, 0x72800000)
328 __AARCH64_INSN_FUNCS(add,	0x7F200000, 0x0B000000)
329 __AARCH64_INSN_FUNCS(adds,	0x7F200000, 0x2B000000)
330 __AARCH64_INSN_FUNCS(sub,	0x7F200000, 0x4B000000)
331 __AARCH64_INSN_FUNCS(subs,	0x7F200000, 0x6B000000)
332 __AARCH64_INSN_FUNCS(madd,	0x7FE08000, 0x1B000000)
333 __AARCH64_INSN_FUNCS(msub,	0x7FE08000, 0x1B008000)
334 __AARCH64_INSN_FUNCS(udiv,	0x7FE0FC00, 0x1AC00800)
335 __AARCH64_INSN_FUNCS(sdiv,	0x7FE0FC00, 0x1AC00C00)
336 __AARCH64_INSN_FUNCS(lslv,	0x7FE0FC00, 0x1AC02000)
337 __AARCH64_INSN_FUNCS(lsrv,	0x7FE0FC00, 0x1AC02400)
338 __AARCH64_INSN_FUNCS(asrv,	0x7FE0FC00, 0x1AC02800)
339 __AARCH64_INSN_FUNCS(rorv,	0x7FE0FC00, 0x1AC02C00)
340 __AARCH64_INSN_FUNCS(rev16,	0x7FFFFC00, 0x5AC00400)
341 __AARCH64_INSN_FUNCS(rev32,	0x7FFFFC00, 0x5AC00800)
342 __AARCH64_INSN_FUNCS(rev64,	0x7FFFFC00, 0x5AC00C00)
343 __AARCH64_INSN_FUNCS(and,	0x7F200000, 0x0A000000)
344 __AARCH64_INSN_FUNCS(bic,	0x7F200000, 0x0A200000)
345 __AARCH64_INSN_FUNCS(orr,	0x7F200000, 0x2A000000)
346 __AARCH64_INSN_FUNCS(mov_reg,	0x7FE0FFE0, 0x2A0003E0)
347 __AARCH64_INSN_FUNCS(orn,	0x7F200000, 0x2A200000)
348 __AARCH64_INSN_FUNCS(eor,	0x7F200000, 0x4A000000)
349 __AARCH64_INSN_FUNCS(eon,	0x7F200000, 0x4A200000)
350 __AARCH64_INSN_FUNCS(ands,	0x7F200000, 0x6A000000)
351 __AARCH64_INSN_FUNCS(bics,	0x7F200000, 0x6A200000)
352 __AARCH64_INSN_FUNCS(and_imm,	0x7F800000, 0x12000000)
353 __AARCH64_INSN_FUNCS(orr_imm,	0x7F800000, 0x32000000)
354 __AARCH64_INSN_FUNCS(eor_imm,	0x7F800000, 0x52000000)
355 __AARCH64_INSN_FUNCS(ands_imm,	0x7F800000, 0x72000000)
356 __AARCH64_INSN_FUNCS(extr,	0x7FA00000, 0x13800000)
357 __AARCH64_INSN_FUNCS(b,		0xFC000000, 0x14000000)
358 __AARCH64_INSN_FUNCS(bl,	0xFC000000, 0x94000000)
359 __AARCH64_INSN_FUNCS(cbz,	0x7F000000, 0x34000000)
360 __AARCH64_INSN_FUNCS(cbnz,	0x7F000000, 0x35000000)
361 __AARCH64_INSN_FUNCS(tbz,	0x7F000000, 0x36000000)
362 __AARCH64_INSN_FUNCS(tbnz,	0x7F000000, 0x37000000)
363 __AARCH64_INSN_FUNCS(bcond,	0xFF000010, 0x54000000)
364 __AARCH64_INSN_FUNCS(svc,	0xFFE0001F, 0xD4000001)
365 __AARCH64_INSN_FUNCS(hvc,	0xFFE0001F, 0xD4000002)
366 __AARCH64_INSN_FUNCS(smc,	0xFFE0001F, 0xD4000003)
367 __AARCH64_INSN_FUNCS(brk,	0xFFE0001F, 0xD4200000)
368 __AARCH64_INSN_FUNCS(exception,	0xFF000000, 0xD4000000)
369 __AARCH64_INSN_FUNCS(hint,	0xFFFFF01F, 0xD503201F)
370 __AARCH64_INSN_FUNCS(br,	0xFFFFFC1F, 0xD61F0000)
371 __AARCH64_INSN_FUNCS(br_auth,	0xFEFFF800, 0xD61F0800)
372 __AARCH64_INSN_FUNCS(blr,	0xFFFFFC1F, 0xD63F0000)
373 __AARCH64_INSN_FUNCS(blr_auth,	0xFEFFF800, 0xD63F0800)
374 __AARCH64_INSN_FUNCS(ret,	0xFFFFFC1F, 0xD65F0000)
375 __AARCH64_INSN_FUNCS(ret_auth,	0xFFFFFBFF, 0xD65F0BFF)
376 __AARCH64_INSN_FUNCS(eret,	0xFFFFFFFF, 0xD69F03E0)
377 __AARCH64_INSN_FUNCS(eret_auth,	0xFFFFFBFF, 0xD69F0BFF)
378 __AARCH64_INSN_FUNCS(mrs,	0xFFF00000, 0xD5300000)
379 __AARCH64_INSN_FUNCS(msr_imm,	0xFFF8F01F, 0xD500401F)
380 __AARCH64_INSN_FUNCS(msr_reg,	0xFFF00000, 0xD5100000)
381 __AARCH64_INSN_FUNCS(dmb,	0xFFFFF0FF, 0xD50330BF)
382 __AARCH64_INSN_FUNCS(dsb_base,	0xFFFFF0FF, 0xD503309F)
383 __AARCH64_INSN_FUNCS(dsb_nxs,	0xFFFFF3FF, 0xD503323F)
384 __AARCH64_INSN_FUNCS(isb,	0xFFFFF0FF, 0xD50330DF)
385 __AARCH64_INSN_FUNCS(sb,	0xFFFFFFFF, 0xD50330FF)
386 __AARCH64_INSN_FUNCS(clrex,	0xFFFFF0FF, 0xD503305F)
387 __AARCH64_INSN_FUNCS(ssbb,	0xFFFFFFFF, 0xD503309F)
388 __AARCH64_INSN_FUNCS(pssbb,	0xFFFFFFFF, 0xD503349F)
389 
390 #undef	__AARCH64_INSN_FUNCS
391 
392 bool aarch64_insn_is_steppable_hint(u32 insn);
393 bool aarch64_insn_is_branch_imm(u32 insn);
394 
395 static inline bool aarch64_insn_is_adr_adrp(u32 insn)
396 {
397 	return aarch64_insn_is_adr(insn) || aarch64_insn_is_adrp(insn);
398 }
399 
400 static inline bool aarch64_insn_is_dsb(u32 insn)
401 {
402 	return aarch64_insn_is_dsb_base(insn) || aarch64_insn_is_dsb_nxs(insn);
403 }
404 
405 static inline bool aarch64_insn_is_barrier(u32 insn)
406 {
407 	return aarch64_insn_is_dmb(insn) || aarch64_insn_is_dsb(insn) ||
408 	       aarch64_insn_is_isb(insn) || aarch64_insn_is_sb(insn) ||
409 	       aarch64_insn_is_clrex(insn) || aarch64_insn_is_ssbb(insn) ||
410 	       aarch64_insn_is_pssbb(insn);
411 }
412 
413 static inline bool aarch64_insn_is_store_single(u32 insn)
414 {
415 	return aarch64_insn_is_store_imm(insn) ||
416 	       aarch64_insn_is_store_pre(insn) ||
417 	       aarch64_insn_is_store_post(insn);
418 }
419 
420 static inline bool aarch64_insn_is_store_pair(u32 insn)
421 {
422 	return aarch64_insn_is_stp(insn) ||
423 	       aarch64_insn_is_stp_pre(insn) ||
424 	       aarch64_insn_is_stp_post(insn);
425 }
426 
427 static inline bool aarch64_insn_is_load_single(u32 insn)
428 {
429 	return aarch64_insn_is_load_imm(insn) ||
430 	       aarch64_insn_is_load_pre(insn) ||
431 	       aarch64_insn_is_load_post(insn);
432 }
433 
434 static inline bool aarch64_insn_is_load_pair(u32 insn)
435 {
436 	return aarch64_insn_is_ldp(insn) ||
437 	       aarch64_insn_is_ldp_pre(insn) ||
438 	       aarch64_insn_is_ldp_post(insn);
439 }
440 
441 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
442 bool aarch64_insn_uses_literal(u32 insn);
443 bool aarch64_insn_is_branch(u32 insn);
444 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
445 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
446 				  u32 insn, u64 imm);
447 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
448 					 u32 insn);
449 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
450 				enum aarch64_insn_branch_type type);
451 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
452 				     enum aarch64_insn_register reg,
453 				     enum aarch64_insn_variant variant,
454 				     enum aarch64_insn_branch_type type);
455 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
456 				     enum aarch64_insn_condition cond);
457 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op);
458 u32 aarch64_insn_gen_nop(void);
459 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
460 				enum aarch64_insn_branch_type type);
461 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
462 				    enum aarch64_insn_register base,
463 				    enum aarch64_insn_register offset,
464 				    enum aarch64_insn_size_type size,
465 				    enum aarch64_insn_ldst_type type);
466 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
467 				     enum aarch64_insn_register reg2,
468 				     enum aarch64_insn_register base,
469 				     int offset,
470 				     enum aarch64_insn_variant variant,
471 				     enum aarch64_insn_ldst_type type);
472 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
473 				   enum aarch64_insn_register base,
474 				   enum aarch64_insn_register state,
475 				   enum aarch64_insn_size_type size,
476 				   enum aarch64_insn_ldst_type type);
477 u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
478 			   enum aarch64_insn_register address,
479 			   enum aarch64_insn_register value,
480 			   enum aarch64_insn_size_type size);
481 u32 aarch64_insn_gen_stadd(enum aarch64_insn_register address,
482 			   enum aarch64_insn_register value,
483 			   enum aarch64_insn_size_type size);
484 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
485 				 enum aarch64_insn_register src,
486 				 int imm, enum aarch64_insn_variant variant,
487 				 enum aarch64_insn_adsb_type type);
488 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
489 			 enum aarch64_insn_register reg,
490 			 enum aarch64_insn_adr_type type);
491 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
492 			      enum aarch64_insn_register src,
493 			      int immr, int imms,
494 			      enum aarch64_insn_variant variant,
495 			      enum aarch64_insn_bitfield_type type);
496 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
497 			      int imm, int shift,
498 			      enum aarch64_insn_variant variant,
499 			      enum aarch64_insn_movewide_type type);
500 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
501 					 enum aarch64_insn_register src,
502 					 enum aarch64_insn_register reg,
503 					 int shift,
504 					 enum aarch64_insn_variant variant,
505 					 enum aarch64_insn_adsb_type type);
506 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
507 			   enum aarch64_insn_register src,
508 			   enum aarch64_insn_variant variant,
509 			   enum aarch64_insn_data1_type type);
510 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
511 			   enum aarch64_insn_register src,
512 			   enum aarch64_insn_register reg,
513 			   enum aarch64_insn_variant variant,
514 			   enum aarch64_insn_data2_type type);
515 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
516 			   enum aarch64_insn_register src,
517 			   enum aarch64_insn_register reg1,
518 			   enum aarch64_insn_register reg2,
519 			   enum aarch64_insn_variant variant,
520 			   enum aarch64_insn_data3_type type);
521 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
522 					 enum aarch64_insn_register src,
523 					 enum aarch64_insn_register reg,
524 					 int shift,
525 					 enum aarch64_insn_variant variant,
526 					 enum aarch64_insn_logic_type type);
527 u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,
528 			      enum aarch64_insn_register src,
529 			      enum aarch64_insn_variant variant);
530 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
531 				       enum aarch64_insn_variant variant,
532 				       enum aarch64_insn_register Rn,
533 				       enum aarch64_insn_register Rd,
534 				       u64 imm);
535 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
536 			  enum aarch64_insn_register Rm,
537 			  enum aarch64_insn_register Rn,
538 			  enum aarch64_insn_register Rd,
539 			  u8 lsb);
540 u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
541 			      enum aarch64_insn_prfm_type type,
542 			      enum aarch64_insn_prfm_target target,
543 			      enum aarch64_insn_prfm_policy policy);
544 s32 aarch64_get_branch_offset(u32 insn);
545 u32 aarch64_set_branch_offset(u32 insn, s32 offset);
546 
547 s32 aarch64_insn_adrp_get_offset(u32 insn);
548 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);
549 
550 bool aarch32_insn_is_wide(u32 insn);
551 
552 #define A32_RN_OFFSET	16
553 #define A32_RT_OFFSET	12
554 #define A32_RT2_OFFSET	 0
555 
556 u32 aarch64_insn_extract_system_reg(u32 insn);
557 u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
558 u32 aarch32_insn_mcr_extract_opc2(u32 insn);
559 u32 aarch32_insn_mcr_extract_crm(u32 insn);
560 
561 typedef bool (pstate_check_t)(unsigned long);
562 extern pstate_check_t * const aarch32_opcode_cond_checks[16];
563 
564 #endif /* __ASSEMBLY__ */
565 
566 #endif	/* __ASM_INSN_H */
567