xref: /openbmc/linux/arch/arm64/include/asm/insn.h (revision d2999e1b)
1 /*
2  * Copyright (C) 2013 Huawei Ltd.
3  * Author: Jiang Liu <liuj97@gmail.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17 #ifndef	__ASM_INSN_H
18 #define	__ASM_INSN_H
19 #include <linux/types.h>
20 
21 /* A64 instructions are always 32 bits. */
22 #define	AARCH64_INSN_SIZE		4
23 
24 #ifndef __ASSEMBLY__
25 /*
26  * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
27  * Section C3.1 "A64 instruction index by encoding":
28  * AArch64 main encoding table
29  *  Bit position
30  *   28 27 26 25	Encoding Group
31  *   0  0  -  -		Unallocated
32  *   1  0  0  -		Data processing, immediate
33  *   1  0  1  -		Branch, exception generation and system instructions
34  *   -  1  -  0		Loads and stores
35  *   -  1  0  1		Data processing - register
36  *   0  1  1  1		Data processing - SIMD and floating point
37  *   1  1  1  1		Data processing - SIMD and floating point
38  * "-" means "don't care"
39  */
40 enum aarch64_insn_encoding_class {
41 	AARCH64_INSN_CLS_UNKNOWN,	/* UNALLOCATED */
42 	AARCH64_INSN_CLS_DP_IMM,	/* Data processing - immediate */
43 	AARCH64_INSN_CLS_DP_REG,	/* Data processing - register */
44 	AARCH64_INSN_CLS_DP_FPSIMD,	/* Data processing - SIMD and FP */
45 	AARCH64_INSN_CLS_LDST,		/* Loads and stores */
46 	AARCH64_INSN_CLS_BR_SYS,	/* Branch, exception generation and
47 					 * system instructions */
48 };
49 
50 enum aarch64_insn_hint_op {
51 	AARCH64_INSN_HINT_NOP	= 0x0 << 5,
52 	AARCH64_INSN_HINT_YIELD	= 0x1 << 5,
53 	AARCH64_INSN_HINT_WFE	= 0x2 << 5,
54 	AARCH64_INSN_HINT_WFI	= 0x3 << 5,
55 	AARCH64_INSN_HINT_SEV	= 0x4 << 5,
56 	AARCH64_INSN_HINT_SEVL	= 0x5 << 5,
57 };
58 
59 enum aarch64_insn_imm_type {
60 	AARCH64_INSN_IMM_ADR,
61 	AARCH64_INSN_IMM_26,
62 	AARCH64_INSN_IMM_19,
63 	AARCH64_INSN_IMM_16,
64 	AARCH64_INSN_IMM_14,
65 	AARCH64_INSN_IMM_12,
66 	AARCH64_INSN_IMM_9,
67 	AARCH64_INSN_IMM_MAX
68 };
69 
70 enum aarch64_insn_branch_type {
71 	AARCH64_INSN_BRANCH_NOLINK,
72 	AARCH64_INSN_BRANCH_LINK,
73 };
74 
75 #define	__AARCH64_INSN_FUNCS(abbr, mask, val)	\
76 static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
77 { return (code & (mask)) == (val); } \
78 static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
79 { return (val); }
80 
81 __AARCH64_INSN_FUNCS(b,		0xFC000000, 0x14000000)
82 __AARCH64_INSN_FUNCS(bl,	0xFC000000, 0x94000000)
83 __AARCH64_INSN_FUNCS(svc,	0xFFE0001F, 0xD4000001)
84 __AARCH64_INSN_FUNCS(hvc,	0xFFE0001F, 0xD4000002)
85 __AARCH64_INSN_FUNCS(smc,	0xFFE0001F, 0xD4000003)
86 __AARCH64_INSN_FUNCS(brk,	0xFFE0001F, 0xD4200000)
87 __AARCH64_INSN_FUNCS(hint,	0xFFFFF01F, 0xD503201F)
88 
89 #undef	__AARCH64_INSN_FUNCS
90 
91 bool aarch64_insn_is_nop(u32 insn);
92 
93 int aarch64_insn_read(void *addr, u32 *insnp);
94 int aarch64_insn_write(void *addr, u32 insn);
95 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
96 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
97 				  u32 insn, u64 imm);
98 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
99 				enum aarch64_insn_branch_type type);
100 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
101 u32 aarch64_insn_gen_nop(void);
102 
103 bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
104 
105 int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
106 int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt);
107 int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
108 #endif /* __ASSEMBLY__ */
109 
110 #endif	/* __ASM_INSN_H */
111