1 /* 2 * Copyright (C) 2013 Huawei Ltd. 3 * Author: Jiang Liu <liuj97@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 #ifndef __ASM_INSN_H 18 #define __ASM_INSN_H 19 #include <linux/types.h> 20 21 /* A64 instructions are always 32 bits. */ 22 #define AARCH64_INSN_SIZE 4 23 24 /* 25 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a 26 * Section C3.1 "A64 instruction index by encoding": 27 * AArch64 main encoding table 28 * Bit position 29 * 28 27 26 25 Encoding Group 30 * 0 0 - - Unallocated 31 * 1 0 0 - Data processing, immediate 32 * 1 0 1 - Branch, exception generation and system instructions 33 * - 1 - 0 Loads and stores 34 * - 1 0 1 Data processing - register 35 * 0 1 1 1 Data processing - SIMD and floating point 36 * 1 1 1 1 Data processing - SIMD and floating point 37 * "-" means "don't care" 38 */ 39 enum aarch64_insn_encoding_class { 40 AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */ 41 AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */ 42 AARCH64_INSN_CLS_DP_REG, /* Data processing - register */ 43 AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */ 44 AARCH64_INSN_CLS_LDST, /* Loads and stores */ 45 AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and 46 * system instructions */ 47 }; 48 49 enum aarch64_insn_hint_op { 50 AARCH64_INSN_HINT_NOP = 0x0 << 5, 51 AARCH64_INSN_HINT_YIELD = 0x1 << 5, 52 AARCH64_INSN_HINT_WFE = 0x2 << 5, 53 AARCH64_INSN_HINT_WFI = 0x3 << 5, 54 AARCH64_INSN_HINT_SEV = 0x4 << 5, 55 AARCH64_INSN_HINT_SEVL = 0x5 << 5, 56 }; 57 58 #define __AARCH64_INSN_FUNCS(abbr, mask, val) \ 59 static __always_inline bool aarch64_insn_is_##abbr(u32 code) \ 60 { return (code & (mask)) == (val); } \ 61 static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \ 62 { return (val); } 63 64 __AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000) 65 __AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000) 66 __AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001) 67 __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002) 68 __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003) 69 __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000) 70 __AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F) 71 72 #undef __AARCH64_INSN_FUNCS 73 74 bool aarch64_insn_is_nop(u32 insn); 75 76 int aarch64_insn_read(void *addr, u32 *insnp); 77 int aarch64_insn_write(void *addr, u32 insn); 78 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn); 79 bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn); 80 81 int aarch64_insn_patch_text_nosync(void *addr, u32 insn); 82 int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt); 83 int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt); 84 85 #endif /* __ASM_INSN_H */ 86