1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 Huawei Ltd. 4 * Author: Jiang Liu <liuj97@gmail.com> 5 * 6 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com> 7 */ 8 #ifndef __ASM_INSN_H 9 #define __ASM_INSN_H 10 #include <linux/build_bug.h> 11 #include <linux/types.h> 12 13 #include <asm/alternative.h> 14 15 /* A64 instructions are always 32 bits. */ 16 #define AARCH64_INSN_SIZE 4 17 18 #ifndef __ASSEMBLY__ 19 /* 20 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a 21 * Section C3.1 "A64 instruction index by encoding": 22 * AArch64 main encoding table 23 * Bit position 24 * 28 27 26 25 Encoding Group 25 * 0 0 - - Unallocated 26 * 1 0 0 - Data processing, immediate 27 * 1 0 1 - Branch, exception generation and system instructions 28 * - 1 - 0 Loads and stores 29 * - 1 0 1 Data processing - register 30 * 0 1 1 1 Data processing - SIMD and floating point 31 * 1 1 1 1 Data processing - SIMD and floating point 32 * "-" means "don't care" 33 */ 34 enum aarch64_insn_encoding_class { 35 AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */ 36 AARCH64_INSN_CLS_SVE, /* SVE instructions */ 37 AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */ 38 AARCH64_INSN_CLS_DP_REG, /* Data processing - register */ 39 AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */ 40 AARCH64_INSN_CLS_LDST, /* Loads and stores */ 41 AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and 42 * system instructions */ 43 }; 44 45 enum aarch64_insn_hint_cr_op { 46 AARCH64_INSN_HINT_NOP = 0x0 << 5, 47 AARCH64_INSN_HINT_YIELD = 0x1 << 5, 48 AARCH64_INSN_HINT_WFE = 0x2 << 5, 49 AARCH64_INSN_HINT_WFI = 0x3 << 5, 50 AARCH64_INSN_HINT_SEV = 0x4 << 5, 51 AARCH64_INSN_HINT_SEVL = 0x5 << 5, 52 53 AARCH64_INSN_HINT_XPACLRI = 0x07 << 5, 54 AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5, 55 AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5, 56 AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5, 57 AARCH64_INSN_HINT_AUTIB_1716 = 0x0E << 5, 58 AARCH64_INSN_HINT_PACIAZ = 0x18 << 5, 59 AARCH64_INSN_HINT_PACIASP = 0x19 << 5, 60 AARCH64_INSN_HINT_PACIBZ = 0x1A << 5, 61 AARCH64_INSN_HINT_PACIBSP = 0x1B << 5, 62 AARCH64_INSN_HINT_AUTIAZ = 0x1C << 5, 63 AARCH64_INSN_HINT_AUTIASP = 0x1D << 5, 64 AARCH64_INSN_HINT_AUTIBZ = 0x1E << 5, 65 AARCH64_INSN_HINT_AUTIBSP = 0x1F << 5, 66 67 AARCH64_INSN_HINT_ESB = 0x10 << 5, 68 AARCH64_INSN_HINT_PSB = 0x11 << 5, 69 AARCH64_INSN_HINT_TSB = 0x12 << 5, 70 AARCH64_INSN_HINT_CSDB = 0x14 << 5, 71 72 AARCH64_INSN_HINT_BTI = 0x20 << 5, 73 AARCH64_INSN_HINT_BTIC = 0x22 << 5, 74 AARCH64_INSN_HINT_BTIJ = 0x24 << 5, 75 AARCH64_INSN_HINT_BTIJC = 0x26 << 5, 76 }; 77 78 enum aarch64_insn_imm_type { 79 AARCH64_INSN_IMM_ADR, 80 AARCH64_INSN_IMM_26, 81 AARCH64_INSN_IMM_19, 82 AARCH64_INSN_IMM_16, 83 AARCH64_INSN_IMM_14, 84 AARCH64_INSN_IMM_12, 85 AARCH64_INSN_IMM_9, 86 AARCH64_INSN_IMM_7, 87 AARCH64_INSN_IMM_6, 88 AARCH64_INSN_IMM_S, 89 AARCH64_INSN_IMM_R, 90 AARCH64_INSN_IMM_N, 91 AARCH64_INSN_IMM_MAX 92 }; 93 94 enum aarch64_insn_register_type { 95 AARCH64_INSN_REGTYPE_RT, 96 AARCH64_INSN_REGTYPE_RN, 97 AARCH64_INSN_REGTYPE_RT2, 98 AARCH64_INSN_REGTYPE_RM, 99 AARCH64_INSN_REGTYPE_RD, 100 AARCH64_INSN_REGTYPE_RA, 101 AARCH64_INSN_REGTYPE_RS, 102 }; 103 104 enum aarch64_insn_register { 105 AARCH64_INSN_REG_0 = 0, 106 AARCH64_INSN_REG_1 = 1, 107 AARCH64_INSN_REG_2 = 2, 108 AARCH64_INSN_REG_3 = 3, 109 AARCH64_INSN_REG_4 = 4, 110 AARCH64_INSN_REG_5 = 5, 111 AARCH64_INSN_REG_6 = 6, 112 AARCH64_INSN_REG_7 = 7, 113 AARCH64_INSN_REG_8 = 8, 114 AARCH64_INSN_REG_9 = 9, 115 AARCH64_INSN_REG_10 = 10, 116 AARCH64_INSN_REG_11 = 11, 117 AARCH64_INSN_REG_12 = 12, 118 AARCH64_INSN_REG_13 = 13, 119 AARCH64_INSN_REG_14 = 14, 120 AARCH64_INSN_REG_15 = 15, 121 AARCH64_INSN_REG_16 = 16, 122 AARCH64_INSN_REG_17 = 17, 123 AARCH64_INSN_REG_18 = 18, 124 AARCH64_INSN_REG_19 = 19, 125 AARCH64_INSN_REG_20 = 20, 126 AARCH64_INSN_REG_21 = 21, 127 AARCH64_INSN_REG_22 = 22, 128 AARCH64_INSN_REG_23 = 23, 129 AARCH64_INSN_REG_24 = 24, 130 AARCH64_INSN_REG_25 = 25, 131 AARCH64_INSN_REG_26 = 26, 132 AARCH64_INSN_REG_27 = 27, 133 AARCH64_INSN_REG_28 = 28, 134 AARCH64_INSN_REG_29 = 29, 135 AARCH64_INSN_REG_FP = 29, /* Frame pointer */ 136 AARCH64_INSN_REG_30 = 30, 137 AARCH64_INSN_REG_LR = 30, /* Link register */ 138 AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */ 139 AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */ 140 }; 141 142 enum aarch64_insn_special_register { 143 AARCH64_INSN_SPCLREG_SPSR_EL1 = 0xC200, 144 AARCH64_INSN_SPCLREG_ELR_EL1 = 0xC201, 145 AARCH64_INSN_SPCLREG_SP_EL0 = 0xC208, 146 AARCH64_INSN_SPCLREG_SPSEL = 0xC210, 147 AARCH64_INSN_SPCLREG_CURRENTEL = 0xC212, 148 AARCH64_INSN_SPCLREG_DAIF = 0xDA11, 149 AARCH64_INSN_SPCLREG_NZCV = 0xDA10, 150 AARCH64_INSN_SPCLREG_FPCR = 0xDA20, 151 AARCH64_INSN_SPCLREG_DSPSR_EL0 = 0xDA28, 152 AARCH64_INSN_SPCLREG_DLR_EL0 = 0xDA29, 153 AARCH64_INSN_SPCLREG_SPSR_EL2 = 0xE200, 154 AARCH64_INSN_SPCLREG_ELR_EL2 = 0xE201, 155 AARCH64_INSN_SPCLREG_SP_EL1 = 0xE208, 156 AARCH64_INSN_SPCLREG_SPSR_INQ = 0xE218, 157 AARCH64_INSN_SPCLREG_SPSR_ABT = 0xE219, 158 AARCH64_INSN_SPCLREG_SPSR_UND = 0xE21A, 159 AARCH64_INSN_SPCLREG_SPSR_FIQ = 0xE21B, 160 AARCH64_INSN_SPCLREG_SPSR_EL3 = 0xF200, 161 AARCH64_INSN_SPCLREG_ELR_EL3 = 0xF201, 162 AARCH64_INSN_SPCLREG_SP_EL2 = 0xF210 163 }; 164 165 enum aarch64_insn_variant { 166 AARCH64_INSN_VARIANT_32BIT, 167 AARCH64_INSN_VARIANT_64BIT 168 }; 169 170 enum aarch64_insn_condition { 171 AARCH64_INSN_COND_EQ = 0x0, /* == */ 172 AARCH64_INSN_COND_NE = 0x1, /* != */ 173 AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */ 174 AARCH64_INSN_COND_CC = 0x3, /* unsigned < */ 175 AARCH64_INSN_COND_MI = 0x4, /* < 0 */ 176 AARCH64_INSN_COND_PL = 0x5, /* >= 0 */ 177 AARCH64_INSN_COND_VS = 0x6, /* overflow */ 178 AARCH64_INSN_COND_VC = 0x7, /* no overflow */ 179 AARCH64_INSN_COND_HI = 0x8, /* unsigned > */ 180 AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */ 181 AARCH64_INSN_COND_GE = 0xa, /* signed >= */ 182 AARCH64_INSN_COND_LT = 0xb, /* signed < */ 183 AARCH64_INSN_COND_GT = 0xc, /* signed > */ 184 AARCH64_INSN_COND_LE = 0xd, /* signed <= */ 185 AARCH64_INSN_COND_AL = 0xe, /* always */ 186 }; 187 188 enum aarch64_insn_branch_type { 189 AARCH64_INSN_BRANCH_NOLINK, 190 AARCH64_INSN_BRANCH_LINK, 191 AARCH64_INSN_BRANCH_RETURN, 192 AARCH64_INSN_BRANCH_COMP_ZERO, 193 AARCH64_INSN_BRANCH_COMP_NONZERO, 194 }; 195 196 enum aarch64_insn_size_type { 197 AARCH64_INSN_SIZE_8, 198 AARCH64_INSN_SIZE_16, 199 AARCH64_INSN_SIZE_32, 200 AARCH64_INSN_SIZE_64, 201 }; 202 203 enum aarch64_insn_ldst_type { 204 AARCH64_INSN_LDST_LOAD_REG_OFFSET, 205 AARCH64_INSN_LDST_STORE_REG_OFFSET, 206 AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX, 207 AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX, 208 AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX, 209 AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX, 210 AARCH64_INSN_LDST_LOAD_EX, 211 AARCH64_INSN_LDST_STORE_EX, 212 }; 213 214 enum aarch64_insn_adsb_type { 215 AARCH64_INSN_ADSB_ADD, 216 AARCH64_INSN_ADSB_SUB, 217 AARCH64_INSN_ADSB_ADD_SETFLAGS, 218 AARCH64_INSN_ADSB_SUB_SETFLAGS 219 }; 220 221 enum aarch64_insn_movewide_type { 222 AARCH64_INSN_MOVEWIDE_ZERO, 223 AARCH64_INSN_MOVEWIDE_KEEP, 224 AARCH64_INSN_MOVEWIDE_INVERSE 225 }; 226 227 enum aarch64_insn_bitfield_type { 228 AARCH64_INSN_BITFIELD_MOVE, 229 AARCH64_INSN_BITFIELD_MOVE_UNSIGNED, 230 AARCH64_INSN_BITFIELD_MOVE_SIGNED 231 }; 232 233 enum aarch64_insn_data1_type { 234 AARCH64_INSN_DATA1_REVERSE_16, 235 AARCH64_INSN_DATA1_REVERSE_32, 236 AARCH64_INSN_DATA1_REVERSE_64, 237 }; 238 239 enum aarch64_insn_data2_type { 240 AARCH64_INSN_DATA2_UDIV, 241 AARCH64_INSN_DATA2_SDIV, 242 AARCH64_INSN_DATA2_LSLV, 243 AARCH64_INSN_DATA2_LSRV, 244 AARCH64_INSN_DATA2_ASRV, 245 AARCH64_INSN_DATA2_RORV, 246 }; 247 248 enum aarch64_insn_data3_type { 249 AARCH64_INSN_DATA3_MADD, 250 AARCH64_INSN_DATA3_MSUB, 251 }; 252 253 enum aarch64_insn_logic_type { 254 AARCH64_INSN_LOGIC_AND, 255 AARCH64_INSN_LOGIC_BIC, 256 AARCH64_INSN_LOGIC_ORR, 257 AARCH64_INSN_LOGIC_ORN, 258 AARCH64_INSN_LOGIC_EOR, 259 AARCH64_INSN_LOGIC_EON, 260 AARCH64_INSN_LOGIC_AND_SETFLAGS, 261 AARCH64_INSN_LOGIC_BIC_SETFLAGS 262 }; 263 264 enum aarch64_insn_prfm_type { 265 AARCH64_INSN_PRFM_TYPE_PLD, 266 AARCH64_INSN_PRFM_TYPE_PLI, 267 AARCH64_INSN_PRFM_TYPE_PST, 268 }; 269 270 enum aarch64_insn_prfm_target { 271 AARCH64_INSN_PRFM_TARGET_L1, 272 AARCH64_INSN_PRFM_TARGET_L2, 273 AARCH64_INSN_PRFM_TARGET_L3, 274 }; 275 276 enum aarch64_insn_prfm_policy { 277 AARCH64_INSN_PRFM_POLICY_KEEP, 278 AARCH64_INSN_PRFM_POLICY_STRM, 279 }; 280 281 enum aarch64_insn_adr_type { 282 AARCH64_INSN_ADR_TYPE_ADRP, 283 AARCH64_INSN_ADR_TYPE_ADR, 284 }; 285 286 #define __AARCH64_INSN_FUNCS(abbr, mask, val) \ 287 static __always_inline bool aarch64_insn_is_##abbr(u32 code) \ 288 { \ 289 BUILD_BUG_ON(~(mask) & (val)); \ 290 return (code & (mask)) == (val); \ 291 } \ 292 static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \ 293 { \ 294 return (val); \ 295 } 296 297 __AARCH64_INSN_FUNCS(adr, 0x9F000000, 0x10000000) 298 __AARCH64_INSN_FUNCS(adrp, 0x9F000000, 0x90000000) 299 __AARCH64_INSN_FUNCS(prfm, 0x3FC00000, 0x39800000) 300 __AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000) 301 __AARCH64_INSN_FUNCS(store_imm, 0x3FC00000, 0x39000000) 302 __AARCH64_INSN_FUNCS(load_imm, 0x3FC00000, 0x39400000) 303 __AARCH64_INSN_FUNCS(store_pre, 0x3FE00C00, 0x38000C00) 304 __AARCH64_INSN_FUNCS(load_pre, 0x3FE00C00, 0x38400C00) 305 __AARCH64_INSN_FUNCS(store_post, 0x3FE00C00, 0x38000400) 306 __AARCH64_INSN_FUNCS(load_post, 0x3FE00C00, 0x38400400) 307 __AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800) 308 __AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0x38200000) 309 __AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800) 310 __AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000) 311 __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000) 312 __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000) 313 __AARCH64_INSN_FUNCS(load_ex, 0x3F400000, 0x08400000) 314 __AARCH64_INSN_FUNCS(store_ex, 0x3F400000, 0x08000000) 315 __AARCH64_INSN_FUNCS(stp, 0x7FC00000, 0x29000000) 316 __AARCH64_INSN_FUNCS(ldp, 0x7FC00000, 0x29400000) 317 __AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000) 318 __AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000) 319 __AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000) 320 __AARCH64_INSN_FUNCS(ldp_pre, 0x7FC00000, 0x29C00000) 321 __AARCH64_INSN_FUNCS(add_imm, 0x7F000000, 0x11000000) 322 __AARCH64_INSN_FUNCS(adds_imm, 0x7F000000, 0x31000000) 323 __AARCH64_INSN_FUNCS(sub_imm, 0x7F000000, 0x51000000) 324 __AARCH64_INSN_FUNCS(subs_imm, 0x7F000000, 0x71000000) 325 __AARCH64_INSN_FUNCS(movn, 0x7F800000, 0x12800000) 326 __AARCH64_INSN_FUNCS(sbfm, 0x7F800000, 0x13000000) 327 __AARCH64_INSN_FUNCS(bfm, 0x7F800000, 0x33000000) 328 __AARCH64_INSN_FUNCS(movz, 0x7F800000, 0x52800000) 329 __AARCH64_INSN_FUNCS(ubfm, 0x7F800000, 0x53000000) 330 __AARCH64_INSN_FUNCS(movk, 0x7F800000, 0x72800000) 331 __AARCH64_INSN_FUNCS(add, 0x7F200000, 0x0B000000) 332 __AARCH64_INSN_FUNCS(adds, 0x7F200000, 0x2B000000) 333 __AARCH64_INSN_FUNCS(sub, 0x7F200000, 0x4B000000) 334 __AARCH64_INSN_FUNCS(subs, 0x7F200000, 0x6B000000) 335 __AARCH64_INSN_FUNCS(madd, 0x7FE08000, 0x1B000000) 336 __AARCH64_INSN_FUNCS(msub, 0x7FE08000, 0x1B008000) 337 __AARCH64_INSN_FUNCS(udiv, 0x7FE0FC00, 0x1AC00800) 338 __AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00) 339 __AARCH64_INSN_FUNCS(lslv, 0x7FE0FC00, 0x1AC02000) 340 __AARCH64_INSN_FUNCS(lsrv, 0x7FE0FC00, 0x1AC02400) 341 __AARCH64_INSN_FUNCS(asrv, 0x7FE0FC00, 0x1AC02800) 342 __AARCH64_INSN_FUNCS(rorv, 0x7FE0FC00, 0x1AC02C00) 343 __AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400) 344 __AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800) 345 __AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00) 346 __AARCH64_INSN_FUNCS(and, 0x7F200000, 0x0A000000) 347 __AARCH64_INSN_FUNCS(bic, 0x7F200000, 0x0A200000) 348 __AARCH64_INSN_FUNCS(orr, 0x7F200000, 0x2A000000) 349 __AARCH64_INSN_FUNCS(mov_reg, 0x7FE0FFE0, 0x2A0003E0) 350 __AARCH64_INSN_FUNCS(orn, 0x7F200000, 0x2A200000) 351 __AARCH64_INSN_FUNCS(eor, 0x7F200000, 0x4A000000) 352 __AARCH64_INSN_FUNCS(eon, 0x7F200000, 0x4A200000) 353 __AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000) 354 __AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000) 355 __AARCH64_INSN_FUNCS(and_imm, 0x7F800000, 0x12000000) 356 __AARCH64_INSN_FUNCS(orr_imm, 0x7F800000, 0x32000000) 357 __AARCH64_INSN_FUNCS(eor_imm, 0x7F800000, 0x52000000) 358 __AARCH64_INSN_FUNCS(ands_imm, 0x7F800000, 0x72000000) 359 __AARCH64_INSN_FUNCS(extr, 0x7FA00000, 0x13800000) 360 __AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000) 361 __AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000) 362 __AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000) 363 __AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000) 364 __AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000) 365 __AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000) 366 __AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000) 367 __AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001) 368 __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002) 369 __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003) 370 __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000) 371 __AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000) 372 __AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F) 373 __AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000) 374 __AARCH64_INSN_FUNCS(br_auth, 0xFEFFF800, 0xD61F0800) 375 __AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000) 376 __AARCH64_INSN_FUNCS(blr_auth, 0xFEFFF800, 0xD63F0800) 377 __AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000) 378 __AARCH64_INSN_FUNCS(ret_auth, 0xFFFFFBFF, 0xD65F0BFF) 379 __AARCH64_INSN_FUNCS(eret, 0xFFFFFFFF, 0xD69F03E0) 380 __AARCH64_INSN_FUNCS(eret_auth, 0xFFFFFBFF, 0xD69F0BFF) 381 __AARCH64_INSN_FUNCS(mrs, 0xFFF00000, 0xD5300000) 382 __AARCH64_INSN_FUNCS(msr_imm, 0xFFF8F01F, 0xD500401F) 383 __AARCH64_INSN_FUNCS(msr_reg, 0xFFF00000, 0xD5100000) 384 __AARCH64_INSN_FUNCS(dmb, 0xFFFFF0FF, 0xD50330BF) 385 __AARCH64_INSN_FUNCS(dsb_base, 0xFFFFF0FF, 0xD503309F) 386 __AARCH64_INSN_FUNCS(dsb_nxs, 0xFFFFF3FF, 0xD503323F) 387 __AARCH64_INSN_FUNCS(isb, 0xFFFFF0FF, 0xD50330DF) 388 __AARCH64_INSN_FUNCS(sb, 0xFFFFFFFF, 0xD50330FF) 389 __AARCH64_INSN_FUNCS(clrex, 0xFFFFF0FF, 0xD503305F) 390 __AARCH64_INSN_FUNCS(ssbb, 0xFFFFFFFF, 0xD503309F) 391 __AARCH64_INSN_FUNCS(pssbb, 0xFFFFFFFF, 0xD503349F) 392 393 #undef __AARCH64_INSN_FUNCS 394 395 bool aarch64_insn_is_steppable_hint(u32 insn); 396 bool aarch64_insn_is_branch_imm(u32 insn); 397 398 static inline bool aarch64_insn_is_adr_adrp(u32 insn) 399 { 400 return aarch64_insn_is_adr(insn) || aarch64_insn_is_adrp(insn); 401 } 402 403 static inline bool aarch64_insn_is_dsb(u32 insn) 404 { 405 return aarch64_insn_is_dsb_base(insn) || aarch64_insn_is_dsb_nxs(insn); 406 } 407 408 static inline bool aarch64_insn_is_barrier(u32 insn) 409 { 410 return aarch64_insn_is_dmb(insn) || aarch64_insn_is_dsb(insn) || 411 aarch64_insn_is_isb(insn) || aarch64_insn_is_sb(insn) || 412 aarch64_insn_is_clrex(insn) || aarch64_insn_is_ssbb(insn) || 413 aarch64_insn_is_pssbb(insn); 414 } 415 416 static inline bool aarch64_insn_is_store_single(u32 insn) 417 { 418 return aarch64_insn_is_store_imm(insn) || 419 aarch64_insn_is_store_pre(insn) || 420 aarch64_insn_is_store_post(insn); 421 } 422 423 static inline bool aarch64_insn_is_store_pair(u32 insn) 424 { 425 return aarch64_insn_is_stp(insn) || 426 aarch64_insn_is_stp_pre(insn) || 427 aarch64_insn_is_stp_post(insn); 428 } 429 430 static inline bool aarch64_insn_is_load_single(u32 insn) 431 { 432 return aarch64_insn_is_load_imm(insn) || 433 aarch64_insn_is_load_pre(insn) || 434 aarch64_insn_is_load_post(insn); 435 } 436 437 static inline bool aarch64_insn_is_load_pair(u32 insn) 438 { 439 return aarch64_insn_is_ldp(insn) || 440 aarch64_insn_is_ldp_pre(insn) || 441 aarch64_insn_is_ldp_post(insn); 442 } 443 444 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn); 445 bool aarch64_insn_uses_literal(u32 insn); 446 bool aarch64_insn_is_branch(u32 insn); 447 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn); 448 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, 449 u32 insn, u64 imm); 450 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type, 451 u32 insn); 452 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr, 453 enum aarch64_insn_branch_type type); 454 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr, 455 enum aarch64_insn_register reg, 456 enum aarch64_insn_variant variant, 457 enum aarch64_insn_branch_type type); 458 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr, 459 enum aarch64_insn_condition cond); 460 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op); 461 u32 aarch64_insn_gen_nop(void); 462 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg, 463 enum aarch64_insn_branch_type type); 464 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg, 465 enum aarch64_insn_register base, 466 enum aarch64_insn_register offset, 467 enum aarch64_insn_size_type size, 468 enum aarch64_insn_ldst_type type); 469 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1, 470 enum aarch64_insn_register reg2, 471 enum aarch64_insn_register base, 472 int offset, 473 enum aarch64_insn_variant variant, 474 enum aarch64_insn_ldst_type type); 475 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg, 476 enum aarch64_insn_register base, 477 enum aarch64_insn_register state, 478 enum aarch64_insn_size_type size, 479 enum aarch64_insn_ldst_type type); 480 u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result, 481 enum aarch64_insn_register address, 482 enum aarch64_insn_register value, 483 enum aarch64_insn_size_type size); 484 u32 aarch64_insn_gen_stadd(enum aarch64_insn_register address, 485 enum aarch64_insn_register value, 486 enum aarch64_insn_size_type size); 487 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst, 488 enum aarch64_insn_register src, 489 int imm, enum aarch64_insn_variant variant, 490 enum aarch64_insn_adsb_type type); 491 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr, 492 enum aarch64_insn_register reg, 493 enum aarch64_insn_adr_type type); 494 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst, 495 enum aarch64_insn_register src, 496 int immr, int imms, 497 enum aarch64_insn_variant variant, 498 enum aarch64_insn_bitfield_type type); 499 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst, 500 int imm, int shift, 501 enum aarch64_insn_variant variant, 502 enum aarch64_insn_movewide_type type); 503 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst, 504 enum aarch64_insn_register src, 505 enum aarch64_insn_register reg, 506 int shift, 507 enum aarch64_insn_variant variant, 508 enum aarch64_insn_adsb_type type); 509 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst, 510 enum aarch64_insn_register src, 511 enum aarch64_insn_variant variant, 512 enum aarch64_insn_data1_type type); 513 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst, 514 enum aarch64_insn_register src, 515 enum aarch64_insn_register reg, 516 enum aarch64_insn_variant variant, 517 enum aarch64_insn_data2_type type); 518 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst, 519 enum aarch64_insn_register src, 520 enum aarch64_insn_register reg1, 521 enum aarch64_insn_register reg2, 522 enum aarch64_insn_variant variant, 523 enum aarch64_insn_data3_type type); 524 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst, 525 enum aarch64_insn_register src, 526 enum aarch64_insn_register reg, 527 int shift, 528 enum aarch64_insn_variant variant, 529 enum aarch64_insn_logic_type type); 530 u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst, 531 enum aarch64_insn_register src, 532 enum aarch64_insn_variant variant); 533 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type, 534 enum aarch64_insn_variant variant, 535 enum aarch64_insn_register Rn, 536 enum aarch64_insn_register Rd, 537 u64 imm); 538 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant, 539 enum aarch64_insn_register Rm, 540 enum aarch64_insn_register Rn, 541 enum aarch64_insn_register Rd, 542 u8 lsb); 543 u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base, 544 enum aarch64_insn_prfm_type type, 545 enum aarch64_insn_prfm_target target, 546 enum aarch64_insn_prfm_policy policy); 547 s32 aarch64_get_branch_offset(u32 insn); 548 u32 aarch64_set_branch_offset(u32 insn, s32 offset); 549 550 s32 aarch64_insn_adrp_get_offset(u32 insn); 551 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset); 552 553 bool aarch32_insn_is_wide(u32 insn); 554 555 #define A32_RN_OFFSET 16 556 #define A32_RT_OFFSET 12 557 #define A32_RT2_OFFSET 0 558 559 u32 aarch64_insn_extract_system_reg(u32 insn); 560 u32 aarch32_insn_extract_reg_num(u32 insn, int offset); 561 u32 aarch32_insn_mcr_extract_opc2(u32 insn); 562 u32 aarch32_insn_mcr_extract_crm(u32 insn); 563 564 typedef bool (pstate_check_t)(unsigned long); 565 extern pstate_check_t * const aarch32_opcode_cond_checks[16]; 566 567 #endif /* __ASSEMBLY__ */ 568 569 #endif /* __ASM_INSN_H */ 570